Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- HexagonMCDuplexInfo.cpp - Instruction bundle checking --------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This implements duplexing of instructions to reduce code size
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MCTargetDesc/HexagonBaseInfo.h"
14
#include "MCTargetDesc/HexagonMCInstrInfo.h"
15
#include "MCTargetDesc/HexagonMCTargetDesc.h"
16
#include "llvm/ADT/SmallVector.h"
17
#include "llvm/MC/MCExpr.h"
18
#include "llvm/MC/MCInst.h"
19
#include "llvm/MC/MCSubtargetInfo.h"
20
#include "llvm/Support/Debug.h"
21
#include "llvm/Support/ErrorHandling.h"
22
#include "llvm/Support/MathExtras.h"
23
#include "llvm/Support/raw_ostream.h"
24
#include <cassert>
25
#include <cstdint>
26
#include <iterator>
27
#include <map>
28
#include <utility>
29
30
using namespace llvm;
31
using namespace Hexagon;
32
33
#define DEBUG_TYPE "hexagon-mcduplex-info"
34
35
// pair table of subInstructions with opcodes
36
static const std::pair<unsigned, unsigned> opcodeData[] = {
37
    std::make_pair((unsigned)SA1_addi, 0),
38
    std::make_pair((unsigned)SA1_addrx, 6144),
39
    std::make_pair((unsigned)SA1_addsp, 3072),
40
    std::make_pair((unsigned)SA1_and1, 4608),
41
    std::make_pair((unsigned)SA1_clrf, 6768),
42
    std::make_pair((unsigned)SA1_clrfnew, 6736),
43
    std::make_pair((unsigned)SA1_clrt, 6752),
44
    std::make_pair((unsigned)SA1_clrtnew, 6720),
45
    std::make_pair((unsigned)SA1_cmpeqi, 6400),
46
    std::make_pair((unsigned)SA1_combine0i, 7168),
47
    std::make_pair((unsigned)SA1_combine1i, 7176),
48
    std::make_pair((unsigned)SA1_combine2i, 7184),
49
    std::make_pair((unsigned)SA1_combine3i, 7192),
50
    std::make_pair((unsigned)SA1_combinerz, 7432),
51
    std::make_pair((unsigned)SA1_combinezr, 7424),
52
    std::make_pair((unsigned)SA1_dec, 4864),
53
    std::make_pair((unsigned)SA1_inc, 4352),
54
    std::make_pair((unsigned)SA1_seti, 2048),
55
    std::make_pair((unsigned)SA1_setin1, 6656),
56
    std::make_pair((unsigned)SA1_sxtb, 5376),
57
    std::make_pair((unsigned)SA1_sxth, 5120),
58
    std::make_pair((unsigned)SA1_tfr, 4096),
59
    std::make_pair((unsigned)SA1_zxtb, 5888),
60
    std::make_pair((unsigned)SA1_zxth, 5632),
61
    std::make_pair((unsigned)SL1_loadri_io, 0),
62
    std::make_pair((unsigned)SL1_loadrub_io, 4096),
63
    std::make_pair((unsigned)SL2_deallocframe, 7936),
64
    std::make_pair((unsigned)SL2_jumpr31, 8128),
65
    std::make_pair((unsigned)SL2_jumpr31_f, 8133),
66
    std::make_pair((unsigned)SL2_jumpr31_fnew, 8135),
67
    std::make_pair((unsigned)SL2_jumpr31_t, 8132),
68
    std::make_pair((unsigned)SL2_jumpr31_tnew, 8134),
69
    std::make_pair((unsigned)SL2_loadrb_io, 4096),
70
    std::make_pair((unsigned)SL2_loadrd_sp, 7680),
71
    std::make_pair((unsigned)SL2_loadrh_io, 0),
72
    std::make_pair((unsigned)SL2_loadri_sp, 7168),
73
    std::make_pair((unsigned)SL2_loadruh_io, 2048),
74
    std::make_pair((unsigned)SL2_return, 8000),
75
    std::make_pair((unsigned)SL2_return_f, 8005),
76
    std::make_pair((unsigned)SL2_return_fnew, 8007),
77
    std::make_pair((unsigned)SL2_return_t, 8004),
78
    std::make_pair((unsigned)SL2_return_tnew, 8006),
79
    std::make_pair((unsigned)SS1_storeb_io, 4096),
80
    std::make_pair((unsigned)SS1_storew_io, 0),
81
    std::make_pair((unsigned)SS2_allocframe, 7168),
82
    std::make_pair((unsigned)SS2_storebi0, 4608),
83
    std::make_pair((unsigned)SS2_storebi1, 4864),
84
    std::make_pair((unsigned)SS2_stored_sp, 2560),
85
    std::make_pair((unsigned)SS2_storeh_io, 0),
86
    std::make_pair((unsigned)SS2_storew_sp, 2048),
87
    std::make_pair((unsigned)SS2_storewi0, 4096),
88
    std::make_pair((unsigned)SS2_storewi1, 4352)};
89
90
31.9k
bool HexagonMCInstrInfo::isDuplexPairMatch(unsigned Ga, unsigned Gb) {
91
31.9k
  switch (Ga) {
92
31.9k
  case HexagonII::HSIG_None:
93
23.7k
  default:
94
23.7k
    return false;
95
23.7k
  case HexagonII::HSIG_L1:
96
550
    return (Gb == HexagonII::HSIG_L1 || 
Gb == HexagonII::HSIG_A497
);
97
23.7k
  case HexagonII::HSIG_L2:
98
3.78k
    return (Gb == HexagonII::HSIG_L1 || 
Gb == HexagonII::HSIG_L23.77k
||
99
3.78k
            
Gb == HexagonII::HSIG_A3.58k
);
100
23.7k
  case HexagonII::HSIG_S1:
101
90
    return (Gb == HexagonII::HSIG_L1 || 
Gb == HexagonII::HSIG_L280
||
102
90
            
Gb == HexagonII::HSIG_S177
||
Gb == HexagonII::HSIG_A64
);
103
23.7k
  case HexagonII::HSIG_S2:
104
1.11k
    return (Gb == HexagonII::HSIG_L1 || 
Gb == HexagonII::HSIG_L21.09k
||
105
1.11k
            
Gb == HexagonII::HSIG_S11.07k
||
Gb == HexagonII::HSIG_S21.07k
||
106
1.11k
            
Gb == HexagonII::HSIG_A908
);
107
23.7k
  case HexagonII::HSIG_A:
108
2.67k
    return (Gb == HexagonII::HSIG_A);
109
23.7k
  case HexagonII::HSIG_Compound:
110
0
    return (Gb == HexagonII::HSIG_Compound);
111
0
  }
112
0
  return false;
113
0
}
114
115
1.68k
unsigned HexagonMCInstrInfo::iClassOfDuplexPair(unsigned Ga, unsigned Gb) {
116
1.68k
  switch (Ga) {
117
1.68k
  case HexagonII::HSIG_None:
118
0
  default:
119
0
    break;
120
147
  case HexagonII::HSIG_L1:
121
147
    switch (Gb) {
122
147
    default:
123
0
      break;
124
147
    case HexagonII::HSIG_L1:
125
53
      return 0;
126
147
    case HexagonII::HSIG_A:
127
94
      return 0x4;
128
0
    }
129
0
    break;
130
571
  case HexagonII::HSIG_L2:
131
571
    switch (Gb) {
132
571
    default:
133
0
      break;
134
571
    case HexagonII::HSIG_L1:
135
10
      return 0x1;
136
571
    case HexagonII::HSIG_L2:
137
198
      return 0x2;
138
571
    case HexagonII::HSIG_A:
139
363
      return 0x5;
140
0
    }
141
0
    break;
142
41
  case HexagonII::HSIG_S1:
143
41
    switch (Gb) {
144
41
    default:
145
0
      break;
146
41
    case HexagonII::HSIG_L1:
147
10
      return 0x8;
148
41
    case HexagonII::HSIG_L2:
149
3
      return 0x9;
150
41
    case HexagonII::HSIG_S1:
151
13
      return 0xA;
152
41
    case HexagonII::HSIG_A:
153
15
      return 0x6;
154
0
    }
155
0
    break;
156
519
  case HexagonII::HSIG_S2:
157
519
    switch (Gb) {
158
519
    default:
159
0
      break;
160
519
    case HexagonII::HSIG_L1:
161
18
      return 0xC;
162
519
    case HexagonII::HSIG_L2:
163
21
      return 0xD;
164
519
    case HexagonII::HSIG_S1:
165
0
      return 0xB;
166
519
    case HexagonII::HSIG_S2:
167
167
      return 0xE;
168
519
    case HexagonII::HSIG_A:
169
313
      return 0x7;
170
0
    }
171
0
    break;
172
409
  case HexagonII::HSIG_A:
173
409
    switch (Gb) {
174
409
    default:
175
0
      break;
176
409
    case HexagonII::HSIG_A:
177
409
      return 0x3;
178
0
    }
179
0
    break;
180
0
  case HexagonII::HSIG_Compound:
181
0
    switch (Gb) {
182
0
    case HexagonII::HSIG_Compound:
183
0
      return 0xFFFFFFFF;
184
0
    }
185
0
    break;
186
0
  }
187
0
  return 0xFFFFFFFF;
188
0
}
189
190
74.4k
unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
191
74.4k
  unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
192
74.4k
193
74.4k
  switch (MCI.getOpcode()) {
194
74.4k
  default:
195
42.6k
    return HexagonII::HSIG_None;
196
74.4k
  //
197
74.4k
  // Group L1:
198
74.4k
  //
199
74.4k
  // Rd = memw(Rs+#u4:2)
200
74.4k
  // Rd = memub(Rs+#u4:0)
201
74.4k
  case Hexagon::L2_loadri_io:
202
1.95k
    DstReg = MCI.getOperand(0).getReg();
203
1.95k
    SrcReg = MCI.getOperand(1).getReg();
204
1.95k
    // Special case this one from Group L2.
205
1.95k
    // Rd = memw(r29+#u5:2)
206
1.95k
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
207
1.51k
      if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
208
1.51k
          Hexagon::R29 == SrcReg && 
inRange<5, 2>(MCI, 2)458
) {
209
417
        return HexagonII::HSIG_L2;
210
417
      }
211
1.09k
      // Rd = memw(Rs+#u4:2)
212
1.09k
      if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
213
1.09k
          
inRange<4, 2>(MCI, 2)950
) {
214
912
        return HexagonII::HSIG_L1;
215
912
      }
216
630
    }
217
630
    break;
218
835
  case Hexagon::L2_loadrub_io:
219
835
    // Rd = memub(Rs+#u4:0)
220
835
    DstReg = MCI.getOperand(0).getReg();
221
835
    SrcReg = MCI.getOperand(1).getReg();
222
835
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
223
835
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)699
&&
224
835
        
inRange<4>(MCI, 2)655
) {
225
381
      return HexagonII::HSIG_L1;
226
381
    }
227
454
    break;
228
454
  //
229
454
  // Group L2:
230
454
  //
231
454
  // Rd = memh/memuh(Rs+#u3:1)
232
454
  // Rd = memb(Rs+#u3:0)
233
454
  // Rd = memw(r29+#u5:2) - Handled above.
234
454
  // Rdd = memd(r29+#u5:3)
235
454
  // deallocframe
236
454
  // [if ([!]p0[.new])] dealloc_return
237
454
  // [if ([!]p0[.new])] jumpr r31
238
454
  case Hexagon::L2_loadrh_io:
239
408
  case Hexagon::L2_loadruh_io:
240
408
    // Rd = memh/memuh(Rs+#u3:1)
241
408
    DstReg = MCI.getOperand(0).getReg();
242
408
    SrcReg = MCI.getOperand(1).getReg();
243
408
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
244
408
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)318
&&
245
408
        
inRange<3, 1>(MCI, 2)264
) {
246
246
      return HexagonII::HSIG_L2;
247
246
    }
248
162
    break;
249
162
  case Hexagon::L2_loadrb_io:
250
38
    // Rd = memb(Rs+#u3:0)
251
38
    DstReg = MCI.getOperand(0).getReg();
252
38
    SrcReg = MCI.getOperand(1).getReg();
253
38
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
254
38
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)32
&&
255
38
        
inRange<3>(MCI, 2)26
) {
256
22
      return HexagonII::HSIG_L2;
257
22
    }
258
16
    break;
259
1.58k
  case Hexagon::L2_loadrd_io:
260
1.58k
    // Rdd = memd(r29+#u5:3)
261
1.58k
    DstReg = MCI.getOperand(0).getReg();
262
1.58k
    SrcReg = MCI.getOperand(1).getReg();
263
1.58k
    if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
264
1.58k
        
HexagonMCInstrInfo::isIntReg(SrcReg)1.41k
&&
Hexagon::R29 == SrcReg1.41k
&&
265
1.58k
        
inRange<5, 3>(MCI, 2)1.22k
) {
266
1.20k
      return HexagonII::HSIG_L2;
267
1.20k
    }
268
379
    break;
269
379
270
379
  case Hexagon::L4_return:
271
306
  case Hexagon::L2_deallocframe:
272
306
    return HexagonII::HSIG_L2;
273
306
274
5.57k
  case Hexagon::EH_RETURN_JMPR:
275
5.57k
  case Hexagon::J2_jumpr:
276
5.57k
  case Hexagon::PS_jmpret:
277
5.57k
    // jumpr r31
278
5.57k
    // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0.
279
5.57k
    DstReg = MCI.getOperand(0).getReg();
280
5.57k
    if (Hexagon::R31 == DstReg)
281
5.57k
      return HexagonII::HSIG_L2;
282
0
    break;
283
0
284
321
  case Hexagon::J2_jumprt:
285
321
  case Hexagon::J2_jumprf:
286
321
  case Hexagon::J2_jumprtnew:
287
321
  case Hexagon::J2_jumprfnew:
288
321
  case Hexagon::J2_jumprtnewpt:
289
321
  case Hexagon::J2_jumprfnewpt:
290
321
  case Hexagon::PS_jmprett:
291
321
  case Hexagon::PS_jmpretf:
292
321
  case Hexagon::PS_jmprettnew:
293
321
  case Hexagon::PS_jmpretfnew:
294
321
  case Hexagon::PS_jmprettnewpt:
295
321
  case Hexagon::PS_jmpretfnewpt:
296
321
    DstReg = MCI.getOperand(1).getReg();
297
321
    SrcReg = MCI.getOperand(0).getReg();
298
321
    // [if ([!]p0[.new])] jumpr r31
299
321
    if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) &&
300
321
        
(Hexagon::R31 == DstReg)307
) {
301
307
      return HexagonII::HSIG_L2;
302
307
    }
303
14
    break;
304
64
  case Hexagon::L4_return_t:
305
64
  case Hexagon::L4_return_f:
306
64
  case Hexagon::L4_return_tnew_pnt:
307
64
  case Hexagon::L4_return_fnew_pnt:
308
64
  case Hexagon::L4_return_tnew_pt:
309
64
  case Hexagon::L4_return_fnew_pt:
310
64
    // [if ([!]p0[.new])] dealloc_return
311
64
    SrcReg = MCI.getOperand(1).getReg();
312
64
    if (Hexagon::P0 == SrcReg) {
313
56
      return HexagonII::HSIG_L2;
314
56
    }
315
8
    break;
316
8
  //
317
8
  // Group S1:
318
8
  //
319
8
  // memw(Rs+#u4:2) = Rt
320
8
  // memb(Rs+#u4:0) = Rt
321
1.05k
  case Hexagon::S2_storeri_io:
322
1.05k
    // Special case this one from Group S2.
323
1.05k
    // memw(r29+#u5:2) = Rt
324
1.05k
    Src1Reg = MCI.getOperand(0).getReg();
325
1.05k
    Src2Reg = MCI.getOperand(2).getReg();
326
1.05k
    if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&
327
1.05k
        HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
328
1.05k
        
Hexagon::R29 == Src1Reg883
&&
inRange<5, 2>(MCI, 1)648
) {
329
467
      return HexagonII::HSIG_S2;
330
467
    }
331
591
    // memw(Rs+#u4:2) = Rt
332
591
    if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
333
591
        
HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)382
&&
334
591
        
inRange<4, 2>(MCI, 1)235
) {
335
165
      return HexagonII::HSIG_S1;
336
165
    }
337
426
    break;
338
426
  case Hexagon::S2_storerb_io:
339
289
    // memb(Rs+#u4:0) = Rt
340
289
    Src1Reg = MCI.getOperand(0).getReg();
341
289
    Src2Reg = MCI.getOperand(2).getReg();
342
289
    if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
343
289
        
HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)262
&&
344
289
        
inRange<4>(MCI, 1)262
) {
345
59
      return HexagonII::HSIG_S1;
346
59
    }
347
230
    break;
348
230
  //
349
230
  // Group S2:
350
230
  //
351
230
  // memh(Rs+#u3:1) = Rt
352
230
  // memw(r29+#u5:2) = Rt
353
230
  // memd(r29+#s6:3) = Rtt
354
230
  // memw(Rs+#u4:2) = #U1
355
230
  // memb(Rs+#u4) = #U1
356
230
  // allocframe(#u5:3)
357
230
  case Hexagon::S2_storerh_io:
358
166
    // memh(Rs+#u3:1) = Rt
359
166
    Src1Reg = MCI.getOperand(0).getReg();
360
166
    Src2Reg = MCI.getOperand(2).getReg();
361
166
    if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
362
166
        
HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)132
&&
363
166
        
inRange<3, 1>(MCI, 1)117
) {
364
61
      return HexagonII::HSIG_S2;
365
61
    }
366
105
    break;
367
1.30k
  case Hexagon::S2_storerd_io:
368
1.30k
    // memd(r29+#s6:3) = Rtt
369
1.30k
    Src1Reg = MCI.getOperand(0).getReg();
370
1.30k
    Src2Reg = MCI.getOperand(2).getReg();
371
1.30k
    if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) &&
372
1.30k
        
HexagonMCInstrInfo::isIntReg(Src1Reg)1.24k
&&
Hexagon::R29 == Src1Reg1.24k
&&
373
1.30k
        
inSRange<6, 3>(MCI, 1)1.11k
) {
374
1.09k
      return HexagonII::HSIG_S2;
375
1.09k
    }
376
208
    break;
377
301
  case Hexagon::S4_storeiri_io:
378
301
    // memw(Rs+#u4:2) = #U1
379
301
    Src1Reg = MCI.getOperand(0).getReg();
380
301
    if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
381
301
        
inRange<4, 2>(MCI, 1)183
&&
inRange<1>(MCI, 2)177
) {
382
148
      return HexagonII::HSIG_S2;
383
148
    }
384
153
    break;
385
153
  case Hexagon::S4_storeirb_io:
386
91
    // memb(Rs+#u4) = #U1
387
91
    Src1Reg = MCI.getOperand(0).getReg();
388
91
    if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
389
91
        
inRange<4>(MCI, 1)79
&&
inRange<1>(MCI, 2)77
) {
390
45
      return HexagonII::HSIG_S2;
391
45
    }
392
46
    break;
393
957
  case Hexagon::S2_allocframe:
394
957
    if (inRange<5, 3>(MCI, 2))
395
852
      return HexagonII::HSIG_S2;
396
105
    break;
397
105
  //
398
105
  // Group A:
399
105
  //
400
105
  // Rx = add(Rx,#s7)
401
105
  // Rd = Rs
402
105
  // Rd = #u6
403
105
  // Rd = #-1
404
105
  // if ([!]P0[.new]) Rd = #0
405
105
  // Rd = add(r29,#u6:2)
406
105
  // Rx = add(Rx,Rs)
407
105
  // P0 = cmp.eq(Rs,#u2)
408
105
  // Rdd = combine(#0,Rs)
409
105
  // Rdd = combine(Rs,#0)
410
105
  // Rdd = combine(#u2,#U2)
411
105
  // Rd = add(Rs,#1)
412
105
  // Rd = add(Rs,#-1)
413
105
  // Rd = sxth/sxtb/zxtb/zxth(Rs)
414
105
  // Rd = and(Rs,#1)
415
5.22k
  case Hexagon::A2_addi:
416
5.22k
    DstReg = MCI.getOperand(0).getReg();
417
5.22k
    SrcReg = MCI.getOperand(1).getReg();
418
5.22k
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
419
3.61k
      // Rd = add(r29,#u6:2)
420
3.61k
      if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
421
3.61k
          
inRange<6, 2>(MCI, 2)564
) {
422
435
        return HexagonII::HSIG_A;
423
435
      }
424
3.18k
      // Rx = add(Rx,#s7)
425
3.18k
      if (DstReg == SrcReg) {
426
1.32k
        return HexagonII::HSIG_A;
427
1.32k
      }
428
1.85k
      // Rd = add(Rs,#1)
429
1.85k
      // Rd = add(Rs,#-1)
430
1.85k
      if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
431
1.85k
          
(1.54k
minConstant(MCI, 2) == 11.54k
||
minConstant(MCI, 2) == -11.34k
)) {
432
666
        return HexagonII::HSIG_A;
433
666
      }
434
2.79k
    }
435
2.79k
    break;
436
2.79k
  case Hexagon::A2_add:
437
1.45k
    // Rx = add(Rx,Rs)
438
1.45k
    DstReg = MCI.getOperand(0).getReg();
439
1.45k
    Src1Reg = MCI.getOperand(1).getReg();
440
1.45k
    Src2Reg = MCI.getOperand(2).getReg();
441
1.45k
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && 
(DstReg == Src1Reg)1.06k
&&
442
1.45k
        
HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)294
) {
443
245
      return HexagonII::HSIG_A;
444
245
    }
445
1.21k
    break;
446
1.21k
  case Hexagon::A2_andir:
447
429
    DstReg = MCI.getOperand(0).getReg();
448
429
    SrcReg = MCI.getOperand(1).getReg();
449
429
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
450
429
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)171
&&
451
429
        
(141
minConstant(MCI, 2) == 1141
||
minConstant(MCI, 2) == 255131
)) {
452
93
      return HexagonII::HSIG_A;
453
93
    }
454
336
    break;
455
2.51k
  case Hexagon::A2_tfr:
456
2.51k
    // Rd = Rs
457
2.51k
    DstReg = MCI.getOperand(0).getReg();
458
2.51k
    SrcReg = MCI.getOperand(1).getReg();
459
2.51k
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
460
2.51k
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)1.88k
) {
461
1.72k
      return HexagonII::HSIG_A;
462
1.72k
    }
463
786
    break;
464
5.20k
  case Hexagon::A2_tfrsi:
465
5.20k
    DstReg = MCI.getOperand(0).getReg();
466
5.20k
467
5.20k
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
468
5.00k
      return HexagonII::HSIG_A;
469
5.00k
    }
470
201
    break;
471
605
  case Hexagon::C2_cmoveit:
472
605
  case Hexagon::C2_cmovenewit:
473
605
  case Hexagon::C2_cmoveif:
474
605
  case Hexagon::C2_cmovenewif:
475
605
    // if ([!]P0[.new]) Rd = #0
476
605
    // Actual form:
477
605
    // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
478
605
    DstReg = MCI.getOperand(0).getReg();  // Rd
479
605
    PredReg = MCI.getOperand(1).getReg(); // P0
480
605
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
481
605
        
Hexagon::P0 == PredReg569
&&
minConstant(MCI, 2) == 0503
) {
482
259
      return HexagonII::HSIG_A;
483
259
    }
484
346
    break;
485
360
  case Hexagon::C2_cmpeqi:
486
360
    // P0 = cmp.eq(Rs,#u2)
487
360
    DstReg = MCI.getOperand(0).getReg();
488
360
    SrcReg = MCI.getOperand(1).getReg();
489
360
    if (Hexagon::P0 == DstReg &&
490
360
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)294
&&
491
360
        
inRange<2>(MCI, 2)278
) {
492
232
      return HexagonII::HSIG_A;
493
232
    }
494
128
    break;
495
477
  case Hexagon::A2_combineii:
496
477
  case Hexagon::A4_combineii:
497
477
    // Rdd = combine(#u2,#U2)
498
477
    DstReg = MCI.getOperand(0).getReg();
499
477
    if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
500
477
        
inRange<2>(MCI, 1)446
&&
inRange<2>(MCI, 2)357
) {
501
321
      return HexagonII::HSIG_A;
502
321
    }
503
156
    break;
504
156
  case Hexagon::A4_combineri:
505
16
    // Rdd = combine(Rs,#0)
506
16
    DstReg = MCI.getOperand(0).getReg();
507
16
    SrcReg = MCI.getOperand(1).getReg();
508
16
    if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
509
16
        HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
510
16
        minConstant(MCI, 2) == 0) {
511
14
      return HexagonII::HSIG_A;
512
14
    }
513
2
    break;
514
58
  case Hexagon::A4_combineir:
515
58
    // Rdd = combine(#0,Rs)
516
58
    DstReg = MCI.getOperand(0).getReg();
517
58
    SrcReg = MCI.getOperand(2).getReg();
518
58
    if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
519
58
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)52
&&
520
58
        
minConstant(MCI, 1) == 052
) {
521
38
      return HexagonII::HSIG_A;
522
38
    }
523
20
    break;
524
186
  case Hexagon::A2_sxtb:
525
186
  case Hexagon::A2_sxth:
526
186
  case Hexagon::A2_zxtb:
527
186
  case Hexagon::A2_zxth:
528
186
    // Rd = sxth/sxtb/zxtb/zxth(Rs)
529
186
    DstReg = MCI.getOperand(0).getReg();
530
186
    SrcReg = MCI.getOperand(1).getReg();
531
186
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
532
186
        
HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)152
) {
533
138
      return HexagonII::HSIG_A;
534
138
    }
535
48
    break;
536
8.96k
  }
537
8.96k
538
8.96k
  return HexagonII::HSIG_None;
539
8.96k
}
540
541
3.99k
bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) {
542
3.99k
  unsigned DstReg, SrcReg;
543
3.99k
  switch (potentialDuplex.getOpcode()) {
544
3.99k
  case Hexagon::A2_addi:
545
360
    // testing for case of: Rx = add(Rx,#s7)
546
360
    DstReg = potentialDuplex.getOperand(0).getReg();
547
360
    SrcReg = potentialDuplex.getOperand(1).getReg();
548
360
    if (DstReg == SrcReg && 
HexagonMCInstrInfo::isIntRegForSubInst(DstReg)185
) {
549
185
      int64_t Value;
550
185
      if (!potentialDuplex.getOperand(2).getExpr()->evaluateAsAbsolute(Value))
551
2
        return true;
552
183
      if (!isShiftedInt<7, 0>(Value))
553
33
        return true;
554
325
    }
555
325
    break;
556
910
  case Hexagon::A2_tfrsi:
557
910
    DstReg = potentialDuplex.getOperand(0).getReg();
558
910
559
910
    if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
560
910
      int64_t Value;
561
910
      if (!potentialDuplex.getOperand(1).getExpr()->evaluateAsAbsolute(Value))
562
105
        return true;
563
805
      // Check for case of Rd = #-1.
564
805
      if (Value == -1)
565
12
        return false;
566
793
      // Check for case of Rd = #u6.
567
793
      if (!isShiftedUInt<6, 0>(Value))
568
224
        return true;
569
569
    }
570
569
    break;
571
2.72k
  default:
572
2.72k
    break;
573
3.62k
  }
574
3.62k
  return false;
575
3.62k
}
576
577
/// non-Symmetrical. See if these two instructions are fit for duplex pair.
578
bool HexagonMCInstrInfo::isOrderedDuplexPair(MCInstrInfo const &MCII,
579
                                             MCInst const &MIa, bool ExtendedA,
580
                                             MCInst const &MIb, bool ExtendedB,
581
                                             bool bisReversable,
582
40.9k
                                             MCSubtargetInfo const &STI) {
583
40.9k
  // Slot 1 cannot be extended in duplexes PRM 10.5
584
40.9k
  if (ExtendedA)
585
3.99k
    return false;
586
36.9k
  // Only A2_addi and A2_tfrsi can be extended in duplex form PRM 10.5
587
36.9k
  if (ExtendedB) {
588
3.77k
    unsigned Opcode = MIb.getOpcode();
589
3.77k
    if ((Opcode != Hexagon::A2_addi) && 
(Opcode != Hexagon::A2_tfrsi)3.71k
)
590
1.39k
      return false;
591
35.5k
  }
592
35.5k
  unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa),
593
35.5k
           MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb);
594
35.5k
595
35.5k
  static std::map<unsigned, unsigned> subinstOpcodeMap(std::begin(opcodeData),
596
35.5k
                                                       std::end(opcodeData));
597
35.5k
598
35.5k
  // If a duplex contains 2 insns in the same group, the insns must be
599
35.5k
  // ordered such that the numerically smaller opcode is in slot 1.
600
35.5k
  if ((MIaG != HexagonII::HSIG_None) && 
(MIaG == MIbG)8.67k
&&
bisReversable1.11k
) {
601
938
    MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa);
602
938
    MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb);
603
938
604
938
    unsigned zeroedSubInstS0 =
605
938
        subinstOpcodeMap.find(SubInst0.getOpcode())->second;
606
938
    unsigned zeroedSubInstS1 =
607
938
        subinstOpcodeMap.find(SubInst1.getOpcode())->second;
608
938
609
938
    if (zeroedSubInstS0 < zeroedSubInstS1)
610
130
      // subinstS0 (maps to slot 0) must be greater than
611
130
      // subinstS1 (maps to slot 1)
612
130
      return false;
613
35.3k
  }
614
35.3k
615
35.3k
  // allocframe must always be in slot 0
616
35.3k
  if (MIb.getOpcode() == Hexagon::S2_allocframe)
617
215
    return false;
618
35.1k
619
35.1k
  if ((MIaG != HexagonII::HSIG_None) && 
(MIbG != HexagonII::HSIG_None)8.53k
) {
620
2.05k
    // Prevent 2 instructions with extenders from duplexing
621
2.05k
    // Note that MIb (slot1) can be extended and MIa (slot0)
622
2.05k
    //   can never be extended
623
2.05k
    if (subInstWouldBeExtended(MIa))
624
106
      return false;
625
1.94k
626
1.94k
    // If duplexing produces an extender, but the original did not
627
1.94k
    //   have an extender, do not duplex.
628
1.94k
    if (subInstWouldBeExtended(MIb) && 
!ExtendedB258
)
629
95
      return false;
630
34.9k
  }
631
34.9k
632
34.9k
  // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
633
34.9k
  if (MIbG == HexagonII::HSIG_L2) {
634
3.49k
    if ((MIb.getNumOperands() > 1) && 
MIb.getOperand(1).isReg()871
&&
635
3.49k
        
(MIb.getOperand(1).getReg() == Hexagon::R31)871
)
636
129
      return false;
637
3.36k
    if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() &&
638
3.36k
        (MIb.getOperand(0).getReg() == Hexagon::R31))
639
2.62k
      return false;
640
32.2k
  }
641
32.2k
642
32.2k
  if (STI.getCPU().equals_lower("hexagonv5") ||
643
32.2k
      
STI.getCPU().equals_lower("hexagonv55")28.6k
||
644
32.2k
      
STI.getCPU().equals_lower("hexagonv60")25.6k
) {
645
24.1k
    // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb);
646
24.1k
    //   therefore, not duplexable if slot 1 is a store, and slot 0 is not.
647
24.1k
    if ((MIbG == HexagonII::HSIG_S1) || 
(MIbG == HexagonII::HSIG_S2)24.1k
) {
648
401
      if ((MIaG != HexagonII::HSIG_S1) && 
(MIaG != HexagonII::HSIG_S2)394
)
649
294
        return false;
650
31.9k
    }
651
24.1k
  }
652
31.9k
653
31.9k
  return (isDuplexPairMatch(MIaG, MIbG));
654
31.9k
}
655
656
/// Symmetrical. See if these two instructions are fit for duplex pair.
657
0
bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
658
0
  unsigned MIaG = getDuplexCandidateGroup(MIa),
659
0
           MIbG = getDuplexCandidateGroup(MIb);
660
0
  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
661
0
}
662
663
inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
664
9.15k
                          unsigned opNum) {
665
9.15k
  if (Inst.getOperand(opNum).isReg()) {
666
5.61k
    switch (Inst.getOperand(opNum).getReg()) {
667
5.61k
    default:
668
0
      llvm_unreachable("Not Duplexable Register");
669
5.61k
      
break0
;
670
5.61k
    case Hexagon::R0:
671
5.61k
    case Hexagon::R1:
672
5.61k
    case Hexagon::R2:
673
5.61k
    case Hexagon::R3:
674
5.61k
    case Hexagon::R4:
675
5.61k
    case Hexagon::R5:
676
5.61k
    case Hexagon::R6:
677
5.61k
    case Hexagon::R7:
678
5.61k
    case Hexagon::D0:
679
5.61k
    case Hexagon::D1:
680
5.61k
    case Hexagon::D2:
681
5.61k
    case Hexagon::D3:
682
5.61k
    case Hexagon::R16:
683
5.61k
    case Hexagon::R17:
684
5.61k
    case Hexagon::R18:
685
5.61k
    case Hexagon::R19:
686
5.61k
    case Hexagon::R20:
687
5.61k
    case Hexagon::R21:
688
5.61k
    case Hexagon::R22:
689
5.61k
    case Hexagon::R23:
690
5.61k
    case Hexagon::D8:
691
5.61k
    case Hexagon::D9:
692
5.61k
    case Hexagon::D10:
693
5.61k
    case Hexagon::D11:
694
5.61k
    case Hexagon::P0:
695
5.61k
      subInstPtr.addOperand(Inst.getOperand(opNum));
696
5.61k
      break;
697
3.53k
    }
698
3.53k
  } else
699
3.53k
    subInstPtr.addOperand(Inst.getOperand(opNum));
700
9.15k
}
701
702
4.63k
MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
703
4.63k
  MCInst Result;
704
4.63k
  bool Absolute;
705
4.63k
  int64_t Value;
706
4.63k
  switch (Inst.getOpcode()) {
707
4.63k
  default:
708
0
    // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
709
0
    llvm_unreachable("Unimplemented subinstruction \n");
710
4.63k
    
break0
;
711
4.63k
  case Hexagon::A2_addi:
712
585
    Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
713
585
    if (Absolute) {
714
581
      if (Value == 1) {
715
114
        Result.setOpcode(Hexagon::SA1_inc);
716
114
        addOps(Result, Inst, 0);
717
114
        addOps(Result, Inst, 1);
718
114
        break;
719
114
      } //  1,2 SUBInst $Rd = add($Rs, #1)
720
467
      if (Value == -1) {
721
178
        Result.setOpcode(Hexagon::SA1_dec);
722
178
        addOps(Result, Inst, 0);
723
178
        addOps(Result, Inst, 1);
724
178
        addOps(Result, Inst, 2);
725
178
        break;
726
178
      } //  1,2 SUBInst $Rd = add($Rs,#-1)
727
289
      if (Inst.getOperand(1).getReg() == Hexagon::R29) {
728
101
        Result.setOpcode(Hexagon::SA1_addsp);
729
101
        addOps(Result, Inst, 0);
730
101
        addOps(Result, Inst, 2);
731
101
        break;
732
101
      } //  1,3 SUBInst $Rd = add(r29, #$u6_2)
733
192
    }
734
192
    Result.setOpcode(Hexagon::SA1_addi);
735
192
    addOps(Result, Inst, 0);
736
192
    addOps(Result, Inst, 1);
737
192
    addOps(Result, Inst, 2);
738
192
    break; //    1,2,3 SUBInst $Rx = add($Rx, #$s7)
739
192
  case Hexagon::A2_add:
740
54
    Result.setOpcode(Hexagon::SA1_addrx);
741
54
    addOps(Result, Inst, 0);
742
54
    addOps(Result, Inst, 1);
743
54
    addOps(Result, Inst, 2);
744
54
    break; //    1,2,3 SUBInst $Rx = add($_src_, $Rs)
745
230
  case Hexagon::S2_allocframe:
746
230
    Result.setOpcode(Hexagon::SS2_allocframe);
747
230
    addOps(Result, Inst, 2);
748
230
    break; //    1 SUBInst allocframe(#$u5_3)
749
192
  case Hexagon::A2_andir:
750
30
    if (minConstant(Inst, 2) == 255) {
751
24
      Result.setOpcode(Hexagon::SA1_zxtb);
752
24
      addOps(Result, Inst, 0);
753
24
      addOps(Result, Inst, 1);
754
24
      break; //    1,2    $Rd = and($Rs, #255)
755
24
    } else {
756
6
      Result.setOpcode(Hexagon::SA1_and1);
757
6
      addOps(Result, Inst, 0);
758
6
      addOps(Result, Inst, 1);
759
6
      break; //    1,2 SUBInst $Rd = and($Rs, #1)
760
6
    }
761
65
  case Hexagon::C2_cmpeqi:
762
65
    Result.setOpcode(Hexagon::SA1_cmpeqi);
763
65
    addOps(Result, Inst, 1);
764
65
    addOps(Result, Inst, 2);
765
65
    break; //    2,3 SUBInst p0 = cmp.eq($Rs, #$u2)
766
108
  case Hexagon::A4_combineii:
767
108
  case Hexagon::A2_combineii:
768
108
    Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
769
108
    assert(Absolute);(void)Absolute;
770
108
    if (Value == 1) {
771
9
      Result.setOpcode(Hexagon::SA1_combine1i);
772
9
      addOps(Result, Inst, 0);
773
9
      addOps(Result, Inst, 2);
774
9
      break; //  1,3 SUBInst $Rdd = combine(#1, #$u2)
775
9
    }
776
99
    if (Value == 3) {
777
4
      Result.setOpcode(Hexagon::SA1_combine3i);
778
4
      addOps(Result, Inst, 0);
779
4
      addOps(Result, Inst, 2);
780
4
      break; //  1,3 SUBInst $Rdd = combine(#3, #$u2)
781
4
    }
782
95
    if (Value == 0) {
783
84
      Result.setOpcode(Hexagon::SA1_combine0i);
784
84
      addOps(Result, Inst, 0);
785
84
      addOps(Result, Inst, 2);
786
84
      break; //  1,3 SUBInst $Rdd = combine(#0, #$u2)
787
84
    }
788
11
    if (Value == 2) {
789
11
      Result.setOpcode(Hexagon::SA1_combine2i);
790
11
      addOps(Result, Inst, 0);
791
11
      addOps(Result, Inst, 2);
792
11
      break; //  1,3 SUBInst $Rdd = combine(#2, #$u2)
793
11
    }
794
0
    break;
795
12
  case Hexagon::A4_combineir:
796
12
    Result.setOpcode(Hexagon::SA1_combinezr);
797
12
    addOps(Result, Inst, 0);
798
12
    addOps(Result, Inst, 2);
799
12
    break; //    1,3 SUBInst $Rdd = combine(#0, $Rs)
800
2
  case Hexagon::A4_combineri:
801
2
    Result.setOpcode(Hexagon::SA1_combinerz);
802
2
    addOps(Result, Inst, 0);
803
2
    addOps(Result, Inst, 1);
804
2
    break; //    1,2 SUBInst $Rdd = combine($Rs, #0)
805
6
  case Hexagon::L4_return_tnew_pnt:
806
6
  case Hexagon::L4_return_tnew_pt:
807
6
    Result.setOpcode(Hexagon::SL2_return_tnew);
808
6
    break; //    none  SUBInst if (p0.new) dealloc_return:nt
809
6
  case Hexagon::L4_return_fnew_pnt:
810
1
  case Hexagon::L4_return_fnew_pt:
811
1
    Result.setOpcode(Hexagon::SL2_return_fnew);
812
1
    break; //    none  SUBInst if (!p0.new) dealloc_return:nt
813
1
  case Hexagon::L4_return_f:
814
0
    Result.setOpcode(Hexagon::SL2_return_f);
815
0
    break; //    none  SUBInst if (!p0) dealloc_return
816
1
  case Hexagon::L4_return_t:
817
0
    Result.setOpcode(Hexagon::SL2_return_t);
818
0
    break; //    none  SUBInst if (p0) dealloc_return
819
157
  case Hexagon::L4_return:
820
157
    Result.setOpcode(Hexagon::SL2_return);
821
157
    break; //    none  SUBInst dealloc_return
822
25
  case Hexagon::L2_deallocframe:
823
25
    Result.setOpcode(Hexagon::SL2_deallocframe);
824
25
    break; //    none  SUBInst deallocframe
825
173
  case Hexagon::EH_RETURN_JMPR:
826
173
  case Hexagon::J2_jumpr:
827
173
  case Hexagon::PS_jmpret:
828
173
    Result.setOpcode(Hexagon::SL2_jumpr31);
829
173
    break; //    none  SUBInst jumpr r31
830
173
  case Hexagon::J2_jumprf:
831
0
  case Hexagon::PS_jmpretf:
832
0
    Result.setOpcode(Hexagon::SL2_jumpr31_f);
833
0
    break; //    none  SUBInst if (!p0) jumpr r31
834
9
  case Hexagon::J2_jumprfnew:
835
9
  case Hexagon::J2_jumprfnewpt:
836
9
  case Hexagon::PS_jmpretfnewpt:
837
9
  case Hexagon::PS_jmpretfnew:
838
9
    Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
839
9
    break; //    none  SUBInst if (!p0.new) jumpr:nt r31
840
9
  case Hexagon::J2_jumprt:
841
2
  case Hexagon::PS_jmprett:
842
2
    Result.setOpcode(Hexagon::SL2_jumpr31_t);
843
2
    break; //    none  SUBInst if (p0) jumpr r31
844
10
  case Hexagon::J2_jumprtnew:
845
10
  case Hexagon::J2_jumprtnewpt:
846
10
  case Hexagon::PS_jmprettnewpt:
847
10
  case Hexagon::PS_jmprettnew:
848
10
    Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
849
10
    break; //    none  SUBInst if (p0.new) jumpr:nt r31
850
10
  case Hexagon::L2_loadrb_io:
851
1
    Result.setOpcode(Hexagon::SL2_loadrb_io);
852
1
    addOps(Result, Inst, 0);
853
1
    addOps(Result, Inst, 1);
854
1
    addOps(Result, Inst, 2);
855
1
    break; //    1,2,3 SUBInst $Rd = memb($Rs + #$u3_0)
856
588
  case Hexagon::L2_loadrd_io:
857
588
    Result.setOpcode(Hexagon::SL2_loadrd_sp);
858
588
    addOps(Result, Inst, 0);
859
588
    addOps(Result, Inst, 2);
860
588
    break; //    1,3 SUBInst $Rdd = memd(r29 + #$u5_3)
861
10
  case Hexagon::L2_loadrh_io:
862
7
    Result.setOpcode(Hexagon::SL2_loadrh_io);
863
7
    addOps(Result, Inst, 0);
864
7
    addOps(Result, Inst, 1);
865
7
    addOps(Result, Inst, 2);
866
7
    break; //    1,2,3 SUBInst $Rd = memh($Rs + #$u3_1)
867
105
  case Hexagon::L2_loadrub_io:
868
105
    Result.setOpcode(Hexagon::SL1_loadrub_io);
869
105
    addOps(Result, Inst, 0);
870
105
    addOps(Result, Inst, 1);
871
105
    addOps(Result, Inst, 2);
872
105
    break; //    1,2,3 SUBInst $Rd = memub($Rs + #$u4_0)
873
59
  case Hexagon::L2_loadruh_io:
874
59
    Result.setOpcode(Hexagon::SL2_loadruh_io);
875
59
    addOps(Result, Inst, 0);
876
59
    addOps(Result, Inst, 1);
877
59
    addOps(Result, Inst, 2);
878
59
    break; //    1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1)
879
322
  case Hexagon::L2_loadri_io:
880
322
    if (Inst.getOperand(1).getReg() == Hexagon::R29) {
881
100
      Result.setOpcode(Hexagon::SL2_loadri_sp);
882
100
      addOps(Result, Inst, 0);
883
100
      addOps(Result, Inst, 2);
884
100
      break; //  2 1,3 SUBInst $Rd = memw(r29 + #$u5_2)
885
222
    } else {
886
222
      Result.setOpcode(Hexagon::SL1_loadri_io);
887
222
      addOps(Result, Inst, 0);
888
222
      addOps(Result, Inst, 1);
889
222
      addOps(Result, Inst, 2);
890
222
      break; //    1,2,3 SUBInst $Rd = memw($Rs + #$u4_2)
891
222
    }
892
11
  case Hexagon::S4_storeirb_io:
893
11
    Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
894
11
    assert(Absolute);(void)Absolute;
895
11
    if (Value == 0) {
896
8
      Result.setOpcode(Hexagon::SS2_storebi0);
897
8
      addOps(Result, Inst, 0);
898
8
      addOps(Result, Inst, 1);
899
8
      break; //    1,2 SUBInst memb($Rs + #$u4_0)=#0
900
8
    } else 
if (3
Value == 13
) {
901
3
      Result.setOpcode(Hexagon::SS2_storebi1);
902
3
      addOps(Result, Inst, 0);
903
3
      addOps(Result, Inst, 1);
904
3
      break; //  2 1,2 SUBInst memb($Rs + #$u4_0)=#1
905
3
    }
906
0
    break;
907
14
  case Hexagon::S2_storerb_io:
908
14
    Result.setOpcode(Hexagon::SS1_storeb_io);
909
14
    addOps(Result, Inst, 0);
910
14
    addOps(Result, Inst, 1);
911
14
    addOps(Result, Inst, 2);
912
14
    break; //    1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
913
241
  case Hexagon::S2_storerd_io:
914
241
    Result.setOpcode(Hexagon::SS2_stored_sp);
915
241
    addOps(Result, Inst, 1);
916
241
    addOps(Result, Inst, 2);
917
241
    break; //    2,3 SUBInst memd(r29 + #$s6_3) = $Rtt
918
12
  case Hexagon::S2_storerh_io:
919
12
    Result.setOpcode(Hexagon::SS2_storeh_io);
920
12
    addOps(Result, Inst, 0);
921
12
    addOps(Result, Inst, 1);
922
12
    addOps(Result, Inst, 2);
923
12
    break; //    1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
924
31
  case Hexagon::S4_storeiri_io:
925
31
    Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
926
31
    assert(Absolute);(void)Absolute;
927
31
    if (Value == 0) {
928
28
      Result.setOpcode(Hexagon::SS2_storewi0);
929
28
      addOps(Result, Inst, 0);
930
28
      addOps(Result, Inst, 1);
931
28
      break; //  3 1,2 SUBInst memw($Rs + #$u4_2)=#0
932
28
    } else 
if (3
Value == 13
) {
933
3
      Result.setOpcode(Hexagon::SS2_storewi1);
934
3
      addOps(Result, Inst, 0);
935
3
      addOps(Result, Inst, 1);
936
3
      break; //  3 1,2 SUBInst memw($Rs + #$u4_2)=#1
937
3
    } else 
if (0
Inst.getOperand(0).getReg() == Hexagon::R290
) {
938
0
      Result.setOpcode(Hexagon::SS2_storew_sp);
939
0
      addOps(Result, Inst, 1);
940
0
      addOps(Result, Inst, 2);
941
0
      break; //  1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt
942
0
    }
943
0
    break;
944
113
  case Hexagon::S2_storeri_io:
945
113
    if (Inst.getOperand(0).getReg() == Hexagon::R29) {
946
77
      Result.setOpcode(Hexagon::SS2_storew_sp);
947
77
      addOps(Result, Inst, 1);
948
77
      addOps(Result, Inst, 2); //  1,2,3 SUBInst memw(sp + #$u5_2) = $Rt
949
77
    } else {
950
36
      Result.setOpcode(Hexagon::SS1_storew_io);
951
36
      addOps(Result, Inst, 0);
952
36
      addOps(Result, Inst, 1);
953
36
      addOps(Result, Inst, 2); //  1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt
954
36
    }
955
113
    break;
956
5
  case Hexagon::A2_sxtb:
957
5
    Result.setOpcode(Hexagon::SA1_sxtb);
958
5
    addOps(Result, Inst, 0);
959
5
    addOps(Result, Inst, 1);
960
5
    break; //  1,2 SUBInst $Rd = sxtb($Rs)
961
27
  case Hexagon::A2_sxth:
962
27
    Result.setOpcode(Hexagon::SA1_sxth);
963
27
    addOps(Result, Inst, 0);
964
27
    addOps(Result, Inst, 1);
965
27
    break; //  1,2 SUBInst $Rd = sxth($Rs)
966
415
  case Hexagon::A2_tfr:
967
415
    Result.setOpcode(Hexagon::SA1_tfr);
968
415
    addOps(Result, Inst, 0);
969
415
    addOps(Result, Inst, 1);
970
415
    break; //  1,2 SUBInst $Rd = $Rs
971
15
  case Hexagon::C2_cmovenewif:
972
15
    Result.setOpcode(Hexagon::SA1_clrfnew);
973
15
    addOps(Result, Inst, 0);
974
15
    addOps(Result, Inst, 1);
975
15
    break; //  2 SUBInst if (!p0.new) $Rd = #0
976
22
  case Hexagon::C2_cmovenewit:
977
22
    Result.setOpcode(Hexagon::SA1_clrtnew);
978
22
    addOps(Result, Inst, 0);
979
22
    addOps(Result, Inst, 1);
980
22
    break; //  2 SUBInst if (p0.new) $Rd = #0
981
5
  case Hexagon::C2_cmoveif:
982
5
    Result.setOpcode(Hexagon::SA1_clrf);
983
5
    addOps(Result, Inst, 0);
984
5
    addOps(Result, Inst, 1);
985
5
    break; //  2 SUBInst if (!p0) $Rd = #0
986
4
  case Hexagon::C2_cmoveit:
987
4
    Result.setOpcode(Hexagon::SA1_clrt);
988
4
    addOps(Result, Inst, 0);
989
4
    addOps(Result, Inst, 1);
990
4
    break; //  2 SUBInst if (p0) $Rd = #0
991
1.16k
  case Hexagon::A2_tfrsi:
992
1.16k
    Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
993
1.16k
    if (Absolute && 
Value == -11.01k
) {
994
11
      Result.setOpcode(Hexagon::SA1_setin1);
995
11
      addOps(Result, Inst, 0);
996
11
      addOps(Result, Inst, 1);
997
11
      break; //  2 1 SUBInst $Rd = #-1
998
1.15k
    } else {
999
1.15k
      Result.setOpcode(Hexagon::SA1_seti);
1000
1.15k
      addOps(Result, Inst, 0);
1001
1.15k
      addOps(Result, Inst, 1);
1002
1.15k
      break; //    1,2 SUBInst $Rd = #$u6
1003
1.15k
    }
1004
0
  case Hexagon::A2_zxtb:
1005
0
    Result.setOpcode(Hexagon::SA1_zxtb);
1006
0
    addOps(Result, Inst, 0);
1007
0
    addOps(Result, Inst, 1);
1008
0
    break; //    1,2    $Rd = and($Rs, #255)
1009
0
1010
7
  case Hexagon::A2_zxth:
1011
7
    Result.setOpcode(Hexagon::SA1_zxth);
1012
7
    addOps(Result, Inst, 0);
1013
7
    addOps(Result, Inst, 1);
1014
7
    break; //    1,2 SUBInst $Rd = zxth($Rs)
1015
4.63k
  }
1016
4.63k
  return Result;
1017
4.63k
}
1018
1019
21.6k
static bool isStoreInst(unsigned opCode) {
1020
21.6k
  switch (opCode) {
1021
21.6k
  case Hexagon::S2_storeri_io:
1022
714
  case Hexagon::S2_storerb_io:
1023
714
  case Hexagon::S2_storerh_io:
1024
714
  case Hexagon::S2_storerd_io:
1025
714
  case Hexagon::S4_storeiri_io:
1026
714
  case Hexagon::S4_storeirb_io:
1027
714
  case Hexagon::S2_allocframe:
1028
714
    return true;
1029
20.9k
  default:
1030
20.9k
    return false;
1031
21.6k
  }
1032
21.6k
}
1033
1034
SmallVector<DuplexCandidate, 8>
1035
HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII,
1036
                                          MCSubtargetInfo const &STI,
1037
23.3k
                                          MCInst const &MCB) {
1038
23.3k
  assert(isBundle(MCB));
1039
23.3k
  SmallVector<DuplexCandidate, 8> duplexToTry;
1040
23.3k
  // Use an "order matters" version of isDuplexPair.
1041
23.3k
  unsigned numInstrInPacket = MCB.getNumOperands();
1042
23.3k
1043
61.4k
  for (unsigned distance = 1; distance < numInstrInPacket; 
++distance38.1k
) {
1044
38.1k
    for (unsigned j = HexagonMCInstrInfo::bundleInstructionsOffset,
1045
38.1k
                  k = j + distance;
1046
59.4k
         (j < numInstrInPacket) && (k < numInstrInPacket); 
++j, ++k21.2k
) {
1047
21.2k
1048
21.2k
      // Check if reversible.
1049
21.2k
      bool bisReversable = true;
1050
21.2k
      if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) &&
1051
21.2k
          
isStoreInst(MCB.getOperand(k).getInst()->getOpcode())390
) {
1052
324
        LLVM_DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j
1053
324
                          << "\n");
1054
324
        bisReversable = false;
1055
324
      }
1056
21.2k
      if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf
1057
1
        bisReversable = false;
1058
21.2k
1059
21.2k
      // Try in order.
1060
21.2k
      if (isOrderedDuplexPair(
1061
21.2k
              MCII, *MCB.getOperand(k).getInst(),
1062
21.2k
              HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1),
1063
21.2k
              *MCB.getOperand(j).getInst(),
1064
21.2k
              HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1),
1065
21.2k
              bisReversable, STI)) {
1066
1.50k
        // Get iClass.
1067
1.50k
        unsigned iClass = iClassOfDuplexPair(
1068
1.50k
            getDuplexCandidateGroup(*MCB.getOperand(k).getInst()),
1069
1.50k
            getDuplexCandidateGroup(*MCB.getOperand(j).getInst()));
1070
1.50k
1071
1.50k
        // Save off pairs for duplex checking.
1072
1.50k
        duplexToTry.push_back(DuplexCandidate(j, k, iClass));
1073
1.50k
        LLVM_DEBUG(dbgs() << "adding pair: " << j << "," << k << ":"
1074
1.50k
                          << MCB.getOperand(j).getInst()->getOpcode() << ","
1075
1.50k
                          << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1076
1.50k
        continue;
1077
19.7k
      } else {
1078
19.7k
        LLVM_DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":"
1079
19.7k
                          << MCB.getOperand(j).getInst()->getOpcode() << ","
1080
19.7k
                          << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1081
19.7k
      }
1082
21.2k
1083
21.2k
      // Try reverse.
1084
21.2k
      
if (19.7k
bisReversable19.7k
) {
1085
19.6k
        if (isOrderedDuplexPair(
1086
19.6k
                MCII, *MCB.getOperand(j).getInst(),
1087
19.6k
                HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1),
1088
19.6k
                *MCB.getOperand(k).getInst(),
1089
19.6k
                HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1),
1090
19.6k
                bisReversable, STI)) {
1091
185
          // Get iClass.
1092
185
          unsigned iClass = iClassOfDuplexPair(
1093
185
              getDuplexCandidateGroup(*MCB.getOperand(j).getInst()),
1094
185
              getDuplexCandidateGroup(*MCB.getOperand(k).getInst()));
1095
185
1096
185
          // Save off pairs for duplex checking.
1097
185
          duplexToTry.push_back(DuplexCandidate(k, j, iClass));
1098
185
          LLVM_DEBUG(dbgs()
1099
185
                     << "adding pair:" << k << "," << j << ":"
1100
185
                     << MCB.getOperand(j).getInst()->getOpcode() << ","
1101
185
                     << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1102
19.4k
        } else {
1103
19.4k
          LLVM_DEBUG(dbgs()
1104
19.4k
                     << "skipping pair: " << k << "," << j << ":"
1105
19.4k
                     << MCB.getOperand(j).getInst()->getOpcode() << ","
1106
19.4k
                     << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1107
19.4k
        }
1108
19.6k
      }
1109
19.7k
    }
1110
38.1k
  }
1111
23.3k
  return duplexToTry;
1112
23.3k
}