Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
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//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MCTargetDesc/HexagonMCInstrInfo.h"
14
#include "MCTargetDesc/HexagonBaseInfo.h"
15
#include "MCTargetDesc/HexagonMCChecker.h"
16
#include "MCTargetDesc/HexagonMCExpr.h"
17
#include "MCTargetDesc/HexagonMCShuffler.h"
18
#include "MCTargetDesc/HexagonMCTargetDesc.h"
19
#include "llvm/ADT/SmallVector.h"
20
#include "llvm/MC/MCContext.h"
21
#include "llvm/MC/MCExpr.h"
22
#include "llvm/MC/MCInst.h"
23
#include "llvm/MC/MCInstrInfo.h"
24
#include "llvm/MC/MCInstrItineraries.h"
25
#include "llvm/MC/MCSubtargetInfo.h"
26
#include "llvm/Support/Casting.h"
27
#include "llvm/Support/ErrorHandling.h"
28
#include <cassert>
29
#include <cstdint>
30
#include <limits>
31
32
using namespace llvm;
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34
678
bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const {
35
678
  return Register != Hexagon::NoRegister;
36
678
}
37
38
Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
39
                                        MCInst const &Inst)
40
    : MCII(MCII), BundleCurrent(Inst.begin() +
41
                                HexagonMCInstrInfo::bundleInstructionsOffset),
42
39.0k
      BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
43
44
Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
45
                                        MCInst const &Inst, std::nullptr_t)
46
    : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
47
39.0k
      DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
48
49
53.7k
Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
50
53.7k
  if (DuplexCurrent != DuplexEnd) {
51
240
    ++DuplexCurrent;
52
240
    if (DuplexCurrent == DuplexEnd) {
53
120
      DuplexCurrent = BundleEnd;
54
120
      DuplexEnd = BundleEnd;
55
120
      ++BundleCurrent;
56
120
    }
57
240
    return *this;
58
240
  }
59
53.4k
  ++BundleCurrent;
60
53.4k
  if (BundleCurrent != BundleEnd) {
61
15.0k
    MCInst const &Inst = *BundleCurrent->getInst();
62
15.0k
    if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
63
120
      DuplexCurrent = Inst.begin();
64
120
      DuplexEnd = Inst.end();
65
120
    }
66
15.0k
  }
67
53.4k
  return *this;
68
53.4k
}
69
70
54.2k
MCInst const &Hexagon::PacketIterator::operator*() const {
71
54.2k
  if (DuplexCurrent != DuplexEnd)
72
240
    return *DuplexCurrent->getInst();
73
53.9k
  return *BundleCurrent->getInst();
74
53.9k
}
75
76
92.7k
bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
77
92.7k
  return BundleCurrent == Other.BundleCurrent && 
BundleEnd == Other.BundleEnd38.5k
&&
78
92.7k
         
DuplexCurrent == Other.DuplexCurrent38.5k
&&
DuplexEnd == Other.DuplexEnd38.5k
;
79
92.7k
}
80
81
void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
82
2.59k
                                     MCContext &Context) {
83
2.59k
  MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
84
2.59k
}
85
86
void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
87
                                          MCInstrInfo const &MCII, MCInst &MCB,
88
2.00k
                                          MCInst const &MCI) {
89
2.00k
  assert(HexagonMCInstrInfo::isBundle(MCB));
90
2.00k
  MCOperand const &exOp =
91
2.00k
      MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
92
2.00k
93
2.00k
  // Create the extender.
94
2.00k
  MCInst *XMCI =
95
2.00k
      new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
96
2.00k
  XMCI->setLoc(MCI.getLoc());
97
2.00k
98
2.00k
  MCB.addOperand(MCOperand::createInst(XMCI));
99
2.00k
}
100
101
iterator_range<Hexagon::PacketIterator>
102
HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII,
103
39.0k
                                       MCInst const &MCI) {
104
39.0k
  assert(isBundle(MCI));
105
39.0k
  return make_range(Hexagon::PacketIterator(MCII, MCI),
106
39.0k
                    Hexagon::PacketIterator(MCII, MCI, nullptr));
107
39.0k
}
108
109
iterator_range<MCInst::const_iterator>
110
156k
HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
111
156k
  assert(isBundle(MCI));
112
156k
  return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
113
156k
}
114
115
162k
size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
116
162k
  if (HexagonMCInstrInfo::isBundle(MCI))
117
162k
    return (MCI.size() - bundleInstructionsOffset);
118
0
  else
119
0
    return (1);
120
162k
}
121
122
bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
123
                                            MCSubtargetInfo const &STI,
124
                                            MCContext &Context, MCInst &MCB,
125
23.4k
                                            HexagonMCChecker *Check) {
126
23.4k
  // Check the bundle for errors.
127
23.4k
  bool CheckOk = Check ? 
Check->check(false)2.48k
:
true20.9k
;
128
23.4k
  if (!CheckOk)
129
23
    return false;
130
23.3k
  // Examine the packet and convert pairs of instructions to compound
131
23.3k
  // instructions when possible.
132
23.3k
  if (!HexagonDisableCompound)
133
23.3k
    HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
134
23.3k
  HexagonMCShuffle(Context, false, MCII, STI, MCB);
135
23.3k
  // Examine the packet and convert pairs of instructions to duplex
136
23.3k
  // instructions when possible.
137
23.3k
  MCInst InstBundlePreDuplex = MCInst(MCB);
138
23.3k
  if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
139
23.3k
    SmallVector<DuplexCandidate, 8> possibleDuplexes;
140
23.3k
    possibleDuplexes =
141
23.3k
        HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB);
142
23.3k
    HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
143
23.3k
  }
144
23.3k
  // Examines packet and pad the packet, if needed, when an
145
23.3k
  // end-loop is in the bundle.
146
23.3k
  HexagonMCInstrInfo::padEndloop(MCB, Context);
147
23.3k
  // If compounding and duplexing didn't reduce the size below
148
23.3k
  // 4 or less we have a packet that is too big.
149
23.3k
  if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE)
150
23.3k
    
return false0
;
151
23.3k
  // Check the bundle for errors.
152
23.3k
  CheckOk = Check ? 
Check->check(true)2.45k
:
true20.9k
;
153
23.3k
  if (!CheckOk)
154
1
    return false;
155
23.3k
  HexagonMCShuffle(Context, true, MCII, STI, MCB);
156
23.3k
  return true;
157
23.3k
}
158
159
MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
160
                                          MCInst const &Inst,
161
2.01k
                                          MCOperand const &MO) {
162
2.01k
  assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
163
2.01k
         HexagonMCInstrInfo::isExtended(MCII, Inst));
164
2.01k
165
2.01k
  MCInst XMI;
166
2.01k
  XMI.setOpcode(Hexagon::A4_ext);
167
2.01k
  if (MO.isImm())
168
0
    XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
169
2.01k
  else if (MO.isExpr())
170
2.01k
    XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
171
2.01k
  else
172
2.01k
    
llvm_unreachable0
("invalid extendable operand");
173
2.01k
  return XMI;
174
2.01k
}
175
176
MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
177
                                         MCInst const &inst0,
178
1.37k
                                         MCInst const &inst1) {
179
1.37k
  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
180
1.37k
  MCInst *duplexInst = new (Context) MCInst;
181
1.37k
  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
182
1.37k
183
1.37k
  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
184
1.37k
  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
185
1.37k
  duplexInst->addOperand(MCOperand::createInst(SubInst0));
186
1.37k
  duplexInst->addOperand(MCOperand::createInst(SubInst1));
187
1.37k
  return duplexInst;
188
1.37k
}
189
190
MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
191
87.0k
                                                   size_t Index) {
192
87.0k
  assert(Index <= bundleSize(MCB));
193
87.0k
  if (Index == 0)
194
32.8k
    return nullptr;
195
54.1k
  MCInst const *Inst =
196
54.1k
      MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
197
54.1k
  if (isImmext(*Inst))
198
8.40k
    return Inst;
199
45.7k
  return nullptr;
200
45.7k
}
201
202
void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
203
                                        MCInstrInfo const &MCII, MCInst &MCB,
204
36.5k
                                        MCInst const &MCI) {
205
36.5k
  if (isConstExtended(MCII, MCI))
206
2.00k
    addConstExtender(Context, MCII, MCB, MCI);
207
36.5k
}
208
209
unsigned HexagonMCInstrInfo::getMemAccessSize(MCInstrInfo const &MCII,
210
0
      MCInst const &MCI) {
211
0
  uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
212
0
  unsigned S = (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
213
0
  return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S));
214
0
}
215
216
unsigned HexagonMCInstrInfo::getAddrMode(MCInstrInfo const &MCII,
217
0
                                         MCInst const &MCI) {
218
0
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
219
0
  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
220
0
                               HexagonII::AddrModeMask);
221
0
}
222
223
MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
224
1.30M
                                               MCInst const &MCI) {
225
1.30M
  return MCII.get(MCI.getOpcode());
226
1.30M
}
227
228
156
unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
229
156
  using namespace Hexagon;
230
156
231
156
  switch (Reg) {
232
156
  default:
233
0
    llvm_unreachable("unknown duplex register");
234
156
  // Rs       Rss
235
156
  case R0:
236
27
  case D0:
237
27
    return 0;
238
27
  case R1:
239
13
  case D1:
240
13
    return 1;
241
13
  case R2:
242
6
  case D2:
243
6
    return 2;
244
6
  case R3:
245
0
  case D3:
246
0
    return 3;
247
2
  case R4:
248
2
  case D8:
249
2
    return 4;
250
2
  case R5:
251
0
  case D9:
252
0
    return 5;
253
1
  case R6:
254
1
  case D10:
255
1
    return 6;
256
3
  case R7:
257
3
  case D11:
258
3
    return 7;
259
3
  case R16:
260
2
    return 8;
261
75
  case R17:
262
75
    return 9;
263
3
  case R18:
264
1
    return 10;
265
3
  case R19:
266
1
    return 11;
267
3
  case R20:
268
0
    return 12;
269
25
  case R21:
270
25
    return 13;
271
3
  case R22:
272
0
    return 14;
273
3
  case R23:
274
0
    return 15;
275
156
  }
276
156
}
277
278
2.86k
MCExpr const &HexagonMCInstrInfo::getExpr(MCExpr const &Expr) {
279
2.86k
  const auto &HExpr = cast<HexagonMCExpr>(Expr);
280
2.86k
  assert(HExpr.getExpr());
281
2.86k
  return *HExpr.getExpr();
282
2.86k
}
283
284
unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
285
119k
                                                   MCInst const &MCI) {
286
119k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
287
119k
  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
288
119k
}
289
290
MCOperand const &
291
HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
292
20.7k
                                         MCInst const &MCI) {
293
20.7k
  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
294
20.7k
  MCOperand const &MO = MCI.getOperand(O);
295
20.7k
296
20.7k
  assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
297
20.7k
          HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
298
20.7k
         (MO.isImm() || MO.isExpr()));
299
20.7k
  return (MO);
300
20.7k
}
301
302
unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
303
742
                                                MCInst const &MCI) {
304
742
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
305
742
  return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
306
742
}
307
308
unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
309
30.4k
                                           MCInst const &MCI) {
310
30.4k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
311
30.4k
  return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
312
30.4k
}
313
314
bool HexagonMCInstrInfo::isExtentSigned(MCInstrInfo const &MCII,
315
31.5k
                                        MCInst const &MCI) {
316
31.5k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
317
31.5k
  return (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
318
31.5k
}
319
320
/// Return the maximum value of an extendable operand.
321
int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
322
15.7k
                                    MCInst const &MCI) {
323
15.7k
  assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
324
15.7k
         HexagonMCInstrInfo::isExtended(MCII, MCI));
325
15.7k
326
15.7k
  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
327
13.7k
    return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
328
1.98k
  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
329
1.98k
}
330
331
/// Return the minimum value of an extendable operand.
332
int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
333
15.7k
                                    MCInst const &MCI) {
334
15.7k
  assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
335
15.7k
         HexagonMCInstrInfo::isExtended(MCII, MCI));
336
15.7k
337
15.7k
  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
338
13.7k
    return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
339
1.98k
  return 0;
340
1.98k
}
341
342
StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
343
0
                                      MCInst const &MCI) {
344
0
  return MCII.getName(MCI.getOpcode());
345
0
}
346
347
unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
348
2.04k
                                                 MCInst const &MCI) {
349
2.04k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
350
2.04k
  return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
351
2.04k
}
352
353
MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
354
1.76k
                                                        MCInst const &MCI) {
355
1.76k
  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
356
1
    // VTMP doesn't actually exist in the encodings for these 184
357
1
    // 3 instructions so go ahead and create it here.
358
1
    static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
359
1
    return (MCO);
360
1.76k
  } else {
361
1.76k
    unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
362
1.76k
    MCOperand const &MCO = MCI.getOperand(O);
363
1.76k
364
1.76k
    assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
365
1.76k
            HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
366
1.76k
           MCO.isReg());
367
1.76k
    return (MCO);
368
1.76k
  }
369
1.76k
}
370
371
/// Return the new value or the newly produced value.
372
unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
373
0
                                                  MCInst const &MCI) {
374
0
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
375
0
  return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
376
0
}
377
378
MCOperand const &
379
HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
380
0
                                        MCInst const &MCI) {
381
0
  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
382
0
  MCOperand const &MCO = MCI.getOperand(O);
383
0
384
0
  assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
385
0
          HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
386
0
         MCO.isReg());
387
0
  return (MCO);
388
0
}
389
390
/// Return the Hexagon ISA class for the insn.
391
unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
392
465k
                                     MCInst const &MCI) {
393
465k
  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
394
465k
  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
395
465k
}
396
397
/// Return the slots this instruction can execute out of
398
unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
399
                                      MCSubtargetInfo const &STI,
400
152k
                                      MCInst const &MCI) {
401
152k
  const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
402
152k
  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
403
152k
  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
404
152k
}
405
406
/// Return the slots this instruction consumes in addition to
407
/// the slot(s) it can execute out of
408
409
unsigned HexagonMCInstrInfo::getOtherReservedSlots(MCInstrInfo const &MCII,
410
                                                   MCSubtargetInfo const &STI,
411
94.5k
                                                   MCInst const &MCI) {
412
94.5k
  const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
413
94.5k
  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
414
94.5k
  unsigned Slots = 0;
415
94.5k
416
94.5k
  // FirstStage are slots that this instruction can execute in.
417
94.5k
  // FirstStage+1 are slots that are also consumed by this instruction.
418
94.5k
  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
419
94.5k
  for (unsigned Stage = II[SchedClass].FirstStage + 1;
420
95.2k
       Stage < II[SchedClass].LastStage; 
++Stage678
) {
421
23.0k
    unsigned Units = (Stage + HexagonStages)->getUnits();
422
23.0k
    if (Units > HexagonGetLastSlot())
423
22.3k
      break;
424
678
    // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
425
678
    Slots |= Units;
426
678
  }
427
94.5k
428
94.5k
  // if 0 is returned, then no additional slots are consumed by this inst.
429
94.5k
  return Slots;
430
94.5k
}
431
432
0
bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
433
0
  if (!HexagonMCInstrInfo::isBundle(MCI))
434
0
    return false;
435
0
436
0
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
437
0
    if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
438
0
      return true;
439
0
  }
440
0
441
0
  return false;
442
0
}
443
444
81.8k
bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
445
81.8k
  return extenderForIndex(MCB, Index) != nullptr;
446
81.8k
}
447
448
0
bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
449
0
  if (!HexagonMCInstrInfo::isBundle(MCI))
450
0
    return false;
451
0
452
0
  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
453
0
    if (isImmext(*I.getInst()))
454
0
      return true;
455
0
  }
456
0
457
0
  return false;
458
0
}
459
460
/// Return whether the insn produces a value.
461
bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
462
479
                                     MCInst const &MCI) {
463
479
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
464
479
  return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
465
479
}
466
467
/// Return whether the insn produces a second value.
468
bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
469
8.78k
                                      MCInst const &MCI) {
470
8.78k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
471
8.78k
  return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
472
8.78k
}
473
474
279
MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
475
279
  assert(isBundle(MCB));
476
279
  assert(Index < HEXAGON_PACKET_SIZE);
477
279
  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
478
279
}
479
480
/// Return where the instruction is an accumulator.
481
bool HexagonMCInstrInfo::isAccumulator(MCInstrInfo const &MCII,
482
0
                                       MCInst const &MCI) {
483
0
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
484
0
  return ((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
485
0
}
486
487
362k
bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
488
362k
  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
489
362k
  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
490
362k
  return Result;
491
362k
}
492
493
bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
494
73.8k
                                         MCInst const &MCI) {
495
73.8k
  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
496
341
    return true;
497
73.5k
  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
498
52.7k
    return false;
499
20.7k
  MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
500
20.7k
  if (isa<HexagonMCExpr>(MO.getExpr()) &&
501
20.7k
      
HexagonMCInstrInfo::mustExtend(*MO.getExpr())19.7k
)
502
136
    return true;
503
20.5k
  // Branch insns are handled as necessary by relaxation.
504
20.5k
  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
505
20.5k
      
(17.6k
HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ17.6k
&&
506
17.6k
       
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()152
) ||
507
20.5k
      
(17.5k
HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ17.5k
&&
508
17.5k
       
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()273
))
509
3.31k
    return false;
510
17.2k
  // Otherwise loop instructions and other CR insts are handled by relaxation
511
17.2k
  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
512
17.2k
           
(MCI.getOpcode() != Hexagon::C4_addipc)511
)
513
472
    return false;
514
16.7k
515
16.7k
  assert(!MO.isImm());
516
16.7k
  if (isa<HexagonMCExpr>(MO.getExpr()) &&
517
16.7k
      
HexagonMCInstrInfo::mustNotExtend(*MO.getExpr())15.8k
)
518
4
    return false;
519
16.7k
  int64_t Value;
520
16.7k
  if (!MO.getExpr()->evaluateAsAbsolute(Value))
521
1.00k
    return true;
522
15.7k
  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
523
15.7k
  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
524
15.7k
  return (MinValue > Value || 
Value > MaxValue15.7k
);
525
15.7k
}
526
527
0
bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
528
0
  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
529
0
         !HexagonMCInstrInfo::isPrefix(MCII, MCI);
530
0
}
531
532
863
bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
533
863
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
534
863
  return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask);
535
863
}
536
537
bool HexagonMCInstrInfo::isCofRelax1(MCInstrInfo const &MCII,
538
863
                                     MCInst const &MCI) {
539
863
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
540
863
  return ((F >> HexagonII::CofRelax1Pos) & HexagonII::CofRelax1Mask);
541
863
}
542
543
bool HexagonMCInstrInfo::isCofRelax2(MCInstrInfo const &MCII,
544
863
                                     MCInst const &MCI) {
545
863
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
546
863
  return ((F >> HexagonII::CofRelax2Pos) & HexagonII::CofRelax2Mask);
547
863
}
548
549
bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
550
0
                                    MCInst const &MCI) {
551
0
  return (getType(MCII, MCI) == HexagonII::TypeCJ);
552
0
}
553
554
11.9k
bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
555
11.9k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
556
11.9k
  return ((F >> HexagonII::CVINewPos) & HexagonII::CVINewMask);
557
11.9k
}
558
559
3.44k
bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
560
3.44k
  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
561
3.44k
          
(1.85k
Reg >= Hexagon::D81.85k
&&
Reg <= Hexagon::D111.69k
));
562
3.44k
}
563
564
74.7k
bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
565
74.7k
  return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
566
74.7k
}
567
568
bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
569
75.4k
                                      MCInst const &MCI) {
570
75.4k
  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
571
75.4k
  return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
572
75.4k
}
573
574
bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
575
74.6k
                                    MCInst const &MCI) {
576
74.6k
  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
577
74.6k
  return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
578
74.6k
}
579
580
198
bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
581
198
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
582
198
  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
583
198
}
584
585
0
bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
586
0
  const uint64_t V = getType(MCII, MCI);
587
0
  return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
588
0
}
589
590
309k
bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
591
309k
  return MCI.getOpcode() == Hexagon::A4_ext;
592
309k
}
593
594
66.4k
bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
595
66.4k
  assert(isBundle(MCI));
596
66.4k
  int64_t Flags = MCI.getOperand(0).getImm();
597
66.4k
  return (Flags & innerLoopMask) != 0;
598
66.4k
}
599
600
8.84k
bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
601
8.84k
  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
602
8.84k
}
603
604
30.9k
bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
605
30.9k
  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
606
30.9k
          
(9.21k
Reg >= Hexagon::R169.21k
&&
Reg <= Hexagon::R236.16k
));
607
30.9k
}
608
609
/// Return whether the insn expects newly produced value.
610
bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
611
26.7k
                                    MCInst const &MCI) {
612
26.7k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
613
26.7k
  return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
614
26.7k
}
615
616
/// Return whether the operand is extendable.
617
bool HexagonMCInstrInfo::isOpExtendable(MCInstrInfo const &MCII,
618
0
                                        MCInst const &MCI, unsigned short O) {
619
0
  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
620
0
}
621
622
64.3k
bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
623
64.3k
  assert(isBundle(MCI));
624
64.3k
  int64_t Flags = MCI.getOperand(0).getImm();
625
64.3k
  return (Flags & outerLoopMask) != 0;
626
64.3k
}
627
628
bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
629
16.7k
                                      MCInst const &MCI) {
630
16.7k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
631
16.7k
  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
632
16.7k
}
633
634
0
bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
635
0
  return HexagonII::TypeEXTENDER == HexagonMCInstrInfo::getType(MCII, MCI);
636
0
}
637
638
bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
639
8.53k
                                         MCInst const &MCI) {
640
8.53k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
641
8.53k
  return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
642
8.53k
}
643
644
/// Return whether the insn is newly predicated.
645
bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
646
10.2k
                                         MCInst const &MCI) {
647
10.2k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
648
10.2k
  return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
649
10.2k
}
650
651
bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
652
2.07k
                                          MCInst const &MCI) {
653
2.07k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
654
2.07k
  return (
655
2.07k
      !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
656
2.07k
}
657
658
321
bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
659
321
  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
660
321
}
661
662
/// Return whether the insn can be packaged only with A and X-type insns.
663
11.9k
bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
664
11.9k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
665
11.9k
  return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
666
11.9k
}
667
668
/// Return whether the insn can be packaged only with an A-type insn in slot #1.
669
bool HexagonMCInstrInfo::isRestrictSlot1AOK(MCInstrInfo const &MCII,
670
94.5k
                                            MCInst const &MCI) {
671
94.5k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
672
94.5k
  return ((F >> HexagonII::RestrictSlot1AOKPos) &
673
94.5k
          HexagonII::RestrictSlot1AOKMask);
674
94.5k
}
675
676
bool HexagonMCInstrInfo::isRestrictNoSlot1Store(MCInstrInfo const &MCII,
677
94.5k
                                                MCInst const &MCI) {
678
94.5k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
679
94.5k
  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
680
94.5k
          HexagonII::RestrictNoSlot1StoreMask);
681
94.5k
}
682
683
/// Return whether the insn is solo, i.e., cannot be in a packet.
684
5.21k
bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
685
5.21k
  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
686
5.21k
  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
687
5.21k
}
688
689
43.3k
bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
690
43.3k
  assert(isBundle(MCI));
691
43.3k
  auto Flags = MCI.getOperand(0).getImm();
692
43.3k
  return (Flags & memReorderDisabledMask) != 0;
693
43.3k
}
694
695
9.14k
bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
696
9.14k
  switch (MCI.getOpcode()) {
697
9.14k
  default:
698
9.05k
    return false;
699
9.14k
  case Hexagon::SA1_addi:
700
84
  case Hexagon::SA1_addrx:
701
84
  case Hexagon::SA1_addsp:
702
84
  case Hexagon::SA1_and1:
703
84
  case Hexagon::SA1_clrf:
704
84
  case Hexagon::SA1_clrfnew:
705
84
  case Hexagon::SA1_clrt:
706
84
  case Hexagon::SA1_clrtnew:
707
84
  case Hexagon::SA1_cmpeqi:
708
84
  case Hexagon::SA1_combine0i:
709
84
  case Hexagon::SA1_combine1i:
710
84
  case Hexagon::SA1_combine2i:
711
84
  case Hexagon::SA1_combine3i:
712
84
  case Hexagon::SA1_combinerz:
713
84
  case Hexagon::SA1_combinezr:
714
84
  case Hexagon::SA1_dec:
715
84
  case Hexagon::SA1_inc:
716
84
  case Hexagon::SA1_seti:
717
84
  case Hexagon::SA1_setin1:
718
84
  case Hexagon::SA1_sxtb:
719
84
  case Hexagon::SA1_sxth:
720
84
  case Hexagon::SA1_tfr:
721
84
  case Hexagon::SA1_zxtb:
722
84
  case Hexagon::SA1_zxth:
723
84
  case Hexagon::SL1_loadri_io:
724
84
  case Hexagon::SL1_loadrub_io:
725
84
  case Hexagon::SL2_deallocframe:
726
84
  case Hexagon::SL2_jumpr31:
727
84
  case Hexagon::SL2_jumpr31_f:
728
84
  case Hexagon::SL2_jumpr31_fnew:
729
84
  case Hexagon::SL2_jumpr31_t:
730
84
  case Hexagon::SL2_jumpr31_tnew:
731
84
  case Hexagon::SL2_loadrb_io:
732
84
  case Hexagon::SL2_loadrd_sp:
733
84
  case Hexagon::SL2_loadrh_io:
734
84
  case Hexagon::SL2_loadri_sp:
735
84
  case Hexagon::SL2_loadruh_io:
736
84
  case Hexagon::SL2_return:
737
84
  case Hexagon::SL2_return_f:
738
84
  case Hexagon::SL2_return_fnew:
739
84
  case Hexagon::SL2_return_t:
740
84
  case Hexagon::SL2_return_tnew:
741
84
  case Hexagon::SS1_storeb_io:
742
84
  case Hexagon::SS1_storew_io:
743
84
  case Hexagon::SS2_allocframe:
744
84
  case Hexagon::SS2_storebi0:
745
84
  case Hexagon::SS2_storebi1:
746
84
  case Hexagon::SS2_stored_sp:
747
84
  case Hexagon::SS2_storeh_io:
748
84
  case Hexagon::SS2_storew_sp:
749
84
  case Hexagon::SS2_storewi0:
750
84
  case Hexagon::SS2_storewi1:
751
84
    return true;
752
9.14k
  }
753
9.14k
}
754
755
982
bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
756
982
  if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
757
982
      
(getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST)522
)
758
90
    return true;
759
892
  return false;
760
892
}
761
762
13.3k
int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
763
13.3k
  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
764
13.3k
                  << 8;
765
13.3k
  if (MCI.size() <= Index)
766
0
    return Sentinal;
767
13.3k
  MCOperand const &MCO = MCI.getOperand(Index);
768
13.3k
  if (!MCO.isExpr())
769
0
    return Sentinal;
770
13.3k
  int64_t Value;
771
13.3k
  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
772
26
    return Sentinal;
773
13.3k
  return Value;
774
13.3k
}
775
776
20.4k
void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
777
20.4k
  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
778
20.4k
  HExpr.setMustExtend(Val);
779
20.4k
}
780
781
20.8k
bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) {
782
20.8k
  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
783
20.8k
  return HExpr.mustExtend();
784
20.8k
}
785
1.22k
void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
786
1.22k
  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
787
1.22k
  HExpr.setMustNotExtend(Val);
788
1.22k
}
789
15.9k
bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
790
15.9k
  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
791
15.9k
  return HExpr.mustNotExtend();
792
15.9k
}
793
1
void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
794
1
  HexagonMCExpr &HExpr =
795
1
      const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
796
1
  HExpr.setS27_2_reloc(Val);
797
1
}
798
31
bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) {
799
31
  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
800
31
  if (!HExpr)
801
0
    return false;
802
31
  return HExpr->s27_2_reloc();
803
31
}
804
805
23.3k
void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) {
806
23.3k
  MCInst Nop;
807
23.3k
  Nop.setOpcode(Hexagon::A2_nop);
808
23.3k
  assert(isBundle(MCB));
809
23.5k
  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
810
23.5k
          
(HexagonMCInstrInfo::bundleSize(MCB) < 321
HEXAGON_PACKET_INNER_SIZE321
)) ||
811
23.5k
         
((23.4k
HexagonMCInstrInfo::isOuterLoop(MCB)23.4k
&&
812
23.4k
           
(HexagonMCInstrInfo::bundleSize(MCB) < 61
HEXAGON_PACKET_OUTER_SIZE61
))))
813
125
    MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
814
23.3k
}
815
816
HexagonMCInstrInfo::PredicateInfo
817
1.81k
HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) {
818
1.81k
  if (!isPredicated(MCII, MCI))
819
1.05k
    return {0, 0, false};
820
757
  MCInstrDesc const &Desc = getDesc(MCII, MCI);
821
1.33k
  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; 
++I581
)
822
1.13k
    if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
823
558
      return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
824
757
  
return {0, 0, false}199
;
825
757
}
826
827
bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
828
94.6k
                                      MCInst const &MCI) {
829
94.6k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
830
94.6k
  return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;
831
94.6k
}
832
833
/// return true if instruction has hasTmpDst attribute.
834
1.77k
bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
835
1.77k
  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
836
1.77k
  return (F >> HexagonII::HasTmpDstPos) & HexagonII::HasTmpDstMask;
837
1.77k
}
838
839
void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
840
1.37k
                                       DuplexCandidate Candidate) {
841
1.37k
  assert(Candidate.packetIndexI < MCB.size());
842
1.37k
  assert(Candidate.packetIndexJ < MCB.size());
843
1.37k
  assert(isBundle(MCB));
844
1.37k
  MCInst *Duplex =
845
1.37k
      deriveDuplex(Context, Candidate.iClass,
846
1.37k
                   *MCB.getOperand(Candidate.packetIndexJ).getInst(),
847
1.37k
                   *MCB.getOperand(Candidate.packetIndexI).getInst());
848
1.37k
  assert(Duplex != nullptr);
849
1.37k
  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
850
1.37k
  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
851
1.37k
}
852
853
237
void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
854
237
  assert(isBundle(MCI));
855
237
  MCOperand &Operand = MCI.getOperand(0);
856
237
  Operand.setImm(Operand.getImm() | innerLoopMask);
857
237
}
858
859
1
void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
860
1
  assert(isBundle(MCI));
861
1
  MCOperand &Operand = MCI.getOperand(0);
862
1
  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
863
1
  assert(isMemReorderDisabled(MCI));
864
1
}
865
866
38
void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
867
38
  assert(isBundle(MCI));
868
38
  MCOperand &Operand = MCI.getOperand(0);
869
38
  Operand.setImm(Operand.getImm() | outerLoopMask);
870
38
}
871
872
unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
873
                                            unsigned Producer,
874
186
                                            unsigned Producer2) {
875
186
  // If we're a single vector consumer of a double producer, set subreg bit
876
186
  // based on if we're accessing the lower or upper register component
877
186
  if (Producer >= Hexagon::W0 && 
Producer <= Hexagon::W151
)
878
1
    if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
879
1
      return (Consumer - Hexagon::V0) & 0x1;
880
185
  if (Producer2 != Hexagon::NoRegister)
881
0
    return Consumer == Producer;
882
185
  return 0;
883
185
}