Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
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//===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file provides Hexagon specific target descriptions.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MCTargetDesc/HexagonMCTargetDesc.h"
14
#include "HexagonDepArch.h"
15
#include "HexagonTargetStreamer.h"
16
#include "MCTargetDesc/HexagonInstPrinter.h"
17
#include "MCTargetDesc/HexagonMCAsmInfo.h"
18
#include "MCTargetDesc/HexagonMCELFStreamer.h"
19
#include "MCTargetDesc/HexagonMCInstrInfo.h"
20
#include "TargetInfo/HexagonTargetInfo.h"
21
#include "llvm/ADT/StringExtras.h"
22
#include "llvm/ADT/StringRef.h"
23
#include "llvm/BinaryFormat/ELF.h"
24
#include "llvm/MC/MCAsmBackend.h"
25
#include "llvm/MC/MCCodeEmitter.h"
26
#include "llvm/MC/MCContext.h"
27
#include "llvm/MC/MCDwarf.h"
28
#include "llvm/MC/MCELFStreamer.h"
29
#include "llvm/MC/MCInstrAnalysis.h"
30
#include "llvm/MC/MCInstrInfo.h"
31
#include "llvm/MC/MCObjectWriter.h"
32
#include "llvm/MC/MCRegisterInfo.h"
33
#include "llvm/MC/MCStreamer.h"
34
#include "llvm/MC/MCSubtargetInfo.h"
35
#include "llvm/Support/ErrorHandling.h"
36
#include "llvm/Support/TargetRegistry.h"
37
#include "llvm/Support/raw_ostream.h"
38
#include <cassert>
39
#include <cstdint>
40
#include <new>
41
#include <string>
42
43
using namespace llvm;
44
45
#define GET_INSTRINFO_MC_DESC
46
#include "HexagonGenInstrInfo.inc"
47
48
#define GET_SUBTARGETINFO_MC_DESC
49
#include "HexagonGenSubtargetInfo.inc"
50
51
#define GET_REGINFO_MC_DESC
52
#include "HexagonGenRegisterInfo.inc"
53
54
cl::opt<bool> llvm::HexagonDisableCompound
55
  ("mno-compound",
56
   cl::desc("Disable looking for compound instructions for Hexagon"));
57
58
cl::opt<bool> llvm::HexagonDisableDuplex
59
  ("mno-pairing",
60
   cl::desc("Disable looking for duplex instructions for Hexagon"));
61
62
namespace { // These flags are to be deprecated
63
cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
64
                  cl::init(false));
65
cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
66
                   cl::init(false));
67
cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
68
                   cl::init(false));
69
cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
70
                   cl::init(false));
71
cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
72
                   cl::init(false));
73
cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
74
                   cl::init(false));
75
} // namespace
76
77
cl::opt<Hexagon::ArchEnum>
78
    EnableHVX("mhvx",
79
      cl::desc("Enable Hexagon Vector eXtensions"),
80
      cl::values(
81
        clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
82
        clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
83
        clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
84
        clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
85
        // Sentinel for no value specified.
86
        clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
87
      // Sentinel for flag not present.
88
      cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional);
89
90
static cl::opt<bool>
91
  DisableHVX("mno-hvx", cl::Hidden,
92
             cl::desc("Disable Hexagon Vector eXtensions"));
93
94
95
static StringRef DefaultArch = "hexagonv60";
96
97
3.32k
static StringRef HexagonGetArchVariant() {
98
3.32k
  if (MV5)
99
2
    return "hexagonv5";
100
3.32k
  if (MV55)
101
0
    return "hexagonv55";
102
3.32k
  if (MV60)
103
5
    return "hexagonv60";
104
3.32k
  if (MV62)
105
4
    return "hexagonv62";
106
3.31k
  if (MV65)
107
40
    return "hexagonv65";
108
3.27k
  if (MV66)
109
0
    return "hexagonv66";
110
3.27k
  return "";
111
3.27k
}
112
113
3.32k
StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
114
3.32k
  StringRef ArchV = HexagonGetArchVariant();
115
3.32k
  if (!ArchV.empty() && 
!CPU.empty()51
) {
116
20
    if (ArchV != CPU)
117
0
      report_fatal_error("conflicting architectures specified.");
118
20
    return CPU;
119
20
  }
120
3.30k
  if (ArchV.empty()) {
121
3.27k
    if (CPU.empty())
122
1.62k
      CPU = DefaultArch;
123
3.27k
    return CPU;
124
3.27k
  }
125
31
  return ArchV;
126
31
}
127
128
23.0k
unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
129
130
namespace {
131
132
class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
133
public:
134
  HexagonTargetAsmStreamer(MCStreamer &S,
135
                           formatted_raw_ostream &OS,
136
                           bool isVerboseAsm,
137
                           MCInstPrinter &IP)
138
931
      : HexagonTargetStreamer(S) {}
139
140
  void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
141
22.1k
                      const MCInst &Inst, const MCSubtargetInfo &STI) override {
142
22.1k
    assert(HexagonMCInstrInfo::isBundle(Inst));
143
22.1k
    assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
144
22.1k
    std::string Buffer;
145
22.1k
    {
146
22.1k
      raw_string_ostream TempStream(Buffer);
147
22.1k
      InstPrinter.printInst(&Inst, TempStream, "", STI);
148
22.1k
    }
149
22.1k
    StringRef Contents(Buffer);
150
22.1k
    auto PacketBundle = Contents.rsplit('\n');
151
22.1k
    auto HeadTail = PacketBundle.first.split('\n');
152
22.1k
    StringRef Separator = "\n";
153
22.1k
    StringRef Indent = "\t";
154
22.1k
    OS << "\t{\n";
155
57.6k
    while (!HeadTail.first.empty()) {
156
35.4k
      StringRef InstTxt;
157
35.4k
      auto Duplex = HeadTail.first.split('\v');
158
35.4k
      if (!Duplex.second.empty()) {
159
1.04k
        OS << Indent << Duplex.first << Separator;
160
1.04k
        InstTxt = Duplex.second;
161
34.4k
      } else if (!HeadTail.first.trim().startswith("immext")) {
162
32.6k
        InstTxt = Duplex.first;
163
32.6k
      }
164
35.4k
      if (!InstTxt.empty())
165
33.6k
        OS << Indent << InstTxt << Separator;
166
35.4k
      HeadTail = HeadTail.second.split('\n');
167
35.4k
    }
168
22.1k
169
22.1k
    if (HexagonMCInstrInfo::isMemReorderDisabled(Inst))
170
1
      OS << "\n\t} :mem_noshuf" << PacketBundle.second;
171
22.1k
    else
172
22.1k
      OS << "\t}" << PacketBundle.second;
173
22.1k
  }
174
};
175
176
class HexagonTargetELFStreamer : public HexagonTargetStreamer {
177
public:
178
128
  MCELFStreamer &getStreamer() {
179
128
    return static_cast<MCELFStreamer &>(Streamer);
180
128
  }
181
  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
182
128
      : HexagonTargetStreamer(S) {
183
128
    MCAssembler &MCA = getStreamer().getAssembler();
184
128
    MCA.setELFHeaderEFlags(Hexagon_MC::GetELFFlags(STI));
185
128
  }
186
187
188
  void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
189
                              unsigned ByteAlignment,
190
0
                              unsigned AccessSize) override {
191
0
    HexagonMCELFStreamer &HexagonELFStreamer =
192
0
        static_cast<HexagonMCELFStreamer &>(getStreamer());
193
0
    HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
194
0
                                                 AccessSize);
195
0
  }
196
197
  void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
198
                                   unsigned ByteAlignment,
199
0
                                   unsigned AccessSize) override {
200
0
    HexagonMCELFStreamer &HexagonELFStreamer =
201
0
        static_cast<HexagonMCELFStreamer &>(getStreamer());
202
0
    HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
203
0
        Symbol, Size, ByteAlignment, AccessSize);
204
0
  }
205
};
206
207
} // end anonymous namespace
208
209
2.56k
llvm::MCInstrInfo *llvm::createHexagonMCInstrInfo() {
210
2.56k
  MCInstrInfo *X = new MCInstrInfo();
211
2.56k
  InitHexagonMCInstrInfo(X);
212
2.56k
  return X;
213
2.56k
}
214
215
1.28k
static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
216
1.28k
  MCRegisterInfo *X = new MCRegisterInfo();
217
1.28k
  InitHexagonMCRegisterInfo(X, Hexagon::R31);
218
1.28k
  return X;
219
1.28k
}
220
221
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
222
1.28k
                                         const Triple &TT) {
223
1.28k
  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
224
1.28k
225
1.28k
  // VirtualFP = (R30 + #0).
226
1.28k
  MCCFIInstruction Inst =
227
1.28k
      MCCFIInstruction::createDefCfa(nullptr,
228
1.28k
          MRI.getDwarfRegNum(Hexagon::R30, true), 0);
229
1.28k
  MAI->addInitialFrameState(Inst);
230
1.28k
231
1.28k
  return MAI;
232
1.28k
}
233
234
static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
235
                                                 unsigned SyntaxVariant,
236
                                                 const MCAsmInfo &MAI,
237
                                                 const MCInstrInfo &MII,
238
                                                 const MCRegisterInfo &MRI)
239
1.02k
{
240
1.02k
  if (SyntaxVariant == 0)
241
1.02k
    return new HexagonInstPrinter(MAI, MII, MRI);
242
0
  else
243
0
    return nullptr;
244
1.02k
}
245
246
static MCTargetStreamer *
247
createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
248
931
                          MCInstPrinter *IP, bool IsVerboseAsm) {
249
931
  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
250
931
}
251
252
static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
253
                                    std::unique_ptr<MCAsmBackend> &&MAB,
254
                                    std::unique_ptr<MCObjectWriter> &&OW,
255
                                    std::unique_ptr<MCCodeEmitter> &&Emitter,
256
128
                                    bool RelaxAll) {
257
128
  return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
258
128
                                  std::move(Emitter));
259
128
}
260
261
static MCTargetStreamer *
262
128
createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
263
128
  return new HexagonTargetELFStreamer(S, STI);
264
128
}
265
266
0
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo* STI, uint64_t F) {
267
0
  uint64_t FB = STI->getFeatureBits().to_ullong();
268
0
  if (FB & (1ULL << F))
269
0
    STI->ToggleFeature(F);
270
0
}
271
272
0
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) {
273
0
  uint64_t FB = STI->getFeatureBits().to_ullong();
274
0
  return (FB & (1ULL << F)) != 0;
275
0
}
276
277
namespace {
278
1.25k
std::string selectHexagonFS(StringRef CPU, StringRef FS) {
279
1.25k
  SmallVector<StringRef, 3> Result;
280
1.25k
  if (!FS.empty())
281
42
    Result.push_back(FS);
282
1.25k
283
1.25k
  switch (EnableHVX) {
284
1.25k
  case Hexagon::ArchEnum::V5:
285
0
  case Hexagon::ArchEnum::V55:
286
0
    break;
287
0
  case Hexagon::ArchEnum::V60:
288
0
    Result.push_back("+hvxv60");
289
0
    break;
290
0
  case Hexagon::ArchEnum::V62:
291
0
    Result.push_back("+hvxv62");
292
0
    break;
293
0
  case Hexagon::ArchEnum::V65:
294
0
    Result.push_back("+hvxv65");
295
0
    break;
296
0
  case Hexagon::ArchEnum::V66:
297
0
    Result.push_back("+hvxv66");
298
0
    break;
299
40
  case Hexagon::ArchEnum::Generic:{
300
40
    Result.push_back(StringSwitch<StringRef>(CPU)
301
40
             .Case("hexagonv60", "+hvxv60")
302
40
             .Case("hexagonv62", "+hvxv62")
303
40
             .Case("hexagonv65", "+hvxv65")
304
40
             .Case("hexagonv66", "+hvxv66"));
305
40
    break;
306
0
  }
307
1.21k
  case Hexagon::ArchEnum::NoArch:
308
1.21k
    // Sentinal if -mhvx isn't specified
309
1.21k
    break;
310
1.25k
  }
311
1.25k
  return join(Result.begin(), Result.end(), ",");
312
1.25k
}
313
}
314
315
static bool isCPUValid(std::string CPU)
316
1.25k
{
317
1.25k
  std::vector<std::string> table {
318
1.25k
    "generic",    "hexagonv5",  "hexagonv55", "hexagonv60",
319
1.25k
    "hexagonv62", "hexagonv65", "hexagonv66",
320
1.25k
  };
321
1.25k
322
1.25k
  return std::find(table.begin(), table.end(), CPU) != table.end();
323
1.25k
}
324
325
namespace {
326
std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
327
1.25k
                                                   StringRef FS) {
328
1.25k
  std::pair<std::string, std::string> Result;
329
1.25k
  Result.first = Hexagon_MC::selectHexagonCPU(CPU);
330
1.25k
  Result.second = selectHexagonFS(Result.first, FS);
331
1.25k
  return Result;
332
1.25k
}
333
}
334
335
2.26k
FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
336
2.26k
  using namespace Hexagon;
337
2.26k
  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
338
2.26k
  // turns on hvxvNN, corresponding to the existing ArchVNN.
339
2.26k
  FeatureBitset FB = S;
340
2.26k
  unsigned CpuArch = ArchV5;
341
9.32k
  for (unsigned F : {ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
342
9.32k
    if (!FB.test(F))
343
7.05k
      continue;
344
2.26k
    CpuArch = F;
345
2.26k
    break;
346
2.26k
  }
347
2.26k
  bool UseHvx = false;
348
6.23k
  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
349
6.23k
    if (!FB.test(F))
350
5.94k
      continue;
351
288
    UseHvx = true;
352
288
    break;
353
288
  }
354
2.26k
  bool HasHvxVer = false;
355
2.26k
  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
356
8.44k
                     ExtensionHVXV66}) {
357
8.44k
    if (!FB.test(F))
358
8.23k
      continue;
359
210
    HasHvxVer = true;
360
210
    UseHvx = true;
361
210
    break;
362
210
  }
363
2.26k
364
2.26k
  if (!UseHvx || 
HasHvxVer288
)
365
2.19k
    return FB;
366
78
367
78
  // HasHvxVer is false, and UseHvx is true.
368
78
  switch (CpuArch) {
369
78
    case ArchV66:
370
0
      FB.set(ExtensionHVXV66);
371
0
      LLVM_FALLTHROUGH;
372
1
    case ArchV65:
373
1
      FB.set(ExtensionHVXV65);
374
1
      LLVM_FALLTHROUGH;
375
2
    case ArchV62:
376
2
      FB.set(ExtensionHVXV62);
377
2
      LLVM_FALLTHROUGH;
378
78
    case ArchV60:
379
78
      FB.set(ExtensionHVXV60);
380
78
      break;
381
78
  }
382
78
  return FB;
383
78
}
384
385
MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
386
                                                          StringRef CPU,
387
1.25k
                                                          StringRef FS) {
388
1.25k
  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
389
1.25k
  StringRef CPUName = Features.first;
390
1.25k
  StringRef ArchFS = Features.second;
391
1.25k
392
1.25k
  if (!isCPUValid(CPUName.str())) {
393
0
    errs() << "error: invalid CPU \"" << CPUName.str().c_str()
394
0
           << "\" specified\n";
395
0
    return nullptr;
396
0
  }
397
1.25k
398
1.25k
  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
399
1.25k
  if (HexagonDisableDuplex) {
400
6
    llvm::FeatureBitset Features = X->getFeatureBits();
401
6
    X->setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
402
6
  }
403
1.25k
404
1.25k
  X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
405
1.25k
  return X;
406
1.25k
}
407
408
128
unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
409
128
  static std::map<StringRef,unsigned> ElfFlags = {
410
128
    {"hexagonv5",  ELF::EF_HEXAGON_MACH_V5},
411
128
    {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
412
128
    {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
413
128
    {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
414
128
    {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
415
128
    {"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
416
128
  };
417
128
418
128
  auto F = ElfFlags.find(STI.getCPU());
419
128
  assert(F != ElfFlags.end() && "Unrecognized Architecture");
420
128
  return F->second;
421
128
}
422
423
namespace {
424
class HexagonMCInstrAnalysis : public MCInstrAnalysis {
425
public:
426
94
  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
427
428
2.60k
  bool isUnconditionalBranch(MCInst const &Inst) const override {
429
2.60k
    //assert(!HexagonMCInstrInfo::isBundle(Inst));
430
2.60k
    return MCInstrAnalysis::isUnconditionalBranch(Inst);
431
2.60k
  }
432
433
2.60k
  bool isConditionalBranch(MCInst const &Inst) const override {
434
2.60k
    //assert(!HexagonMCInstrInfo::isBundle(Inst));
435
2.60k
    return MCInstrAnalysis::isConditionalBranch(Inst);
436
2.60k
  }
437
438
  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
439
0
                      uint64_t Size, uint64_t &Target) const override {
440
0
    //assert(!HexagonMCInstrInfo::isBundle(Inst));
441
0
    if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
442
0
      return false;
443
0
    auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
444
0
    assert(Extended.isExpr());
445
0
    int64_t Value;
446
0
    if(!Extended.getExpr()->evaluateAsAbsolute(Value))
447
0
      return false;
448
0
    Target = Value;
449
0
    return true;
450
0
  }
451
};
452
}
453
454
94
static MCInstrAnalysis *createHexagonMCInstrAnalysis(const MCInstrInfo *Info) {
455
94
  return new HexagonMCInstrAnalysis(Info);
456
94
}
457
458
// Force static initialization.
459
96.4k
extern "C" void LLVMInitializeHexagonTargetMC() {
460
96.4k
  // Register the MC asm info.
461
96.4k
  RegisterMCAsmInfoFn X(getTheHexagonTarget(), createHexagonMCAsmInfo);
462
96.4k
463
96.4k
  // Register the MC instruction info.
464
96.4k
  TargetRegistry::RegisterMCInstrInfo(getTheHexagonTarget(),
465
96.4k
                                      createHexagonMCInstrInfo);
466
96.4k
467
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  // Register the MC register info.
468
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  TargetRegistry::RegisterMCRegInfo(getTheHexagonTarget(),
469
96.4k
                                    createHexagonMCRegisterInfo);
470
96.4k
471
96.4k
  // Register the MC subtarget info.
472
96.4k
  TargetRegistry::RegisterMCSubtargetInfo(getTheHexagonTarget(),
473
96.4k
    Hexagon_MC::createHexagonMCSubtargetInfo);
474
96.4k
475
96.4k
  // Register the MC Code Emitter
476
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  TargetRegistry::RegisterMCCodeEmitter(getTheHexagonTarget(),
477
96.4k
                                        createHexagonMCCodeEmitter);
478
96.4k
479
96.4k
  // Register the asm backend
480
96.4k
  TargetRegistry::RegisterMCAsmBackend(getTheHexagonTarget(),
481
96.4k
                                       createHexagonAsmBackend);
482
96.4k
483
96.4k
484
96.4k
  // Register the MC instruction analyzer.
485
96.4k
  TargetRegistry::RegisterMCInstrAnalysis(getTheHexagonTarget(),
486
96.4k
                                          createHexagonMCInstrAnalysis);
487
96.4k
488
96.4k
  // Register the obj streamer
489
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  TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(),
490
96.4k
                                      createMCStreamer);
491
96.4k
492
96.4k
  // Register the obj target streamer
493
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  TargetRegistry::RegisterObjectTargetStreamer(getTheHexagonTarget(),
494
96.4k
                                      createHexagonObjectTargetStreamer);
495
96.4k
496
96.4k
  // Register the asm streamer
497
96.4k
  TargetRegistry::RegisterAsmTargetStreamer(getTheHexagonTarget(),
498
96.4k
                                            createMCAsmTargetStreamer);
499
96.4k
500
96.4k
  // Register the MC Inst Printer
501
96.4k
  TargetRegistry::RegisterMCInstPrinter(getTheHexagonTarget(),
502
96.4k
                                        createHexagonMCInstPrinter);
503
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}