Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
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//===- HexagonShuffler.h - Instruction bundle shuffling ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the shuffling of insns inside a bundle according to the
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// packet formation rules of the Hexagon ISA.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/SMLoc.h"
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#include <cstdint>
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#include <utility>
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCInstrInfo;
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class MCSubtargetInfo;
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// Insn resources.
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class HexagonResource {
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  // Mask of the slots or units that may execute the insn and
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  // the weight or priority that the insn requires to be assigned a slot.
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  unsigned Slots, Weight;
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public:
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  HexagonResource(unsigned s) { setUnits(s); }
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  void setUnits(unsigned s) {
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    Slots = s & ((1u << HEXAGON_PACKET_SIZE) - 1);
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    setWeight(s);
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  }
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  unsigned setWeight(unsigned s);
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  unsigned getUnits() const { return (Slots); }
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  unsigned getWeight() const { return (Weight); }
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  // Check if the resources are in ascending slot order.
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  static bool lessUnits(const HexagonResource &A, const HexagonResource &B) {
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    return (countPopulation(A.getUnits()) < countPopulation(B.getUnits()));
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  }
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  // Check if the resources are in ascending weight order.
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  static bool lessWeight(const HexagonResource &A, const HexagonResource &B) {
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    return (A.getWeight() < B.getWeight());
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  }
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};
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// HVX insn resources.
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class HexagonCVIResource : public HexagonResource {
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public:
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  using UnitsAndLanes = std::pair<unsigned, unsigned>;
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  using TypeUnitsAndLanes = DenseMap<unsigned, UnitsAndLanes>;
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private:
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  // Available HVX slots.
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  enum {
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    CVI_NONE = 0,
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    CVI_XLANE = 1 << 0,
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    CVI_SHIFT = 1 << 1,
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    CVI_MPY0 = 1 << 2,
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    CVI_MPY1 = 1 << 3,
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    CVI_ZW = 1 << 4
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  };
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  // Count of adjacent slots that the insn requires to be executed.
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  unsigned Lanes;
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  // Flag whether the insn is a load or a store.
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  bool Load, Store;
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  // Flag whether the HVX resources are valid.
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  bool Valid;
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  void setLanes(unsigned l) { Lanes = l; }
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  void setLoad(bool f = true) { Load = f; }
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  void setStore(bool f = true) { Store = f; }
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public:
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  HexagonCVIResource(TypeUnitsAndLanes *TUL, MCInstrInfo const &MCII,
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                     unsigned s, MCInst const *id);
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  static void SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU);
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  bool isValid() const { return Valid; }
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  unsigned getLanes() const { return Lanes; }
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  bool mayLoad() const { return Load; }
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  bool mayStore() const { return Store; }
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};
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// Handle to an insn used by the shuffling algorithm.
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class HexagonInstr {
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  friend class HexagonShuffler;
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  MCInst const *ID;
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  MCInst const *Extender;
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  HexagonResource Core;
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  HexagonCVIResource CVI;
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public:
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  HexagonInstr(HexagonCVIResource::TypeUnitsAndLanes *T,
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               MCInstrInfo const &MCII, MCInst const *id,
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               MCInst const *Extender, unsigned s)
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      : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id) {}
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  MCInst const &getDesc() const { return *ID; }
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  MCInst const *getExtender() const { return Extender; }
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  // Check if the handles are in ascending order for shuffling purposes.
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  bool operator<(const HexagonInstr &B) const {
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    return (HexagonResource::lessWeight(B.Core, Core));
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  }
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  // Check if the handles are in ascending order by core slots.
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  static bool lessCore(const HexagonInstr &A, const HexagonInstr &B) {
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    return (HexagonResource::lessUnits(A.Core, B.Core));
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  }
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  // Check if the handles are in ascending order by HVX slots.
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  static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B) {
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    return (HexagonResource::lessUnits(A.CVI, B.CVI));
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  }
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};
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// Bundle shuffler.
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class HexagonShuffler {
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  using HexagonPacket =
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      SmallVector<HexagonInstr, HEXAGON_PRESHUFFLE_PACKET_SIZE>;
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  // Insn handles in a bundle.
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  HexagonPacket Packet;
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  HexagonPacket PacketSave;
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  HexagonCVIResource::TypeUnitsAndLanes TUL;
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protected:
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  MCContext &Context;
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  int64_t BundleFlags;
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  MCInstrInfo const &MCII;
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  MCSubtargetInfo const &STI;
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  SMLoc Loc;
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  bool ReportErrors;
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  std::vector<std::pair<SMLoc, std::string>> AppliedRestrictions;
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  void applySlotRestrictions();
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  void restrictSlot1AOK();
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  void restrictNoSlot1Store();
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public:
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  using iterator = HexagonPacket::iterator;
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  HexagonShuffler(MCContext &Context, bool ReportErrors,
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                  MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
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  // Reset to initial state.
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  void reset();
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  // Check if the bundle may be validly shuffled.
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  bool check();
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  // Reorder the insn handles in the bundle.
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  bool shuffle();
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  unsigned size() const { return (Packet.size()); }
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  bool isMemReorderDisabled() const {
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    return (BundleFlags & HexagonMCInstrInfo::memReorderDisabledMask) != 0;
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  }
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  iterator begin() { return (Packet.begin()); }
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  iterator end() { return (Packet.end()); }
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  // Add insn handle to the bundle .
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  void append(MCInst const &ID, MCInst const *Extender, unsigned S);
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  // Return the error code for the last check or shuffling of the bundle.
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  void reportError(Twine const &Msg);
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};
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} // end namespace llvm
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#endif //  LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H