/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/RDFRegisters.h
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1 | | //===- RDFRegisters.h -------------------------------------------*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | |
9 | | #ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H |
10 | | #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H |
11 | | |
12 | | #include "llvm/ADT/BitVector.h" |
13 | | #include "llvm/ADT/STLExtras.h" |
14 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
15 | | #include "llvm/MC/LaneBitmask.h" |
16 | | #include <cassert> |
17 | | #include <cstdint> |
18 | | #include <map> |
19 | | #include <set> |
20 | | #include <vector> |
21 | | |
22 | | namespace llvm { |
23 | | |
24 | | class MachineFunction; |
25 | | class raw_ostream; |
26 | | |
27 | | namespace rdf { |
28 | | |
29 | | using RegisterId = uint32_t; |
30 | | |
31 | | // Template class for a map translating uint32_t into arbitrary types. |
32 | | // The map will act like an indexed set: upon insertion of a new object, |
33 | | // it will automatically assign a new index to it. Index of 0 is treated |
34 | | // as invalid and is never allocated. |
35 | | template <typename T, unsigned N = 32> |
36 | | struct IndexedSet { |
37 | 13.3k | IndexedSet() { Map.reserve(N); } llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::IndexedSet() Line | Count | Source | 37 | 6.69k | IndexedSet() { Map.reserve(N); } |
llvm::rdf::IndexedSet<unsigned int const*, 32u>::IndexedSet() Line | Count | Source | 37 | 6.69k | IndexedSet() { Map.reserve(N); } |
|
38 | | |
39 | 195k | T get(uint32_t Idx) const { |
40 | 195k | // Index Idx corresponds to Map[Idx-1]. |
41 | 195k | assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); |
42 | 195k | return Map[Idx-1]; |
43 | 195k | } llvm::rdf::IndexedSet<unsigned int const*, 32u>::get(unsigned int) const Line | Count | Source | 39 | 112k | T get(uint32_t Idx) const { | 40 | 112k | // Index Idx corresponds to Map[Idx-1]. | 41 | 112k | assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); | 42 | 112k | return Map[Idx-1]; | 43 | 112k | } |
llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::get(unsigned int) const Line | Count | Source | 39 | 83.0k | T get(uint32_t Idx) const { | 40 | 83.0k | // Index Idx corresponds to Map[Idx-1]. | 41 | 83.0k | assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); | 42 | 83.0k | return Map[Idx-1]; | 43 | 83.0k | } |
|
44 | | |
45 | 19.9k | uint32_t insert(T Val) { |
46 | 19.9k | // Linear search. |
47 | 19.9k | auto F = llvm::find(Map, Val); |
48 | 19.9k | if (F != Map.end()) |
49 | 7.52k | return F - Map.begin() + 1; |
50 | 12.4k | Map.push_back(Val); |
51 | 12.4k | return Map.size(); // Return actual_index + 1. |
52 | 12.4k | } llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::insert(llvm::LaneBitmask) Line | Count | Source | 45 | 11.7k | uint32_t insert(T Val) { | 46 | 11.7k | // Linear search. | 47 | 11.7k | auto F = llvm::find(Map, Val); | 48 | 11.7k | if (F != Map.end()) | 49 | 6.09k | return F - Map.begin() + 1; | 50 | 5.70k | Map.push_back(Val); | 51 | 5.70k | return Map.size(); // Return actual_index + 1. | 52 | 5.70k | } |
llvm::rdf::IndexedSet<unsigned int const*, 32u>::insert(unsigned int const*) Line | Count | Source | 45 | 8.12k | uint32_t insert(T Val) { | 46 | 8.12k | // Linear search. | 47 | 8.12k | auto F = llvm::find(Map, Val); | 48 | 8.12k | if (F != Map.end()) | 49 | 1.42k | return F - Map.begin() + 1; | 50 | 6.69k | Map.push_back(Val); | 51 | 6.69k | return Map.size(); // Return actual_index + 1. | 52 | 6.69k | } |
|
53 | | |
54 | 217k | uint32_t find(T Val) const { |
55 | 217k | auto F = llvm::find(Map, Val); |
56 | 217k | assert(F != Map.end()); |
57 | 217k | return F - Map.begin() + 1; |
58 | 217k | } llvm::rdf::IndexedSet<unsigned int const*, 32u>::find(unsigned int const*) const Line | Count | Source | 54 | 217k | uint32_t find(T Val) const { | 55 | 217k | auto F = llvm::find(Map, Val); | 56 | 217k | assert(F != Map.end()); | 57 | 217k | return F - Map.begin() + 1; | 58 | 217k | } |
Unexecuted instantiation: llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::find(llvm::LaneBitmask) const |
59 | | |
60 | 13.3k | uint32_t size() const { return Map.size(); } |
61 | | |
62 | | using const_iterator = typename std::vector<T>::const_iterator; |
63 | | |
64 | 85.6k | const_iterator begin() const { return Map.begin(); } |
65 | 85.6k | const_iterator end() const { return Map.end(); } |
66 | | |
67 | | private: |
68 | | std::vector<T> Map; |
69 | | }; |
70 | | |
71 | | struct RegisterRef { |
72 | | RegisterId Reg = 0; |
73 | | LaneBitmask Mask = LaneBitmask::getNone(); |
74 | | |
75 | 25.3k | RegisterRef() = default; |
76 | | explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll()) |
77 | 3.54M | : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {} |
78 | | |
79 | 76.1k | operator bool() const { |
80 | 76.1k | return Reg != 0 && Mask.any()51.2k ; |
81 | 76.1k | } |
82 | | |
83 | 1.22M | bool operator== (const RegisterRef &RR) const { |
84 | 1.22M | return Reg == RR.Reg && Mask == RR.Mask375k ; |
85 | 1.22M | } |
86 | | |
87 | 764k | bool operator!= (const RegisterRef &RR) const { |
88 | 764k | return !operator==(RR); |
89 | 764k | } |
90 | | |
91 | 1.00M | bool operator< (const RegisterRef &RR) const { |
92 | 1.00M | return Reg < RR.Reg || (548k Reg == RR.Reg548k && Mask < RR.Mask255k ); |
93 | 1.00M | } |
94 | | }; |
95 | | |
96 | | |
97 | | struct PhysicalRegisterInfo { |
98 | | PhysicalRegisterInfo(const TargetRegisterInfo &tri, |
99 | | const MachineFunction &mf); |
100 | | |
101 | 3.61M | static bool isRegMaskId(RegisterId R) { |
102 | 3.61M | return TargetRegisterInfo::isStackSlot(R); |
103 | 3.61M | } |
104 | | |
105 | 217k | RegisterId getRegMaskId(const uint32_t *RM) const { |
106 | 217k | return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM)); |
107 | 217k | } |
108 | | |
109 | 105k | const uint32_t *getRegMaskBits(RegisterId R) const { |
110 | 105k | return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R)); |
111 | 105k | } |
112 | | |
113 | | RegisterRef normalize(RegisterRef RR) const; |
114 | | |
115 | 366k | bool alias(RegisterRef RA, RegisterRef RB) const { |
116 | 366k | if (!isRegMaskId(RA.Reg)) |
117 | 350k | return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB)348k : aliasRM(RA, RB)1.83k ; |
118 | 16.4k | return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA)14.9k : aliasMM(RA, RB)1.46k ; |
119 | 16.4k | } |
120 | | |
121 | | std::set<RegisterId> getAliasSet(RegisterId Reg) const; |
122 | | |
123 | 50.3k | RegisterRef getRefForUnit(uint32_t U) const { |
124 | 50.3k | return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask); |
125 | 50.3k | } |
126 | | |
127 | 105k | const BitVector &getMaskUnits(RegisterId MaskId) const { |
128 | 105k | return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units; |
129 | 105k | } |
130 | | |
131 | | RegisterRef mapTo(RegisterRef RR, unsigned R) const; |
132 | 4.27M | const TargetRegisterInfo &getTRI() const { return TRI; } |
133 | | |
134 | | private: |
135 | | struct RegInfo { |
136 | | const TargetRegisterClass *RegClass = nullptr; |
137 | | }; |
138 | | struct UnitInfo { |
139 | | RegisterId Reg = 0; |
140 | | LaneBitmask Mask; |
141 | | }; |
142 | | struct MaskInfo { |
143 | | BitVector Units; |
144 | | }; |
145 | | |
146 | | const TargetRegisterInfo &TRI; |
147 | | IndexedSet<const uint32_t*> RegMasks; |
148 | | std::vector<RegInfo> RegInfos; |
149 | | std::vector<UnitInfo> UnitInfos; |
150 | | std::vector<MaskInfo> MaskInfos; |
151 | | |
152 | | bool aliasRR(RegisterRef RA, RegisterRef RB) const; |
153 | | bool aliasRM(RegisterRef RR, RegisterRef RM) const; |
154 | | bool aliasMM(RegisterRef RM, RegisterRef RN) const; |
155 | | }; |
156 | | |
157 | | struct RegisterAggr { |
158 | | RegisterAggr(const PhysicalRegisterInfo &pri) |
159 | 1.22M | : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {} |
160 | 177k | RegisterAggr(const RegisterAggr &RG) = default; |
161 | | |
162 | 16.2k | bool empty() const { return Units.none(); } |
163 | | bool hasAliasOf(RegisterRef RR) const; |
164 | | bool hasCoverOf(RegisterRef RR) const; |
165 | | |
166 | | static bool isCoverOf(RegisterRef RA, RegisterRef RB, |
167 | 859k | const PhysicalRegisterInfo &PRI) { |
168 | 859k | return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); |
169 | 859k | } |
170 | | |
171 | | RegisterAggr &insert(RegisterRef RR); |
172 | | RegisterAggr &insert(const RegisterAggr &RG); |
173 | | RegisterAggr &intersect(RegisterRef RR); |
174 | | RegisterAggr &intersect(const RegisterAggr &RG); |
175 | | RegisterAggr &clear(RegisterRef RR); |
176 | | RegisterAggr &clear(const RegisterAggr &RG); |
177 | | |
178 | | RegisterRef intersectWith(RegisterRef RR) const; |
179 | | RegisterRef clearIn(RegisterRef RR) const; |
180 | | RegisterRef makeRegRef() const; |
181 | | |
182 | | void print(raw_ostream &OS) const; |
183 | | |
184 | | struct rr_iterator { |
185 | | using MapType = std::map<RegisterId, LaneBitmask>; |
186 | | |
187 | | private: |
188 | | MapType Masks; |
189 | | MapType::iterator Pos; |
190 | | unsigned Index; |
191 | | const RegisterAggr *Owner; |
192 | | |
193 | | public: |
194 | | rr_iterator(const RegisterAggr &RG, bool End); |
195 | | |
196 | 25.1k | RegisterRef operator*() const { |
197 | 25.1k | return RegisterRef(Pos->first, Pos->second); |
198 | 25.1k | } |
199 | | |
200 | 25.1k | rr_iterator &operator++() { |
201 | 25.1k | ++Pos; |
202 | 25.1k | ++Index; |
203 | 25.1k | return *this; |
204 | 25.1k | } |
205 | | |
206 | 34.1k | bool operator==(const rr_iterator &I) const { |
207 | 34.1k | assert(Owner == I.Owner); |
208 | 34.1k | (void)Owner; |
209 | 34.1k | return Index == I.Index; |
210 | 34.1k | } |
211 | | |
212 | 34.1k | bool operator!=(const rr_iterator &I) const { |
213 | 34.1k | return !(*this == I); |
214 | 34.1k | } |
215 | | }; |
216 | | |
217 | 9.02k | rr_iterator rr_begin() const { |
218 | 9.02k | return rr_iterator(*this, false); |
219 | 9.02k | } |
220 | 9.02k | rr_iterator rr_end() const { |
221 | 9.02k | return rr_iterator(*this, true); |
222 | 9.02k | } |
223 | | |
224 | | private: |
225 | | BitVector Units; |
226 | | const PhysicalRegisterInfo &PRI; |
227 | | }; |
228 | | |
229 | | // Optionally print the lane mask, if it is not ~0. |
230 | | struct PrintLaneMaskOpt { |
231 | 0 | PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {} |
232 | | LaneBitmask Mask; |
233 | | }; |
234 | | raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P); |
235 | | |
236 | | } // end namespace rdf |
237 | | |
238 | | } // end namespace llvm |
239 | | |
240 | | #endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H |