Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/RDFRegisters.h
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//===- RDFRegisters.h -------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
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#define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <set>
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#include <vector>
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namespace llvm {
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class MachineFunction;
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class raw_ostream;
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namespace rdf {
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  using RegisterId = uint32_t;
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  // Template class for a map translating uint32_t into arbitrary types.
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  // The map will act like an indexed set: upon insertion of a new object,
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  // it will automatically assign a new index to it. Index of 0 is treated
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  // as invalid and is never allocated.
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  template <typename T, unsigned N = 32>
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  struct IndexedSet {
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    IndexedSet() { Map.reserve(N); }
llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::IndexedSet()
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6.69k
    IndexedSet() { Map.reserve(N); }
llvm::rdf::IndexedSet<unsigned int const*, 32u>::IndexedSet()
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6.69k
    IndexedSet() { Map.reserve(N); }
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    T get(uint32_t Idx) const {
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      // Index Idx corresponds to Map[Idx-1].
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      assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
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      return Map[Idx-1];
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    }
llvm::rdf::IndexedSet<unsigned int const*, 32u>::get(unsigned int) const
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112k
    T get(uint32_t Idx) const {
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      // Index Idx corresponds to Map[Idx-1].
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      assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
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      return Map[Idx-1];
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    }
llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::get(unsigned int) const
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83.0k
    T get(uint32_t Idx) const {
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      // Index Idx corresponds to Map[Idx-1].
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      assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
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      return Map[Idx-1];
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    }
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    uint32_t insert(T Val) {
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      // Linear search.
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      auto F = llvm::find(Map, Val);
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      if (F != Map.end())
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        return F - Map.begin() + 1;
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      Map.push_back(Val);
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      return Map.size();  // Return actual_index + 1.
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    }
llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::insert(llvm::LaneBitmask)
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11.7k
    uint32_t insert(T Val) {
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      // Linear search.
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      auto F = llvm::find(Map, Val);
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      if (F != Map.end())
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        return F - Map.begin() + 1;
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      Map.push_back(Val);
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      return Map.size();  // Return actual_index + 1.
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    }
llvm::rdf::IndexedSet<unsigned int const*, 32u>::insert(unsigned int const*)
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8.12k
    uint32_t insert(T Val) {
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      // Linear search.
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      auto F = llvm::find(Map, Val);
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      if (F != Map.end())
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        return F - Map.begin() + 1;
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      Map.push_back(Val);
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      return Map.size();  // Return actual_index + 1.
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    }
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    uint32_t find(T Val) const {
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      auto F = llvm::find(Map, Val);
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      assert(F != Map.end());
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      return F - Map.begin() + 1;
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    }
llvm::rdf::IndexedSet<unsigned int const*, 32u>::find(unsigned int const*) const
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217k
    uint32_t find(T Val) const {
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      auto F = llvm::find(Map, Val);
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      assert(F != Map.end());
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      return F - Map.begin() + 1;
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    }
Unexecuted instantiation: llvm::rdf::IndexedSet<llvm::LaneBitmask, 32u>::find(llvm::LaneBitmask) const
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    uint32_t size() const { return Map.size(); }
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    using const_iterator = typename std::vector<T>::const_iterator;
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    const_iterator begin() const { return Map.begin(); }
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    const_iterator end() const { return Map.end(); }
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  private:
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    std::vector<T> Map;
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  };
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  struct RegisterRef {
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    RegisterId Reg = 0;
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    LaneBitmask Mask = LaneBitmask::getNone();
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    RegisterRef() = default;
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    explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
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      : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
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    operator bool() const {
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      return Reg != 0 && 
Mask.any()51.2k
;
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    }
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    bool operator== (const RegisterRef &RR) const {
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      return Reg == RR.Reg && 
Mask == RR.Mask375k
;
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    }
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    bool operator!= (const RegisterRef &RR) const {
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      return !operator==(RR);
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    }
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    bool operator< (const RegisterRef &RR) const {
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      return Reg < RR.Reg || 
(548k
Reg == RR.Reg548k
&&
Mask < RR.Mask255k
);
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    }
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  };
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  struct PhysicalRegisterInfo {
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    PhysicalRegisterInfo(const TargetRegisterInfo &tri,
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                         const MachineFunction &mf);
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    static bool isRegMaskId(RegisterId R) {
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      return TargetRegisterInfo::isStackSlot(R);
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    }
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    RegisterId getRegMaskId(const uint32_t *RM) const {
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      return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
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    }
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    const uint32_t *getRegMaskBits(RegisterId R) const {
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      return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
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    }
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    RegisterRef normalize(RegisterRef RR) const;
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    bool alias(RegisterRef RA, RegisterRef RB) const {
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      if (!isRegMaskId(RA.Reg))
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        return !isRegMaskId(RB.Reg) ? 
aliasRR(RA, RB)348k
:
aliasRM(RA, RB)1.83k
;
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      return !isRegMaskId(RB.Reg) ? 
aliasRM(RB, RA)14.9k
:
aliasMM(RA, RB)1.46k
;
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    }
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    std::set<RegisterId> getAliasSet(RegisterId Reg) const;
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    RegisterRef getRefForUnit(uint32_t U) const {
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      return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
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    }
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    const BitVector &getMaskUnits(RegisterId MaskId) const {
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      return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
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    }
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    RegisterRef mapTo(RegisterRef RR, unsigned R) const;
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    const TargetRegisterInfo &getTRI() const { return TRI; }
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  private:
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    struct RegInfo {
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      const TargetRegisterClass *RegClass = nullptr;
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    };
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    struct UnitInfo {
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      RegisterId Reg = 0;
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      LaneBitmask Mask;
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    };
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    struct MaskInfo {
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      BitVector Units;
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    };
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    const TargetRegisterInfo &TRI;
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    IndexedSet<const uint32_t*> RegMasks;
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    std::vector<RegInfo> RegInfos;
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    std::vector<UnitInfo> UnitInfos;
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    std::vector<MaskInfo> MaskInfos;
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    bool aliasRR(RegisterRef RA, RegisterRef RB) const;
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    bool aliasRM(RegisterRef RR, RegisterRef RM) const;
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    bool aliasMM(RegisterRef RM, RegisterRef RN) const;
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  };
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  struct RegisterAggr {
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    RegisterAggr(const PhysicalRegisterInfo &pri)
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        : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
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    RegisterAggr(const RegisterAggr &RG) = default;
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    bool empty() const { return Units.none(); }
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    bool hasAliasOf(RegisterRef RR) const;
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    bool hasCoverOf(RegisterRef RR) const;
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    static bool isCoverOf(RegisterRef RA, RegisterRef RB,
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                          const PhysicalRegisterInfo &PRI) {
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      return RegisterAggr(PRI).insert(RA).hasCoverOf(RB);
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    }
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    RegisterAggr &insert(RegisterRef RR);
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    RegisterAggr &insert(const RegisterAggr &RG);
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    RegisterAggr &intersect(RegisterRef RR);
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    RegisterAggr &intersect(const RegisterAggr &RG);
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    RegisterAggr &clear(RegisterRef RR);
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    RegisterAggr &clear(const RegisterAggr &RG);
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    RegisterRef intersectWith(RegisterRef RR) const;
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    RegisterRef clearIn(RegisterRef RR) const;
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    RegisterRef makeRegRef() const;
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    void print(raw_ostream &OS) const;
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    struct rr_iterator {
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      using MapType = std::map<RegisterId, LaneBitmask>;
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    private:
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      MapType Masks;
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      MapType::iterator Pos;
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      unsigned Index;
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      const RegisterAggr *Owner;
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    public:
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      rr_iterator(const RegisterAggr &RG, bool End);
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      RegisterRef operator*() const {
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        return RegisterRef(Pos->first, Pos->second);
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      }
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      rr_iterator &operator++() {
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        ++Pos;
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        ++Index;
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        return *this;
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      }
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      bool operator==(const rr_iterator &I) const {
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        assert(Owner == I.Owner);
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        (void)Owner;
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        return Index == I.Index;
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      }
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      bool operator!=(const rr_iterator &I) const {
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        return !(*this == I);
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      }
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    };
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    rr_iterator rr_begin() const {
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      return rr_iterator(*this, false);
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    }
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    rr_iterator rr_end() const {
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      return rr_iterator(*this, true);
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    }
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  private:
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    BitVector Units;
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    const PhysicalRegisterInfo &PRI;
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  };
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  // Optionally print the lane mask, if it is not ~0.
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  struct PrintLaneMaskOpt {
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0
    PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {}
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    LaneBitmask Mask;
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  };
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  raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P);
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} // end namespace rdf
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H