Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
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Source (jump to first uncovered line)
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//===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the LanaiTargetLowering class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "LanaiISelLowering.h"
14
#include "Lanai.h"
15
#include "LanaiCondCode.h"
16
#include "LanaiMachineFunctionInfo.h"
17
#include "LanaiSubtarget.h"
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#include "LanaiTargetObjectFile.h"
19
#include "MCTargetDesc/LanaiBaseInfo.h"
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#include "llvm/ADT/APInt.h"
21
#include "llvm/ADT/ArrayRef.h"
22
#include "llvm/ADT/SmallVector.h"
23
#include "llvm/ADT/StringRef.h"
24
#include "llvm/ADT/StringSwitch.h"
25
#include "llvm/CodeGen/CallingConvLower.h"
26
#include "llvm/CodeGen/MachineFrameInfo.h"
27
#include "llvm/CodeGen/MachineFunction.h"
28
#include "llvm/CodeGen/MachineMemOperand.h"
29
#include "llvm/CodeGen/MachineRegisterInfo.h"
30
#include "llvm/CodeGen/RuntimeLibcalls.h"
31
#include "llvm/CodeGen/SelectionDAG.h"
32
#include "llvm/CodeGen/SelectionDAGNodes.h"
33
#include "llvm/CodeGen/TargetCallingConv.h"
34
#include "llvm/CodeGen/ValueTypes.h"
35
#include "llvm/IR/CallingConv.h"
36
#include "llvm/IR/DerivedTypes.h"
37
#include "llvm/IR/Function.h"
38
#include "llvm/IR/GlobalValue.h"
39
#include "llvm/Support/Casting.h"
40
#include "llvm/Support/CodeGen.h"
41
#include "llvm/Support/CommandLine.h"
42
#include "llvm/Support/Debug.h"
43
#include "llvm/Support/ErrorHandling.h"
44
#include "llvm/Support/KnownBits.h"
45
#include "llvm/Support/MachineValueType.h"
46
#include "llvm/Support/MathExtras.h"
47
#include "llvm/Support/raw_ostream.h"
48
#include "llvm/Target/TargetMachine.h"
49
#include <cassert>
50
#include <cmath>
51
#include <cstdint>
52
#include <cstdlib>
53
#include <utility>
54
55
#define DEBUG_TYPE "lanai-lower"
56
57
using namespace llvm;
58
59
// Limit on number of instructions the lowered multiplication may have before a
60
// call to the library function should be generated instead. The threshold is
61
// currently set to 14 as this was the smallest threshold that resulted in all
62
// constant multiplications being lowered. A threshold of 5 covered all cases
63
// except for one multiplication which required 14. mulsi3 requires 16
64
// instructions (including the prologue and epilogue but excluding instructions
65
// at call site). Until we can inline mulsi3, generating at most 14 instructions
66
// will be faster than invoking mulsi3.
67
static cl::opt<int> LanaiLowerConstantMulThreshold(
68
    "lanai-constant-mul-threshold", cl::Hidden,
69
    cl::desc("Maximum number of instruction to generate when lowering constant "
70
             "multiplication instead of calling library function [default=14]"),
71
    cl::init(14));
72
73
LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
74
                                         const LanaiSubtarget &STI)
75
27
    : TargetLowering(TM) {
76
27
  // Set up the register classes.
77
27
  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
78
27
79
27
  // Compute derived properties from the register classes
80
27
  TRI = STI.getRegisterInfo();
81
27
  computeRegisterProperties(TRI);
82
27
83
27
  setStackPointerRegisterToSaveRestore(Lanai::SP);
84
27
85
27
  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
86
27
  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87
27
  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88
27
  setOperationAction(ISD::SETCC, MVT::i32, Custom);
89
27
  setOperationAction(ISD::SELECT, MVT::i32, Expand);
90
27
  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
91
27
92
27
  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
93
27
  setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
94
27
  setOperationAction(ISD::JumpTable, MVT::i32, Custom);
95
27
  setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
96
27
97
27
  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
98
27
  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
99
27
  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
100
27
101
27
  setOperationAction(ISD::VASTART, MVT::Other, Custom);
102
27
  setOperationAction(ISD::VAARG, MVT::Other, Expand);
103
27
  setOperationAction(ISD::VACOPY, MVT::Other, Expand);
104
27
  setOperationAction(ISD::VAEND, MVT::Other, Expand);
105
27
106
27
  setOperationAction(ISD::SDIV, MVT::i32, Expand);
107
27
  setOperationAction(ISD::UDIV, MVT::i32, Expand);
108
27
  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
109
27
  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
110
27
  setOperationAction(ISD::SREM, MVT::i32, Expand);
111
27
  setOperationAction(ISD::UREM, MVT::i32, Expand);
112
27
113
27
  setOperationAction(ISD::MUL, MVT::i32, Custom);
114
27
  setOperationAction(ISD::MULHU, MVT::i32, Expand);
115
27
  setOperationAction(ISD::MULHS, MVT::i32, Expand);
116
27
  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117
27
  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118
27
119
27
  setOperationAction(ISD::ROTR, MVT::i32, Expand);
120
27
  setOperationAction(ISD::ROTL, MVT::i32, Expand);
121
27
  setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
122
27
  setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
123
27
  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
124
27
125
27
  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
126
27
  setOperationAction(ISD::CTPOP, MVT::i32, Legal);
127
27
  setOperationAction(ISD::CTLZ, MVT::i32, Legal);
128
27
  setOperationAction(ISD::CTTZ, MVT::i32, Legal);
129
27
130
27
  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
131
27
  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
132
27
  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
133
27
134
27
  // Extended load operations for i1 types must be promoted
135
162
  for (MVT VT : MVT::integer_valuetypes()) {
136
162
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
137
162
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
138
162
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
139
162
  }
140
27
141
27
  setTargetDAGCombine(ISD::ADD);
142
27
  setTargetDAGCombine(ISD::SUB);
143
27
  setTargetDAGCombine(ISD::AND);
144
27
  setTargetDAGCombine(ISD::OR);
145
27
  setTargetDAGCombine(ISD::XOR);
146
27
147
27
  // Function alignments (log2)
148
27
  setMinFunctionAlignment(2);
149
27
  setPrefFunctionAlignment(2);
150
27
151
27
  setJumpIsExpensive(true);
152
27
153
27
  // TODO: Setting the minimum jump table entries needed before a
154
27
  // switch is transformed to a jump table to 100 to avoid creating jump tables
155
27
  // as this was causing bad performance compared to a large group of if
156
27
  // statements. Re-evaluate this on new benchmarks.
157
27
  setMinimumJumpTableEntries(100);
158
27
159
27
  // Use fast calling convention for library functions.
160
13.2k
  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; 
++I13.2k
) {
161
13.2k
    setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
162
13.2k
  }
163
27
164
27
  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
165
27
  MaxStoresPerMemsetOptSize = 8;
166
27
  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
167
27
  MaxStoresPerMemcpyOptSize = 8;
168
27
  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
169
27
  MaxStoresPerMemmoveOptSize = 8;
170
27
171
27
  // Booleans always contain 0 or 1.
172
27
  setBooleanContents(ZeroOrOneBooleanContent);
173
27
}
174
175
SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
176
103
                                            SelectionDAG &DAG) const {
177
103
  switch (Op.getOpcode()) {
178
103
  case ISD::MUL:
179
16
    return LowerMUL(Op, DAG);
180
103
  case ISD::BR_CC:
181
16
    return LowerBR_CC(Op, DAG);
182
103
  case ISD::ConstantPool:
183
0
    return LowerConstantPool(Op, DAG);
184
103
  case ISD::GlobalAddress:
185
9
    return LowerGlobalAddress(Op, DAG);
186
103
  case ISD::BlockAddress:
187
0
    return LowerBlockAddress(Op, DAG);
188
103
  case ISD::JumpTable:
189
0
    return LowerJumpTable(Op, DAG);
190
103
  case ISD::SELECT_CC:
191
25
    return LowerSELECT_CC(Op, DAG);
192
103
  case ISD::SETCC:
193
35
    return LowerSETCC(Op, DAG);
194
103
  case ISD::SHL_PARTS:
195
1
    return LowerSHL_PARTS(Op, DAG);
196
103
  case ISD::SRL_PARTS:
197
1
    return LowerSRL_PARTS(Op, DAG);
198
103
  case ISD::VASTART:
199
0
    return LowerVASTART(Op, DAG);
200
103
  case ISD::DYNAMIC_STACKALLOC:
201
0
    return LowerDYNAMIC_STACKALLOC(Op, DAG);
202
103
  case ISD::RETURNADDR:
203
0
    return LowerRETURNADDR(Op, DAG);
204
103
  case ISD::FRAMEADDR:
205
0
    return LowerFRAMEADDR(Op, DAG);
206
103
  default:
207
0
    llvm_unreachable("unimplemented operand");
208
103
  }
209
103
}
210
211
//===----------------------------------------------------------------------===//
212
//                       Lanai Inline Assembly Support
213
//===----------------------------------------------------------------------===//
214
215
unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
216
0
                                                SelectionDAG & /*DAG*/) const {
217
0
  // Only unallocatable registers should be matched here.
218
0
  unsigned Reg = StringSwitch<unsigned>(RegName)
219
0
                     .Case("pc", Lanai::PC)
220
0
                     .Case("sp", Lanai::SP)
221
0
                     .Case("fp", Lanai::FP)
222
0
                     .Case("rr1", Lanai::RR1)
223
0
                     .Case("r10", Lanai::R10)
224
0
                     .Case("rr2", Lanai::RR2)
225
0
                     .Case("r11", Lanai::R11)
226
0
                     .Case("rca", Lanai::RCA)
227
0
                     .Default(0);
228
0
229
0
  if (Reg)
230
0
    return Reg;
231
0
  report_fatal_error("Invalid register name global variable");
232
0
}
233
234
std::pair<unsigned, const TargetRegisterClass *>
235
LanaiTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
236
                                                  StringRef Constraint,
237
3
                                                  MVT VT) const {
238
3
  if (Constraint.size() == 1)
239
3
    // GCC Constraint Letters
240
3
    switch (Constraint[0]) {
241
3
    case 'r': // GENERAL_REGS
242
0
      return std::make_pair(0U, &Lanai::GPRRegClass);
243
3
    default:
244
3
      break;
245
3
    }
246
3
247
3
  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
248
3
}
249
250
// Examine constraint type and operand type and determine a weight value.
251
// This object must already have been set up with the operand type
252
// and the current alternative constraint selected.
253
TargetLowering::ConstraintWeight
254
LanaiTargetLowering::getSingleConstraintMatchWeight(
255
0
    AsmOperandInfo &Info, const char *Constraint) const {
256
0
  ConstraintWeight Weight = CW_Invalid;
257
0
  Value *CallOperandVal = Info.CallOperandVal;
258
0
  // If we don't have a value, we can't do a match,
259
0
  // but allow it at the lowest weight.
260
0
  if (CallOperandVal == nullptr)
261
0
    return CW_Default;
262
0
  // Look at the constraint type.
263
0
  switch (*Constraint) {
264
0
  case 'I': // signed 16 bit immediate
265
0
  case 'J': // integer zero
266
0
  case 'K': // unsigned 16 bit immediate
267
0
  case 'L': // immediate in the range 0 to 31
268
0
  case 'M': // signed 32 bit immediate where lower 16 bits are 0
269
0
  case 'N': // signed 26 bit immediate
270
0
  case 'O': // integer zero
271
0
    if (isa<ConstantInt>(CallOperandVal))
272
0
      Weight = CW_Constant;
273
0
    break;
274
0
  default:
275
0
    Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
276
0
    break;
277
0
  }
278
0
  return Weight;
279
0
}
280
281
// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
282
// vector.  If it is invalid, don't add anything to Ops.
283
void LanaiTargetLowering::LowerAsmOperandForConstraint(
284
    SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
285
3
    SelectionDAG &DAG) const {
286
3
  SDValue Result(nullptr, 0);
287
3
288
3
  // Only support length 1 constraints for now.
289
3
  if (Constraint.length() > 1)
290
0
    return;
291
3
292
3
  char ConstraintLetter = Constraint[0];
293
3
  switch (ConstraintLetter) {
294
3
  case 'I': // Signed 16 bit constant
295
0
    // If this fails, the parent routine will give an error
296
0
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
297
0
      if (isInt<16>(C->getSExtValue())) {
298
0
        Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
299
0
                                       Op.getValueType());
300
0
        break;
301
0
      }
302
0
    }
303
0
    return;
304
0
  case 'J': // integer zero
305
0
  case 'O':
306
0
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
307
0
      if (C->getZExtValue() == 0) {
308
0
        Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
309
0
        break;
310
0
      }
311
0
    }
312
0
    return;
313
0
  case 'K': // unsigned 16 bit immediate
314
0
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
315
0
      if (isUInt<16>(C->getZExtValue())) {
316
0
        Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
317
0
                                       Op.getValueType());
318
0
        break;
319
0
      }
320
0
    }
321
0
    return;
322
0
  case 'L': // immediate in the range 0 to 31
323
0
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
324
0
      if (C->getZExtValue() <= 31) {
325
0
        Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
326
0
                                       Op.getValueType());
327
0
        break;
328
0
      }
329
0
    }
330
0
    return;
331
0
  case 'M': // signed 32 bit immediate where lower 16 bits are 0
332
0
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
333
0
      int64_t Val = C->getSExtValue();
334
0
      if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
335
0
        Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
336
0
        break;
337
0
      }
338
0
    }
339
0
    return;
340
0
  case 'N': // signed 26 bit immediate
341
0
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
342
0
      int64_t Val = C->getSExtValue();
343
0
      if ((Val >= -33554432) && (Val <= 33554431)) {
344
0
        Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
345
0
        break;
346
0
      }
347
0
    }
348
0
    return;
349
3
  default:
350
3
    break; // This will fall through to the generic implementation
351
3
  }
352
3
353
3
  if (Result.getNode()) {
354
0
    Ops.push_back(Result);
355
0
    return;
356
0
  }
357
3
358
3
  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
359
3
}
360
361
//===----------------------------------------------------------------------===//
362
//                      Calling Convention Implementation
363
//===----------------------------------------------------------------------===//
364
365
#include "LanaiGenCallingConv.inc"
366
367
static unsigned NumFixedArgs;
368
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
369
                              CCValAssign::LocInfo LocInfo,
370
0
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
371
0
  // Handle fixed arguments with default CC.
372
0
  // Note: Both the default and fast CC handle VarArg the same and hence the
373
0
  // calling convention of the function is not considered here.
374
0
  if (ValNo < NumFixedArgs) {
375
0
    return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
376
0
  }
377
0
378
0
  // Promote i8/i16 args to i32
379
0
  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
380
0
    LocVT = MVT::i32;
381
0
    if (ArgFlags.isSExt())
382
0
      LocInfo = CCValAssign::SExt;
383
0
    else if (ArgFlags.isZExt())
384
0
      LocInfo = CCValAssign::ZExt;
385
0
    else
386
0
      LocInfo = CCValAssign::AExt;
387
0
  }
388
0
389
0
  // VarArgs get passed on stack
390
0
  unsigned Offset = State.AllocateStack(4, 4);
391
0
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
392
0
  return false;
393
0
}
394
395
SDValue LanaiTargetLowering::LowerFormalArguments(
396
    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
397
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
398
92
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
399
92
  switch (CallConv) {
400
92
  case CallingConv::C:
401
92
  case CallingConv::Fast:
402
92
    return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
403
92
  default:
404
0
    report_fatal_error("Unsupported calling convention");
405
92
  }
406
92
}
407
408
SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
409
13
                                       SmallVectorImpl<SDValue> &InVals) const {
410
13
  SelectionDAG &DAG = CLI.DAG;
411
13
  SDLoc &DL = CLI.DL;
412
13
  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
413
13
  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
414
13
  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
415
13
  SDValue Chain = CLI.Chain;
416
13
  SDValue Callee = CLI.Callee;
417
13
  bool &IsTailCall = CLI.IsTailCall;
418
13
  CallingConv::ID CallConv = CLI.CallConv;
419
13
  bool IsVarArg = CLI.IsVarArg;
420
13
421
13
  // Lanai target does not yet support tail call optimization.
422
13
  IsTailCall = false;
423
13
424
13
  switch (CallConv) {
425
13
  case CallingConv::Fast:
426
13
  case CallingConv::C:
427
13
    return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
428
13
                          OutVals, Ins, DL, DAG, InVals);
429
13
  default:
430
0
    report_fatal_error("Unsupported calling convention");
431
13
  }
432
13
}
433
434
// LowerCCCArguments - transform physical registers into virtual registers and
435
// generate load operations for arguments places on the stack.
436
SDValue LanaiTargetLowering::LowerCCCArguments(
437
    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
438
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
439
92
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
440
92
  MachineFunction &MF = DAG.getMachineFunction();
441
92
  MachineFrameInfo &MFI = MF.getFrameInfo();
442
92
  MachineRegisterInfo &RegInfo = MF.getRegInfo();
443
92
  LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
444
92
445
92
  // Assign locations to all of the incoming arguments.
446
92
  SmallVector<CCValAssign, 16> ArgLocs;
447
92
  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
448
92
                 *DAG.getContext());
449
92
  if (CallConv == CallingConv::Fast) {
450
0
    CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
451
92
  } else {
452
92
    CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
453
92
  }
454
92
455
252
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i160
) {
456
160
    CCValAssign &VA = ArgLocs[i];
457
160
    if (VA.isRegLoc()) {
458
108
      // Arguments passed in registers
459
108
      EVT RegVT = VA.getLocVT();
460
108
      switch (RegVT.getSimpleVT().SimpleTy) {
461
108
      case MVT::i32: {
462
108
        unsigned VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
463
108
        RegInfo.addLiveIn(VA.getLocReg(), VReg);
464
108
        SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
465
108
466
108
        // If this is an 8/16-bit value, it is really passed promoted to 32
467
108
        // bits. Insert an assert[sz]ext to capture this, then truncate to the
468
108
        // right size.
469
108
        if (VA.getLocInfo() == CCValAssign::SExt)
470
0
          ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
471
0
                                 DAG.getValueType(VA.getValVT()));
472
108
        else if (VA.getLocInfo() == CCValAssign::ZExt)
473
0
          ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
474
0
                                 DAG.getValueType(VA.getValVT()));
475
108
476
108
        if (VA.getLocInfo() != CCValAssign::Full)
477
0
          ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
478
108
479
108
        InVals.push_back(ArgValue);
480
108
        break;
481
108
      }
482
108
      default:
483
0
        LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
484
0
                          << RegVT.getEVTString() << "\n");
485
0
        llvm_unreachable("unhandled argument type");
486
52
      }
487
52
    } else {
488
52
      // Sanity check
489
52
      assert(VA.isMemLoc());
490
52
      // Load the argument to a virtual register
491
52
      unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
492
52
      // Check that the argument fits in stack slot
493
52
      if (ObjSize > 4) {
494
0
        errs() << "LowerFormalArguments Unhandled argument type: "
495
0
               << EVT(VA.getLocVT()).getEVTString() << "\n";
496
0
      }
497
52
      // Create the frame index object for this incoming parameter...
498
52
      int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
499
52
500
52
      // Create the SelectionDAG nodes corresponding to a load
501
52
      // from this parameter
502
52
      SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
503
52
      InVals.push_back(DAG.getLoad(
504
52
          VA.getLocVT(), DL, Chain, FIN,
505
52
          MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
506
52
    }
507
160
  }
508
92
509
92
  // The Lanai ABI for returning structs by value requires that we copy
510
92
  // the sret argument into rv for the return. Save the argument into
511
92
  // a virtual register so that we can access it from the return points.
512
92
  if (MF.getFunction().hasStructRetAttr()) {
513
0
    unsigned Reg = LanaiMFI->getSRetReturnReg();
514
0
    if (!Reg) {
515
0
      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
516
0
      LanaiMFI->setSRetReturnReg(Reg);
517
0
    }
518
0
    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
519
0
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
520
0
  }
521
92
522
92
  if (IsVarArg) {
523
0
    // Record the frame index of the first variable argument
524
0
    // which is a value necessary to VASTART.
525
0
    int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
526
0
    LanaiMFI->setVarArgsFrameIndex(FI);
527
0
  }
528
92
529
92
  return Chain;
530
92
}
531
532
SDValue
533
LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
534
                                 bool IsVarArg,
535
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
536
                                 const SmallVectorImpl<SDValue> &OutVals,
537
92
                                 const SDLoc &DL, SelectionDAG &DAG) const {
538
92
  // CCValAssign - represent the assignment of the return value to a location
539
92
  SmallVector<CCValAssign, 16> RVLocs;
540
92
541
92
  // CCState - Info about the registers and stack slot.
542
92
  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
543
92
                 *DAG.getContext());
544
92
545
92
  // Analize return values.
546
92
  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
547
92
548
92
  SDValue Flag;
549
92
  SmallVector<SDValue, 4> RetOps(1, Chain);
550
92
551
92
  // Copy the result values into the output registers.
552
183
  for (unsigned i = 0; i != RVLocs.size(); 
++i91
) {
553
91
    CCValAssign &VA = RVLocs[i];
554
91
    assert(VA.isRegLoc() && "Can only return in registers!");
555
91
556
91
    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
557
91
558
91
    // Guarantee that all emitted copies are stuck together with flags.
559
91
    Flag = Chain.getValue(1);
560
91
    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
561
91
  }
562
92
563
92
  // The Lanai ABI for returning structs by value requires that we copy
564
92
  // the sret argument into rv for the return. We saved the argument into
565
92
  // a virtual register in the entry block, so now we copy the value out
566
92
  // and into rv.
567
92
  if (DAG.getMachineFunction().getFunction().hasStructRetAttr()) {
568
0
    MachineFunction &MF = DAG.getMachineFunction();
569
0
    LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
570
0
    unsigned Reg = LanaiMFI->getSRetReturnReg();
571
0
    assert(Reg &&
572
0
           "SRetReturnReg should have been set in LowerFormalArguments().");
573
0
    SDValue Val =
574
0
        DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
575
0
576
0
    Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
577
0
    Flag = Chain.getValue(1);
578
0
    RetOps.push_back(
579
0
        DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
580
0
  }
581
92
582
92
  RetOps[0] = Chain; // Update chain
583
92
584
92
  unsigned Opc = LanaiISD::RET_FLAG;
585
92
  if (Flag.getNode())
586
89
    RetOps.push_back(Flag);
587
92
588
92
  // Return Void
589
92
  return DAG.getNode(Opc, DL, MVT::Other,
590
92
                     ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
591
92
}
592
593
// LowerCCCCallTo - functions arguments are copied from virtual regs to
594
// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
595
SDValue LanaiTargetLowering::LowerCCCCallTo(
596
    SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
597
    bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
598
    const SmallVectorImpl<SDValue> &OutVals,
599
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
600
13
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
601
13
  // Analyze operands of the call, assigning locations to each operand.
602
13
  SmallVector<CCValAssign, 16> ArgLocs;
603
13
  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
604
13
                 *DAG.getContext());
605
13
  GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
606
13
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
607
13
608
13
  NumFixedArgs = 0;
609
13
  if (IsVarArg && 
G0
) {
610
0
    const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
611
0
    if (CalleeFn)
612
0
      NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
613
0
  }
614
13
  if (NumFixedArgs)
615
0
    CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
616
13
  else {
617
13
    if (CallConv == CallingConv::Fast)
618
7
      CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
619
6
    else
620
6
      CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
621
13
  }
622
13
623
13
  // Get a count of how many bytes are to be pushed on the stack.
624
13
  unsigned NumBytes = CCInfo.getNextStackOffset();
625
13
626
13
  // Create local copies for byval args.
627
13
  SmallVector<SDValue, 8> ByValArgs;
628
31
  for (unsigned I = 0, E = Outs.size(); I != E; 
++I18
) {
629
18
    ISD::ArgFlagsTy Flags = Outs[I].Flags;
630
18
    if (!Flags.isByVal())
631
18
      continue;
632
0
633
0
    SDValue Arg = OutVals[I];
634
0
    unsigned Size = Flags.getByValSize();
635
0
    unsigned Align = Flags.getByValAlign();
636
0
637
0
    int FI = MFI.CreateStackObject(Size, Align, false);
638
0
    SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
639
0
    SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
640
0
641
0
    Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
642
0
                          /*IsVolatile=*/false,
643
0
                          /*AlwaysInline=*/false,
644
0
                          /*isTailCall=*/false, MachinePointerInfo(),
645
0
                          MachinePointerInfo());
646
0
    ByValArgs.push_back(FIPtr);
647
0
  }
648
13
649
13
  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
650
13
651
13
  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
652
13
  SmallVector<SDValue, 12> MemOpChains;
653
13
  SDValue StackPtr;
654
13
655
13
  // Walk the register/memloc assignments, inserting copies/loads.
656
31
  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; 
++I18
) {
657
18
    CCValAssign &VA = ArgLocs[I];
658
18
    SDValue Arg = OutVals[I];
659
18
    ISD::ArgFlagsTy Flags = Outs[I].Flags;
660
18
661
18
    // Promote the value if needed.
662
18
    switch (VA.getLocInfo()) {
663
18
    case CCValAssign::Full:
664
18
      break;
665
18
    case CCValAssign::SExt:
666
0
      Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
667
0
      break;
668
18
    case CCValAssign::ZExt:
669
0
      Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
670
0
      break;
671
18
    case CCValAssign::AExt:
672
0
      Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
673
0
      break;
674
18
    default:
675
0
      llvm_unreachable("Unknown loc info!");
676
18
    }
677
18
678
18
    // Use local copy if it is a byval arg.
679
18
    if (Flags.isByVal())
680
0
      Arg = ByValArgs[J++];
681
18
682
18
    // Arguments that can be passed on register must be kept at RegsToPass
683
18
    // vector
684
18
    if (VA.isRegLoc()) {
685
16
      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
686
16
    } else {
687
2
      assert(VA.isMemLoc());
688
2
689
2
      if (StackPtr.getNode() == nullptr)
690
2
        StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
691
2
                                      getPointerTy(DAG.getDataLayout()));
692
2
693
2
      SDValue PtrOff =
694
2
          DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
695
2
                      DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
696
2
697
2
      MemOpChains.push_back(
698
2
          DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
699
2
    }
700
18
  }
701
13
702
13
  // Transform all store nodes into one single node because all store nodes are
703
13
  // independent of each other.
704
13
  if (!MemOpChains.empty())
705
2
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
706
2
                        ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
707
13
708
13
  SDValue InFlag;
709
13
710
13
  // Build a sequence of copy-to-reg nodes chained together with token chain and
711
13
  // flag operands which copy the outgoing args into registers.  The InFlag in
712
13
  // necessary since all emitted instructions must be stuck together.
713
29
  for (unsigned I = 0, E = RegsToPass.size(); I != E; 
++I16
) {
714
16
    Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
715
16
                             RegsToPass[I].second, InFlag);
716
16
    InFlag = Chain.getValue(1);
717
16
  }
718
13
719
13
  // If the callee is a GlobalAddress node (quite common, every direct call is)
720
13
  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
721
13
  // Likewise ExternalSymbol -> TargetExternalSymbol.
722
13
  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
723
13
  if (G) {
724
6
    Callee = DAG.getTargetGlobalAddress(
725
6
        G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
726
7
  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
727
7
    Callee = DAG.getTargetExternalSymbol(
728
7
        E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
729
7
  }
730
13
731
13
  // Returns a chain & a flag for retval copy to use.
732
13
  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
733
13
  SmallVector<SDValue, 8> Ops;
734
13
  Ops.push_back(Chain);
735
13
  Ops.push_back(Callee);
736
13
737
13
  // Add a register mask operand representing the call-preserved registers.
738
13
  // TODO: Should return-twice functions be handled?
739
13
  const uint32_t *Mask =
740
13
      TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
741
13
  assert(Mask && "Missing call preserved mask for calling convention");
742
13
  Ops.push_back(DAG.getRegisterMask(Mask));
743
13
744
13
  // Add argument registers to the end of the list so that they are
745
13
  // known live into the call.
746
29
  for (unsigned I = 0, E = RegsToPass.size(); I != E; 
++I16
)
747
16
    Ops.push_back(DAG.getRegister(RegsToPass[I].first,
748
16
                                  RegsToPass[I].second.getValueType()));
749
13
750
13
  if (InFlag.getNode())
751
9
    Ops.push_back(InFlag);
752
13
753
13
  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
754
13
                      ArrayRef<SDValue>(&Ops[0], Ops.size()));
755
13
  InFlag = Chain.getValue(1);
756
13
757
13
  // Create the CALLSEQ_END node.
758
13
  Chain = DAG.getCALLSEQ_END(
759
13
      Chain,
760
13
      DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
761
13
      DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
762
13
      DL);
763
13
  InFlag = Chain.getValue(1);
764
13
765
13
  // Handle result values, copying them out of physregs into vregs that we
766
13
  // return.
767
13
  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
768
13
                         InVals);
769
13
}
770
771
// LowerCallResult - Lower the result values of a call into the
772
// appropriate copies out of appropriate physical registers.
773
SDValue LanaiTargetLowering::LowerCallResult(
774
    SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
775
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
776
13
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
777
13
  // Assign locations to each value returned by this call.
778
13
  SmallVector<CCValAssign, 16> RVLocs;
779
13
  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
780
13
                 *DAG.getContext());
781
13
782
13
  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
783
13
784
13
  // Copy all of the result registers out of their specified physreg.
785
22
  for (unsigned I = 0; I != RVLocs.size(); 
++I9
) {
786
9
    Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
787
9
                               RVLocs[I].getValVT(), InFlag)
788
9
                .getValue(1);
789
9
    InFlag = Chain.getValue(2);
790
9
    InVals.push_back(Chain.getValue(0));
791
9
  }
792
13
793
13
  return Chain;
794
13
}
795
796
//===----------------------------------------------------------------------===//
797
//                      Custom Lowerings
798
//===----------------------------------------------------------------------===//
799
800
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL,
801
76
                                        SDValue &RHS, SelectionDAG &DAG) {
802
76
  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
803
76
804
76
  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
805
76
  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
806
76
  // and Lanai only supports integer comparisons, so only provide definitions
807
76
  // for them.
808
76
  switch (SetCCOpcode) {
809
76
  case ISD::SETEQ:
810
19
    return LPCC::ICC_EQ;
811
76
  case ISD::SETGT:
812
6
    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
813
1
      if (RHSC->getZExtValue() == 0xFFFFFFFF) {
814
0
        // X > -1 -> X >= 0 -> is_plus(X)
815
0
        RHS = DAG.getConstant(0, DL, RHS.getValueType());
816
0
        return LPCC::ICC_PL;
817
0
      }
818
6
    return LPCC::ICC_GT;
819
6
  case ISD::SETUGT:
820
5
    return LPCC::ICC_UGT;
821
8
  case ISD::SETLT:
822
8
    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
823
5
      if (RHSC->getZExtValue() == 0)
824
0
        // X < 0 -> is_minus(X)
825
0
        return LPCC::ICC_MI;
826
8
    return LPCC::ICC_LT;
827
8
  case ISD::SETULT:
828
8
    return LPCC::ICC_ULT;
829
8
  case ISD::SETLE:
830
4
    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
831
2
      if (RHSC->getZExtValue() == 0xFFFFFFFF) {
832
0
        // X <= -1 -> X < 0 -> is_minus(X)
833
0
        RHS = DAG.getConstant(0, DL, RHS.getValueType());
834
0
        return LPCC::ICC_MI;
835
0
      }
836
4
    return LPCC::ICC_LE;
837
4
  case ISD::SETULE:
838
4
    return LPCC::ICC_ULE;
839
4
  case ISD::SETGE:
840
4
    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
841
2
      if (RHSC->getZExtValue() == 0)
842
2
        // X >= 0 -> is_plus(X)
843
2
        return LPCC::ICC_PL;
844
2
    return LPCC::ICC_GE;
845
5
  case ISD::SETUGE:
846
5
    return LPCC::ICC_UGE;
847
13
  case ISD::SETNE:
848
13
    return LPCC::ICC_NE;
849
2
  case ISD::SETONE:
850
0
  case ISD::SETUNE:
851
0
  case ISD::SETOGE:
852
0
  case ISD::SETOLE:
853
0
  case ISD::SETOLT:
854
0
  case ISD::SETOGT:
855
0
  case ISD::SETOEQ:
856
0
  case ISD::SETUEQ:
857
0
  case ISD::SETO:
858
0
  case ISD::SETUO:
859
0
    llvm_unreachable("Unsupported comparison.");
860
0
  default:
861
0
    llvm_unreachable("Unknown integer condition code!");
862
76
  }
863
76
}
864
865
16
SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
866
16
  SDValue Chain = Op.getOperand(0);
867
16
  SDValue Cond = Op.getOperand(1);
868
16
  SDValue LHS = Op.getOperand(2);
869
16
  SDValue RHS = Op.getOperand(3);
870
16
  SDValue Dest = Op.getOperand(4);
871
16
  SDLoc DL(Op);
872
16
873
16
  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
874
16
  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
875
16
  SDValue Flag =
876
16
      DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
877
16
878
16
  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
879
16
                     TargetCC, Flag);
880
16
}
881
882
16
SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
883
16
  EVT VT = Op->getValueType(0);
884
16
  if (VT != MVT::i32)
885
0
    return SDValue();
886
16
887
16
  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
888
16
  if (!C)
889
1
    return SDValue();
890
15
891
15
  int64_t MulAmt = C->getSExtValue();
892
15
  int32_t HighestOne = -1;
893
15
  uint32_t NonzeroEntries = 0;
894
15
  int SignedDigit[32] = {0};
895
15
896
15
  // Convert to non-adjacent form (NAF) signed-digit representation.
897
15
  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
898
15
  // minimal Hamming weight representation of a number (on average 1/3 of the
899
15
  // digits will be non-zero vs 1/2 for regular binary representation). And as
900
15
  // the non-zero digits will be the only digits contributing to the instruction
901
15
  // count, this is desirable. The next loop converts it to NAF (following the
902
15
  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
903
15
  // choosing the non-zero coefficients such that the resulting quotient is
904
15
  // divisible by 2 which will cause the next coefficient to be zero.
905
15
  int64_t E = std::abs(MulAmt);
906
15
  int S = (MulAmt < 0 ? 
-18
:
17
);
907
15
  int I = 0;
908
136
  while (E > 0) {
909
121
    int ZI = 0;
910
121
    if (E % 2 == 1) {
911
58
      ZI = 2 - (E % 4);
912
58
      if (ZI != 0)
913
58
        ++NonzeroEntries;
914
58
    }
915
121
    SignedDigit[I] = S * ZI;
916
121
    if (SignedDigit[I] == 1)
917
14
      HighestOne = I;
918
121
    E = (E - ZI) / 2;
919
121
    ++I;
920
121
  }
921
15
922
15
  // Compute number of instructions required. Due to differences in lowering
923
15
  // between the different processors this count is not exact.
924
15
  // Start by assuming a shift and a add/sub for every non-zero entry (hence
925
15
  // every non-zero entry requires 1 shift and 1 add/sub except for the first
926
15
  // entry).
927
15
  int32_t InstrRequired = 2 * NonzeroEntries - 1;
928
15
  // Correct possible over-adding due to shift by 0 (which is not emitted).
929
15
  if (std::abs(MulAmt) % 2 == 1)
930
8
    --InstrRequired;
931
15
  // Return if the form generated would exceed the instruction threshold.
932
15
  if (InstrRequired > LanaiLowerConstantMulThreshold)
933
2
    return SDValue();
934
13
935
13
  SDValue Res;
936
13
  SDLoc DL(Op);
937
13
  SDValue V = Op->getOperand(0);
938
13
939
13
  // Initialize the running sum. Set the running sum to the maximal shifted
940
13
  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
941
13
  // term NAF).
942
13
  if (HighestOne == -1)
943
2
    Res = DAG.getConstant(0, DL, MVT::i32);
944
11
  else {
945
11
    Res = DAG.getNode(ISD::SHL, DL, VT, V,
946
11
                      DAG.getConstant(HighestOne, DL, MVT::i32));
947
11
    SignedDigit[HighestOne] = 0;
948
11
  }
949
13
950
13
  // Assemble multiplication from shift, add, sub using NAF form and running
951
13
  // sum.
952
429
  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
953
416
       ++I) {
954
416
    if (SignedDigit[I] == 0)
955
401
      continue;
956
15
957
15
    // Shifted multiplicand (v<<i).
958
15
    SDValue Op =
959
15
        DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
960
15
    if (SignedDigit[I] == 1)
961
3
      Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
962
12
    else if (SignedDigit[I] == -1)
963
12
      Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
964
15
  }
965
13
  return Res;
966
13
}
967
968
35
SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
969
35
  SDValue LHS = Op.getOperand(0);
970
35
  SDValue RHS = Op.getOperand(1);
971
35
  SDValue Cond = Op.getOperand(2);
972
35
  SDLoc DL(Op);
973
35
974
35
  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
975
35
  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
976
35
  SDValue Flag =
977
35
      DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
978
35
979
35
  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
980
35
}
981
982
SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
983
25
                                            SelectionDAG &DAG) const {
984
25
  SDValue LHS = Op.getOperand(0);
985
25
  SDValue RHS = Op.getOperand(1);
986
25
  SDValue TrueV = Op.getOperand(2);
987
25
  SDValue FalseV = Op.getOperand(3);
988
25
  SDValue Cond = Op.getOperand(4);
989
25
  SDLoc DL(Op);
990
25
991
25
  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
992
25
  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
993
25
  SDValue Flag =
994
25
      DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
995
25
996
25
  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
997
25
  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
998
25
                     Flag);
999
25
}
1000
1001
0
SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1002
0
  MachineFunction &MF = DAG.getMachineFunction();
1003
0
  LanaiMachineFunctionInfo *FuncInfo = MF.getInfo<LanaiMachineFunctionInfo>();
1004
0
1005
0
  SDLoc DL(Op);
1006
0
  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1007
0
                                 getPointerTy(DAG.getDataLayout()));
1008
0
1009
0
  // vastart just stores the address of the VarArgsFrameIndex slot into the
1010
0
  // memory location argument.
1011
0
  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1012
0
  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1013
0
                      MachinePointerInfo(SV));
1014
0
}
1015
1016
SDValue LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1017
0
                                                     SelectionDAG &DAG) const {
1018
0
  SDValue Chain = Op.getOperand(0);
1019
0
  SDValue Size = Op.getOperand(1);
1020
0
  SDLoc DL(Op);
1021
0
1022
0
  unsigned SPReg = getStackPointerRegisterToSaveRestore();
1023
0
1024
0
  // Get a reference to the stack pointer.
1025
0
  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1026
0
1027
0
  // Subtract the dynamic size from the actual stack size to
1028
0
  // obtain the new stack size.
1029
0
  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1030
0
1031
0
  // For Lanai, the outgoing memory arguments area should be on top of the
1032
0
  // alloca area on the stack i.e., the outgoing memory arguments should be
1033
0
  // at a lower address than the alloca area. Move the alloca area down the
1034
0
  // stack by adding back the space reserved for outgoing arguments to SP
1035
0
  // here.
1036
0
  //
1037
0
  // We do not know what the size of the outgoing args is at this point.
1038
0
  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1039
0
  // stack pointer. We replace this instruction with on that has the correct,
1040
0
  // known offset in emitPrologue().
1041
0
  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1042
0
1043
0
  // The Sub result contains the new stack start address, so it
1044
0
  // must be placed in the stack pointer register.
1045
0
  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1046
0
1047
0
  SDValue Ops[2] = {ArgAdjust, CopyChain};
1048
0
  return DAG.getMergeValues(Ops, DL);
1049
0
}
1050
1051
SDValue LanaiTargetLowering::LowerRETURNADDR(SDValue Op,
1052
0
                                             SelectionDAG &DAG) const {
1053
0
  MachineFunction &MF = DAG.getMachineFunction();
1054
0
  MachineFrameInfo &MFI = MF.getFrameInfo();
1055
0
  MFI.setReturnAddressIsTaken(true);
1056
0
1057
0
  EVT VT = Op.getValueType();
1058
0
  SDLoc DL(Op);
1059
0
  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1060
0
  if (Depth) {
1061
0
    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1062
0
    const unsigned Offset = -4;
1063
0
    SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1064
0
                              DAG.getIntPtrConstant(Offset, DL));
1065
0
    return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1066
0
  }
1067
0
1068
0
  // Return the link register, which contains the return address.
1069
0
  // Mark it an implicit live-in.
1070
0
  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1071
0
  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1072
0
}
1073
1074
SDValue LanaiTargetLowering::LowerFRAMEADDR(SDValue Op,
1075
0
                                            SelectionDAG &DAG) const {
1076
0
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1077
0
  MFI.setFrameAddressIsTaken(true);
1078
0
1079
0
  EVT VT = Op.getValueType();
1080
0
  SDLoc DL(Op);
1081
0
  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1082
0
  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1083
0
  while (Depth--) {
1084
0
    const unsigned Offset = -8;
1085
0
    SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1086
0
                              DAG.getIntPtrConstant(Offset, DL));
1087
0
    FrameAddr =
1088
0
        DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1089
0
  }
1090
0
  return FrameAddr;
1091
0
}
1092
1093
const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1094
  switch (Opcode) {
1095
  case LanaiISD::ADJDYNALLOC:
1096
    return "LanaiISD::ADJDYNALLOC";
1097
  case LanaiISD::RET_FLAG:
1098
    return "LanaiISD::RET_FLAG";
1099
  case LanaiISD::CALL:
1100
    return "LanaiISD::CALL";
1101
  case LanaiISD::SELECT_CC:
1102
    return "LanaiISD::SELECT_CC";
1103
  case LanaiISD::SETCC:
1104
    return "LanaiISD::SETCC";
1105
  case LanaiISD::SUBBF:
1106
    return "LanaiISD::SUBBF";
1107
  case LanaiISD::SET_FLAG:
1108
    return "LanaiISD::SET_FLAG";
1109
  case LanaiISD::BR_CC:
1110
    return "LanaiISD::BR_CC";
1111
  case LanaiISD::Wrapper:
1112
    return "LanaiISD::Wrapper";
1113
  case LanaiISD::HI:
1114
    return "LanaiISD::HI";
1115
  case LanaiISD::LO:
1116
    return "LanaiISD::LO";
1117
  case LanaiISD::SMALL:
1118
    return "LanaiISD::SMALL";
1119
  default:
1120
    return nullptr;
1121
  }
1122
}
1123
1124
SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op,
1125
0
                                               SelectionDAG &DAG) const {
1126
0
  SDLoc DL(Op);
1127
0
  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1128
0
  const Constant *C = N->getConstVal();
1129
0
  const LanaiTargetObjectFile *TLOF =
1130
0
      static_cast<const LanaiTargetObjectFile *>(
1131
0
          getTargetMachine().getObjFileLowering());
1132
0
1133
0
  // If the code model is small or constant will be placed in the small section,
1134
0
  // then assume address will fit in 21-bits.
1135
0
  if (getTargetMachine().getCodeModel() == CodeModel::Small ||
1136
0
      TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1137
0
    SDValue Small = DAG.getTargetConstantPool(
1138
0
        C, MVT::i32, N->getAlignment(), N->getOffset(), LanaiII::MO_NO_FLAG);
1139
0
    return DAG.getNode(ISD::OR, DL, MVT::i32,
1140
0
                       DAG.getRegister(Lanai::R0, MVT::i32),
1141
0
                       DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1142
0
  } else {
1143
0
    uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1144
0
    uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1145
0
1146
0
    SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1147
0
                                           N->getOffset(), OpFlagHi);
1148
0
    SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1149
0
                                           N->getOffset(), OpFlagLo);
1150
0
    Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1151
0
    Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1152
0
    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1153
0
    return Result;
1154
0
  }
1155
0
}
1156
1157
SDValue LanaiTargetLowering::LowerGlobalAddress(SDValue Op,
1158
9
                                                SelectionDAG &DAG) const {
1159
9
  SDLoc DL(Op);
1160
9
  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1161
9
  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1162
9
1163
9
  const LanaiTargetObjectFile *TLOF =
1164
9
      static_cast<const LanaiTargetObjectFile *>(
1165
9
          getTargetMachine().getObjFileLowering());
1166
9
1167
9
  // If the code model is small or global variable will be placed in the small
1168
9
  // section, then assume address will fit in 21-bits.
1169
9
  const GlobalObject *GO = GV->getBaseObject();
1170
9
  if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1171
2
    SDValue Small = DAG.getTargetGlobalAddress(
1172
2
        GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1173
2
    return DAG.getNode(ISD::OR, DL, MVT::i32,
1174
2
                       DAG.getRegister(Lanai::R0, MVT::i32),
1175
2
                       DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1176
7
  } else {
1177
7
    uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1178
7
    uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1179
7
1180
7
    // Create the TargetGlobalAddress node, folding in the constant offset.
1181
7
    SDValue Hi = DAG.getTargetGlobalAddress(
1182
7
        GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1183
7
    SDValue Lo = DAG.getTargetGlobalAddress(
1184
7
        GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1185
7
    Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1186
7
    Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1187
7
    return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1188
7
  }
1189
9
}
1190
1191
SDValue LanaiTargetLowering::LowerBlockAddress(SDValue Op,
1192
0
                                               SelectionDAG &DAG) const {
1193
0
  SDLoc DL(Op);
1194
0
  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1195
0
1196
0
  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1197
0
  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1198
0
1199
0
  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1200
0
  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1201
0
  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1202
0
  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1203
0
  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1204
0
  return Result;
1205
0
}
1206
1207
SDValue LanaiTargetLowering::LowerJumpTable(SDValue Op,
1208
0
                                            SelectionDAG &DAG) const {
1209
0
  SDLoc DL(Op);
1210
0
  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1211
0
1212
0
  // If the code model is small assume address will fit in 21-bits.
1213
0
  if (getTargetMachine().getCodeModel() == CodeModel::Small) {
1214
0
    SDValue Small = DAG.getTargetJumpTable(
1215
0
        JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1216
0
    return DAG.getNode(ISD::OR, DL, MVT::i32,
1217
0
                       DAG.getRegister(Lanai::R0, MVT::i32),
1218
0
                       DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1219
0
  } else {
1220
0
    uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1221
0
    uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1222
0
1223
0
    SDValue Hi = DAG.getTargetJumpTable(
1224
0
        JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1225
0
    SDValue Lo = DAG.getTargetJumpTable(
1226
0
        JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1227
0
    Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1228
0
    Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1229
0
    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1230
0
    return Result;
1231
0
  }
1232
0
}
1233
1234
SDValue LanaiTargetLowering::LowerSHL_PARTS(SDValue Op,
1235
1
                                            SelectionDAG &DAG) const {
1236
1
  EVT VT = Op.getValueType();
1237
1
  unsigned VTBits = VT.getSizeInBits();
1238
1
  SDLoc dl(Op);
1239
1
  assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1240
1
  SDValue ShOpLo = Op.getOperand(0);
1241
1
  SDValue ShOpHi = Op.getOperand(1);
1242
1
  SDValue ShAmt = Op.getOperand(2);
1243
1
1244
1
  // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1245
1
  //   LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1246
1
  //   HiBitsForHi = ShOpHi << ShAmt
1247
1
  //   Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1248
1
  //   Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1249
1
  //   return (Hi << 32) | Lo;
1250
1
1251
1
  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1252
1
                                 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1253
1
  SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1254
1
1255
1
  // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1256
1
  // wanted 0, so CSEL it directly.
1257
1
  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1258
1
  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1259
1
  LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1260
1
1261
1
  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1262
1
                                   DAG.getConstant(VTBits, dl, MVT::i32));
1263
1
  SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1264
1
  SDValue HiForNormalShift =
1265
1
      DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1266
1
1267
1
  SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1268
1
1269
1
  SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1270
1
  SDValue Hi =
1271
1
      DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1272
1
1273
1
  // Lanai shifts of larger than register sizes are wrapped rather than
1274
1
  // clamped, so we can't just emit "lo << b" if b is too big.
1275
1
  SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1276
1
  SDValue Lo = DAG.getSelect(
1277
1
      dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1278
1
1279
1
  SDValue Ops[2] = {Lo, Hi};
1280
1
  return DAG.getMergeValues(Ops, dl);
1281
1
}
1282
1283
SDValue LanaiTargetLowering::LowerSRL_PARTS(SDValue Op,
1284
1
                                            SelectionDAG &DAG) const {
1285
1
  MVT VT = Op.getSimpleValueType();
1286
1
  unsigned VTBits = VT.getSizeInBits();
1287
1
  SDLoc dl(Op);
1288
1
  SDValue ShOpLo = Op.getOperand(0);
1289
1
  SDValue ShOpHi = Op.getOperand(1);
1290
1
  SDValue ShAmt = Op.getOperand(2);
1291
1
1292
1
  // Performs the following for a >> b:
1293
1
  //   unsigned r_high = a_high >> b;
1294
1
  //   r_high = (32 - b <= 0) ? 0 : r_high;
1295
1
  //
1296
1
  //   unsigned r_low = a_low >> b;
1297
1
  //   r_low = (32 - b <= 0) ? r_high : r_low;
1298
1
  //   r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1299
1
  //   return (unsigned long long)r_high << 32 | r_low;
1300
1
  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1301
1
  // mask the shift amount.
1302
1
1303
1
  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1304
1
  SDValue NegatedPlus32 = DAG.getNode(
1305
1
      ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1306
1
  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1307
1
1308
1
  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1309
1
  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1310
1
1311
1
  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1312
1
  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1313
1
  SDValue CarryBits =
1314
1
      DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1315
1
  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1316
1
  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1317
1
                     DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1318
1
1319
1
  SDValue Ops[2] = {Lo, Hi};
1320
1
  return DAG.getMergeValues(Ops, dl);
1321
1
}
1322
1323
// Helper function that checks if N is a null or all ones constant.
1324
0
static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1325
0
  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1326
0
}
1327
1328
// Return true if N is conditionally 0 or all ones.
1329
// Detects these expressions where cc is an i1 value:
1330
//
1331
//   (select cc 0, y)   [AllOnes=0]
1332
//   (select cc y, 0)   [AllOnes=0]
1333
//   (zext cc)          [AllOnes=0]
1334
//   (sext cc)          [AllOnes=0/1]
1335
//   (select cc -1, y)  [AllOnes=1]
1336
//   (select cc y, -1)  [AllOnes=1]
1337
//
1338
// * AllOnes determines whether to check for an all zero (AllOnes false) or an
1339
//   all ones operand (AllOnes true).
1340
// * Invert is set when N is the all zero/ones constant when CC is false.
1341
// * OtherOp is set to the alternative value of N.
1342
//
1343
// For example, for (select cc X, Y) and AllOnes = 0 if:
1344
// * X = 0, Invert = False and OtherOp = Y
1345
// * Y = 0, Invert = True and OtherOp = X
1346
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1347
                                       bool &Invert, SDValue &OtherOp,
1348
158
                                       SelectionDAG &DAG) {
1349
158
  switch (N->getOpcode()) {
1350
158
  default:
1351
158
    return false;
1352
158
  case ISD::SELECT: {
1353
0
    CC = N->getOperand(0);
1354
0
    SDValue N1 = N->getOperand(1);
1355
0
    SDValue N2 = N->getOperand(2);
1356
0
    if (isZeroOrAllOnes(N1, AllOnes)) {
1357
0
      Invert = false;
1358
0
      OtherOp = N2;
1359
0
      return true;
1360
0
    }
1361
0
    if (isZeroOrAllOnes(N2, AllOnes)) {
1362
0
      Invert = true;
1363
0
      OtherOp = N1;
1364
0
      return true;
1365
0
    }
1366
0
    return false;
1367
0
  }
1368
0
  case ISD::ZERO_EXTEND: {
1369
0
    // (zext cc) can never be the all ones value.
1370
0
    if (AllOnes)
1371
0
      return false;
1372
0
    CC = N->getOperand(0);
1373
0
    if (CC.getValueType() != MVT::i1)
1374
0
      return false;
1375
0
    SDLoc dl(N);
1376
0
    EVT VT = N->getValueType(0);
1377
0
    OtherOp = DAG.getConstant(1, dl, VT);
1378
0
    Invert = true;
1379
0
    return true;
1380
0
  }
1381
0
  case ISD::SIGN_EXTEND: {
1382
0
    CC = N->getOperand(0);
1383
0
    if (CC.getValueType() != MVT::i1)
1384
0
      return false;
1385
0
    SDLoc dl(N);
1386
0
    EVT VT = N->getValueType(0);
1387
0
    Invert = !AllOnes;
1388
0
    if (AllOnes)
1389
0
      // When looking for an AllOnes constant, N is an sext, and the 'other'
1390
0
      // value is 0.
1391
0
      OtherOp = DAG.getConstant(0, dl, VT);
1392
0
    else
1393
0
      OtherOp =
1394
0
          DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
1395
0
    return true;
1396
0
  }
1397
158
  }
1398
158
}
1399
1400
// Combine a constant select operand into its use:
1401
//
1402
//   (add (select cc, 0, c), x)  -> (select cc, x, (add, x, c))
1403
//   (sub x, (select cc, 0, c))  -> (select cc, x, (sub, x, c))
1404
//   (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))  [AllOnes=1]
1405
//   (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
1406
//   (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))
1407
//
1408
// The transform is rejected if the select doesn't have a constant operand that
1409
// is null, or all ones when AllOnes is set.
1410
//
1411
// Also recognize sext/zext from i1:
1412
//
1413
//   (add (zext cc), x) -> (select cc (add x, 1), x)
1414
//   (add (sext cc), x) -> (select cc (add x, -1), x)
1415
//
1416
// These transformations eventually create predicated instructions.
1417
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1418
                                   TargetLowering::DAGCombinerInfo &DCI,
1419
158
                                   bool AllOnes) {
1420
158
  SelectionDAG &DAG = DCI.DAG;
1421
158
  EVT VT = N->getValueType(0);
1422
158
  SDValue NonConstantVal;
1423
158
  SDValue CCOp;
1424
158
  bool SwapSelectOps;
1425
158
  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1426
158
                                  NonConstantVal, DAG))
1427
158
    return SDValue();
1428
0
1429
0
  // Slct is now know to be the desired identity constant when CC is true.
1430
0
  SDValue TrueVal = OtherOp;
1431
0
  SDValue FalseVal =
1432
0
      DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1433
0
  // Unless SwapSelectOps says CC should be false.
1434
0
  if (SwapSelectOps)
1435
0
    std::swap(TrueVal, FalseVal);
1436
0
1437
0
  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1438
0
}
1439
1440
// Attempt combineSelectAndUse on each operand of a commutative operator N.
1441
static SDValue
1442
combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1443
82
                               bool AllOnes) {
1444
82
  SDValue N0 = N->getOperand(0);
1445
82
  SDValue N1 = N->getOperand(1);
1446
82
  if (N0.getNode()->hasOneUse())
1447
63
    if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1448
0
      return Result;
1449
82
  if (N1.getNode()->hasOneUse())
1450
81
    if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1451
0
      return Result;
1452
82
  return SDValue();
1453
82
}
1454
1455
// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1456
static SDValue PerformSUBCombine(SDNode *N,
1457
26
                                 TargetLowering::DAGCombinerInfo &DCI) {
1458
26
  SDValue N0 = N->getOperand(0);
1459
26
  SDValue N1 = N->getOperand(1);
1460
26
1461
26
  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1462
26
  if (N1.getNode()->hasOneUse())
1463
14
    if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1464
0
      return Result;
1465
26
1466
26
  return SDValue();
1467
26
}
1468
1469
SDValue LanaiTargetLowering::PerformDAGCombine(SDNode *N,
1470
510
                                               DAGCombinerInfo &DCI) const {
1471
510
  switch (N->getOpcode()) {
1472
510
  default:
1473
402
    break;
1474
510
  case ISD::ADD:
1475
71
  case ISD::OR:
1476
71
  case ISD::XOR:
1477
71
    return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1478
71
  case ISD::AND:
1479
11
    return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1480
71
  case ISD::SUB:
1481
26
    return PerformSUBCombine(N, DCI);
1482
402
  }
1483
402
1484
402
  return SDValue();
1485
402
}
1486
1487
void LanaiTargetLowering::computeKnownBitsForTargetNode(
1488
    const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1489
65
    const SelectionDAG &DAG, unsigned Depth) const {
1490
65
  unsigned BitWidth = Known.getBitWidth();
1491
65
  switch (Op.getOpcode()) {
1492
65
  default:
1493
41
    break;
1494
65
  case LanaiISD::SETCC:
1495
18
    Known = KnownBits(BitWidth);
1496
18
    Known.Zero.setBits(1, BitWidth);
1497
18
    break;
1498
65
  case LanaiISD::SELECT_CC:
1499
6
    KnownBits Known2;
1500
6
    Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1501
6
    Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1502
6
    Known.Zero &= Known2.Zero;
1503
6
    Known.One &= Known2.One;
1504
6
    break;
1505
65
  }
1506
65
}