Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
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Source (jump to first uncovered line)
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//===-- LanaiInstrInfo.cpp - Lanai Instruction Information ------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the Lanai implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "LanaiInstrInfo.h"
14
#include "LanaiAluCode.h"
15
#include "LanaiCondCode.h"
16
#include "MCTargetDesc/LanaiBaseInfo.h"
17
#include "llvm/ADT/STLExtras.h"
18
#include "llvm/ADT/SmallVector.h"
19
#include "llvm/CodeGen/MachineFunctionPass.h"
20
#include "llvm/CodeGen/MachineInstrBuilder.h"
21
#include "llvm/CodeGen/MachineRegisterInfo.h"
22
#include "llvm/Support/ErrorHandling.h"
23
#include "llvm/Support/TargetRegistry.h"
24
25
using namespace llvm;
26
27
#define GET_INSTRINFO_CTOR_DTOR
28
#include "LanaiGenInstrInfo.inc"
29
30
LanaiInstrInfo::LanaiInstrInfo()
31
    : LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
32
27
      RegisterInfo() {}
33
34
void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
35
                                 MachineBasicBlock::iterator Position,
36
                                 const DebugLoc &DL,
37
                                 unsigned DestinationRegister,
38
                                 unsigned SourceRegister,
39
8
                                 bool KillSource) const {
40
8
  if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
41
0
    llvm_unreachable("Impossible reg-to-reg copy");
42
0
  }
43
8
44
8
  BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
45
8
      .addReg(SourceRegister, getKillRegState(KillSource))
46
8
      .addImm(0);
47
8
}
48
49
void LanaiInstrInfo::storeRegToStackSlot(
50
    MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
51
    unsigned SourceRegister, bool IsKill, int FrameIndex,
52
    const TargetRegisterClass *RegisterClass,
53
2
    const TargetRegisterInfo * /*RegisterInfo*/) const {
54
2
  DebugLoc DL;
55
2
  if (Position != MBB.end()) {
56
2
    DL = Position->getDebugLoc();
57
2
  }
58
2
59
2
  if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
60
0
    llvm_unreachable("Can't store this register to stack slot");
61
0
  }
62
2
  BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
63
2
      .addReg(SourceRegister, getKillRegState(IsKill))
64
2
      .addFrameIndex(FrameIndex)
65
2
      .addImm(0)
66
2
      .addImm(LPAC::ADD);
67
2
}
68
69
void LanaiInstrInfo::loadRegFromStackSlot(
70
    MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
71
    unsigned DestinationRegister, int FrameIndex,
72
    const TargetRegisterClass *RegisterClass,
73
2
    const TargetRegisterInfo * /*RegisterInfo*/) const {
74
2
  DebugLoc DL;
75
2
  if (Position != MBB.end()) {
76
2
    DL = Position->getDebugLoc();
77
2
  }
78
2
79
2
  if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
80
0
    llvm_unreachable("Can't load this register from stack slot");
81
0
  }
82
2
  BuildMI(MBB, Position, DL, get(Lanai::LDW_RI), DestinationRegister)
83
2
      .addFrameIndex(FrameIndex)
84
2
      .addImm(0)
85
2
      .addImm(LPAC::ADD);
86
2
}
87
88
bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(
89
    const MachineInstr &MIa, const MachineInstr &MIb,
90
5
    AliasAnalysis * /*AA*/) const {
91
5
  assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
92
5
  assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
93
5
94
5
  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
95
5
      MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
96
0
    return false;
97
5
98
5
  // Retrieve the base register, offset from the base register and width. Width
99
5
  // is the size of memory that is being loaded/stored (e.g. 1, 2, 4).  If
100
5
  // base registers are identical, and the offset of a lower memory access +
101
5
  // the width doesn't overlap the offset of a higher memory access,
102
5
  // then the memory accesses are different.
103
5
  const TargetRegisterInfo *TRI = &getRegisterInfo();
104
5
  const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
105
5
  int64_t OffsetA = 0, OffsetB = 0;
106
5
  unsigned int WidthA = 0, WidthB = 0;
107
5
  if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
108
5
      getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
109
5
    if (BaseOpA->isIdenticalTo(*BaseOpB)) {
110
5
      int LowOffset = std::min(OffsetA, OffsetB);
111
5
      int HighOffset = std::max(OffsetA, OffsetB);
112
5
      int LowWidth = (LowOffset == OffsetA) ? WidthA : 
WidthB0
;
113
5
      if (LowOffset + LowWidth <= HighOffset)
114
3
        return true;
115
2
    }
116
5
  }
117
2
  return false;
118
2
}
119
120
26
bool LanaiInstrInfo::expandPostRAPseudo(MachineInstr & /*MI*/) const {
121
26
  return false;
122
26
}
123
124
43
static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) {
125
43
  switch (CC) {
126
43
  case LPCC::ICC_T: //  true
127
0
    return LPCC::ICC_F;
128
43
  case LPCC::ICC_F: //  false
129
0
    return LPCC::ICC_T;
130
43
  case LPCC::ICC_HI: //  high
131
1
    return LPCC::ICC_LS;
132
43
  case LPCC::ICC_LS: //  low or same
133
0
    return LPCC::ICC_HI;
134
43
  case LPCC::ICC_CC: //  carry cleared
135
0
    return LPCC::ICC_CS;
136
43
  case LPCC::ICC_CS: //  carry set
137
0
    return LPCC::ICC_CC;
138
43
  case LPCC::ICC_NE: //  not equal
139
10
    return LPCC::ICC_EQ;
140
43
  case LPCC::ICC_EQ: //  equal
141
12
    return LPCC::ICC_NE;
142
43
  case LPCC::ICC_VC: //  oVerflow cleared
143
0
    return LPCC::ICC_VS;
144
43
  case LPCC::ICC_VS: //  oVerflow set
145
0
    return LPCC::ICC_VC;
146
43
  case LPCC::ICC_PL: //  plus (note: 0 is "minus" too here)
147
1
    return LPCC::ICC_MI;
148
43
  case LPCC::ICC_MI: //  minus
149
0
    return LPCC::ICC_PL;
150
43
  case LPCC::ICC_GE: //  greater than or equal
151
8
    return LPCC::ICC_LT;
152
43
  case LPCC::ICC_LT: //  less than
153
8
    return LPCC::ICC_GE;
154
43
  case LPCC::ICC_GT: //  greater than
155
3
    return LPCC::ICC_LE;
156
43
  case LPCC::ICC_LE: //  less than or equal
157
0
    return LPCC::ICC_GT;
158
43
  default:
159
0
    llvm_unreachable("Invalid condtional code");
160
43
  }
161
43
}
162
163
std::pair<unsigned, unsigned>
164
4
LanaiInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
165
4
  return std::make_pair(TF, 0u);
166
4
}
167
168
ArrayRef<std::pair<unsigned, const char *>>
169
5
LanaiInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
170
5
  using namespace LanaiII;
171
5
  static const std::pair<unsigned, const char *> TargetFlags[] = {
172
5
      {MO_ABS_HI, "lanai-hi"},
173
5
      {MO_ABS_LO, "lanai-lo"},
174
5
      {MO_NO_FLAG, "lanai-nf"}};
175
5
  return makeArrayRef(TargetFlags);
176
5
}
177
178
bool LanaiInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
179
                                    unsigned &SrcReg2, int &CmpMask,
180
93
                                    int &CmpValue) const {
181
93
  switch (MI.getOpcode()) {
182
93
  default:
183
0
    break;
184
93
  case Lanai::SFSUB_F_RI_LO:
185
44
  case Lanai::SFSUB_F_RI_HI:
186
44
    SrcReg = MI.getOperand(0).getReg();
187
44
    SrcReg2 = 0;
188
44
    CmpMask = ~0;
189
44
    CmpValue = MI.getOperand(1).getImm();
190
44
    return true;
191
49
  case Lanai::SFSUB_F_RR:
192
49
    SrcReg = MI.getOperand(0).getReg();
193
49
    SrcReg2 = MI.getOperand(1).getReg();
194
49
    CmpMask = ~0;
195
49
    CmpValue = 0;
196
49
    return true;
197
0
  }
198
0
199
0
  return false;
200
0
}
201
202
// isRedundantFlagInstr - check whether the first instruction, whose only
203
// purpose is to update flags, can be made redundant.
204
// * SFSUB_F_RR can be made redundant by SUB_RI if the operands are the same.
205
// * SFSUB_F_RI can be made redundant by SUB_I if the operands are the same.
206
inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
207
                                        unsigned SrcReg2, int ImmValue,
208
28
                                        MachineInstr *OI) {
209
28
  if (CmpI->getOpcode() == Lanai::SFSUB_F_RR &&
210
28
      
OI->getOpcode() == Lanai::SUB_R10
&&
211
28
      
(4
(4
OI->getOperand(1).getReg() == SrcReg4
&&
212
4
        OI->getOperand(2).getReg() == SrcReg2) ||
213
4
       
(0
OI->getOperand(1).getReg() == SrcReg20
&&
214
0
        OI->getOperand(2).getReg() == SrcReg)))
215
4
    return true;
216
24
217
24
  if (((CmpI->getOpcode() == Lanai::SFSUB_F_RI_LO &&
218
24
        
OI->getOpcode() == Lanai::SUB_I_LO18
) ||
219
24
       
(23
CmpI->getOpcode() == Lanai::SFSUB_F_RI_HI23
&&
220
23
        
OI->getOpcode() == Lanai::SUB_I_HI0
)) &&
221
24
      
OI->getOperand(1).getReg() == SrcReg1
&&
222
24
      
OI->getOperand(2).getImm() == ImmValue1
)
223
1
    return true;
224
23
  return false;
225
23
}
226
227
58
inline static unsigned flagSettingOpcodeVariant(unsigned OldOpcode) {
228
58
  switch (OldOpcode) {
229
58
  case Lanai::ADD_I_HI:
230
0
    return Lanai::ADD_F_I_HI;
231
58
  case Lanai::ADD_I_LO:
232
0
    return Lanai::ADD_F_I_LO;
233
58
  case Lanai::ADD_R:
234
0
    return Lanai::ADD_F_R;
235
58
  case Lanai::ADDC_I_HI:
236
0
    return Lanai::ADDC_F_I_HI;
237
58
  case Lanai::ADDC_I_LO:
238
0
    return Lanai::ADDC_F_I_LO;
239
58
  case Lanai::ADDC_R:
240
0
    return Lanai::ADDC_F_R;
241
58
  case Lanai::AND_I_HI:
242
0
    return Lanai::AND_F_I_HI;
243
58
  case Lanai::AND_I_LO:
244
0
    return Lanai::AND_F_I_LO;
245
58
  case Lanai::AND_R:
246
12
    return Lanai::AND_F_R;
247
58
  case Lanai::OR_I_HI:
248
0
    return Lanai::OR_F_I_HI;
249
58
  case Lanai::OR_I_LO:
250
0
    return Lanai::OR_F_I_LO;
251
58
  case Lanai::OR_R:
252
4
    return Lanai::OR_F_R;
253
58
  case Lanai::SL_I:
254
0
    return Lanai::SL_F_I;
255
58
  case Lanai::SRL_R:
256
0
    return Lanai::SRL_F_R;
257
58
  case Lanai::SA_I:
258
0
    return Lanai::SA_F_I;
259
58
  case Lanai::SRA_R:
260
0
    return Lanai::SRA_F_R;
261
58
  case Lanai::SUB_I_HI:
262
0
    return Lanai::SUB_F_I_HI;
263
58
  case Lanai::SUB_I_LO:
264
13
    return Lanai::SUB_F_I_LO;
265
58
  case Lanai::SUB_R:
266
20
    return Lanai::SUB_F_R;
267
58
  case Lanai::SUBB_I_HI:
268
0
    return Lanai::SUBB_F_I_HI;
269
58
  case Lanai::SUBB_I_LO:
270
0
    return Lanai::SUBB_F_I_LO;
271
58
  case Lanai::SUBB_R:
272
0
    return Lanai::SUBB_F_R;
273
58
  case Lanai::XOR_I_HI:
274
0
    return Lanai::XOR_F_I_HI;
275
58
  case Lanai::XOR_I_LO:
276
0
    return Lanai::XOR_F_I_LO;
277
58
  case Lanai::XOR_R:
278
0
    return Lanai::XOR_F_R;
279
58
  default:
280
9
    return Lanai::NOP;
281
58
  }
282
58
}
283
284
bool LanaiInstrInfo::optimizeCompareInstr(
285
    MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/,
286
93
    int CmpValue, const MachineRegisterInfo *MRI) const {
287
93
  // Get the unique definition of SrcReg.
288
93
  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
289
93
  if (!MI)
290
0
    return false;
291
93
292
93
  // Get ready to iterate backward from CmpInstr.
293
93
  MachineBasicBlock::iterator I = CmpInstr, E = MI,
294
93
                              B = CmpInstr.getParent()->begin();
295
93
296
93
  // Early exit if CmpInstr is at the beginning of the BB.
297
93
  if (I == B)
298
5
    return false;
299
88
300
88
  // There are two possible candidates which can be changed to set SR:
301
88
  // One is MI, the other is a SUB instruction.
302
88
  // * For SFSUB_F_RR(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
303
88
  // * For SFSUB_F_RI(r1, CmpValue), we are looking for SUB(r1, CmpValue).
304
88
  MachineInstr *Sub = nullptr;
305
88
  if (SrcReg2 != 0)
306
48
    // MI is not a candidate to transform into a flag setting instruction.
307
48
    MI = nullptr;
308
40
  else if (MI->getParent() != CmpInstr.getParent() || 
CmpValue != 038
) {
309
9
    // Conservatively refuse to convert an instruction which isn't in the same
310
9
    // BB as the comparison. Don't return if SFSUB_F_RI and CmpValue != 0 as Sub
311
9
    // may still be a candidate.
312
9
    if (CmpInstr.getOpcode() == Lanai::SFSUB_F_RI_LO)
313
9
      MI = nullptr;
314
0
    else
315
0
      return false;
316
88
  }
317
88
318
88
  // Check that SR isn't set between the comparison instruction and the
319
88
  // instruction we want to change while searching for Sub.
320
88
  const TargetRegisterInfo *TRI = &getRegisterInfo();
321
109
  for (--I; I != E; 
--I21
) {
322
53
    const MachineInstr &Instr = *I;
323
53
324
53
    if (Instr.modifiesRegister(Lanai::SR, TRI) ||
325
53
        Instr.readsRegister(Lanai::SR, TRI))
326
25
      // This instruction modifies or uses SR after the one we want to change.
327
25
      // We can't do this transformation.
328
25
      return false;
329
28
330
28
    // Check whether CmpInstr can be made redundant by the current instruction.
331
28
    if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
332
5
      Sub = &*I;
333
5
      break;
334
5
    }
335
23
336
23
    // Don't search outside the containing basic block.
337
23
    if (I == B)
338
2
      return false;
339
23
  }
340
88
341
88
  // Return false if no candidates exist.
342
88
  
if (61
!MI61
&&
!Sub31
)
343
26
    return false;
344
35
345
35
  // The single candidate is called MI.
346
35
  if (!MI)
347
5
    MI = Sub;
348
35
349
35
  if (flagSettingOpcodeVariant(MI->getOpcode()) != Lanai::NOP) {
350
26
    bool isSafe = false;
351
26
352
26
    SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4>
353
26
        OperandsToUpdate;
354
26
    I = CmpInstr;
355
26
    E = CmpInstr.getParent()->end();
356
89
    while (!isSafe && ++I != E) {
357
65
      const MachineInstr &Instr = *I;
358
235
      for (unsigned IO = 0, EO = Instr.getNumOperands(); !isSafe && IO != EO;
359
172
           
++IO170
) {
360
172
        const MachineOperand &MO = Instr.getOperand(IO);
361
172
        if (MO.isRegMask() && 
MO.clobbersPhysReg(Lanai::SR)0
) {
362
0
          isSafe = true;
363
0
          break;
364
0
        }
365
172
        if (!MO.isReg() || 
MO.getReg() != Lanai::SR119
)
366
145
          continue;
367
27
        if (MO.isDef()) {
368
0
          isSafe = true;
369
0
          break;
370
0
        }
371
27
        // Condition code is after the operand before SR.
372
27
        LPCC::CondCode CC;
373
27
        CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
374
27
375
27
        if (Sub) {
376
5
          LPCC::CondCode NewCC = getOppositeCondition(CC);
377
5
          if (NewCC == LPCC::ICC_T)
378
0
            return false;
379
5
          // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on
380
5
          // CMP needs to be updated to be based on SUB.  Push the condition
381
5
          // code operands to OperandsToUpdate.  If it is safe to remove
382
5
          // CmpInstr, the condition code of these operands will be modified.
383
5
          if (SrcReg2 != 0 && 
Sub->getOperand(1).getReg() == SrcReg24
&&
384
5
              
Sub->getOperand(2).getReg() == SrcReg0
) {
385
0
            OperandsToUpdate.push_back(
386
0
                std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
387
0
          }
388
22
        } else {
389
22
          // No Sub, so this is x = <op> y, z; cmp x, 0.
390
22
          switch (CC) {
391
22
          case LPCC::ICC_EQ: // Z
392
20
          case LPCC::ICC_NE: // Z
393
20
          case LPCC::ICC_MI: // N
394
20
          case LPCC::ICC_PL: // N
395
20
          case LPCC::ICC_F:  // none
396
20
          case LPCC::ICC_T:  // none
397
20
            // SR can be used multiple times, we should continue.
398
20
            break;
399
20
          case LPCC::ICC_CS: // C
400
2
          case LPCC::ICC_CC: // C
401
2
          case LPCC::ICC_VS: // V
402
2
          case LPCC::ICC_VC: // V
403
2
          case LPCC::ICC_HI: // C Z
404
2
          case LPCC::ICC_LS: // C Z
405
2
          case LPCC::ICC_GE: // N V
406
2
          case LPCC::ICC_LT: // N V
407
2
          case LPCC::ICC_GT: // Z N V
408
2
          case LPCC::ICC_LE: // Z N V
409
2
            // The instruction uses the V bit or C bit which is not safe.
410
2
            return false;
411
2
          case LPCC::UNKNOWN:
412
0
            return false;
413
22
          }
414
22
        }
415
27
      }
416
65
    }
417
26
418
26
    // If SR is not killed nor re-defined, we should check whether it is
419
26
    // live-out. If it is live-out, do not optimize.
420
26
    
if (24
!isSafe24
) {
421
24
      MachineBasicBlock *MBB = CmpInstr.getParent();
422
24
      for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
423
24
                                            SE = MBB->succ_end();
424
46
           SI != SE; 
++SI22
)
425
23
        if ((*SI)->isLiveIn(Lanai::SR))
426
1
          return false;
427
24
    }
428
24
429
24
    // Toggle the optional operand to SR.
430
24
    MI->setDesc(get(flagSettingOpcodeVariant(MI->getOpcode())));
431
23
    MI->addRegisterDefined(Lanai::SR);
432
23
    CmpInstr.eraseFromParent();
433
23
    return true;
434
9
  }
435
9
436
9
  return false;
437
9
}
438
439
bool LanaiInstrInfo::analyzeSelect(const MachineInstr &MI,
440
                                   SmallVectorImpl<MachineOperand> &Cond,
441
                                   unsigned &TrueOp, unsigned &FalseOp,
442
34
                                   bool &Optimizable) const {
443
34
  assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction");
444
34
  // Select operands:
445
34
  // 0: Def.
446
34
  // 1: True use.
447
34
  // 2: False use.
448
34
  // 3: Condition code.
449
34
  TrueOp = 1;
450
34
  FalseOp = 2;
451
34
  Cond.push_back(MI.getOperand(3));
452
34
  Optimizable = true;
453
34
  return false;
454
34
}
455
456
// Identify instructions that can be folded into a SELECT instruction, and
457
// return the defining instruction.
458
static MachineInstr *canFoldIntoSelect(unsigned Reg,
459
67
                                       const MachineRegisterInfo &MRI) {
460
67
  if (!TargetRegisterInfo::isVirtualRegister(Reg))
461
0
    return nullptr;
462
67
  if (!MRI.hasOneNonDBGUse(Reg))
463
15
    return nullptr;
464
52
  MachineInstr *MI = MRI.getVRegDef(Reg);
465
52
  if (!MI)
466
0
    return nullptr;
467
52
  // MI is folded into the SELECT by predicating it.
468
52
  if (!MI->isPredicable())
469
42
    return nullptr;
470
10
  // Check if MI has any non-dead defs or physreg uses. This also detects
471
10
  // predicated instructions which will be reading SR.
472
40
  
for (unsigned i = 1, e = MI->getNumOperands(); 10
i != e;
++i30
) {
473
34
    const MachineOperand &MO = MI->getOperand(i);
474
34
    // Reject frame index operands.
475
34
    if (MO.isFI() || MO.isCPI() || MO.isJTI())
476
0
      return nullptr;
477
34
    if (!MO.isReg())
478
10
      continue;
479
24
    // MI can't have any tied operands, that would conflict with predication.
480
24
    if (MO.isTied())
481
0
      return nullptr;
482
24
    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
483
4
      return nullptr;
484
20
    if (MO.isDef() && 
!MO.isDead()0
)
485
0
      return nullptr;
486
20
  }
487
10
  bool DontMoveAcrossStores = true;
488
6
  if (!MI->isSafeToMove(/*AliasAnalysis=*/nullptr, DontMoveAcrossStores))
489
3
    return nullptr;
490
3
  return MI;
491
3
}
492
493
MachineInstr *
494
LanaiInstrInfo::optimizeSelect(MachineInstr &MI,
495
                               SmallPtrSetImpl<MachineInstr *> &SeenMIs,
496
34
                               bool /*PreferFalse*/) const {
497
34
  assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction");
498
34
  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
499
34
  MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI);
500
34
  bool Invert = !DefMI;
501
34
  if (!DefMI)
502
33
    DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI);
503
34
  if (!DefMI)
504
31
    return nullptr;
505
3
506
3
  // Find new register class to use.
507
3
  MachineOperand FalseReg = MI.getOperand(Invert ? 
12
:
21
);
508
3
  unsigned DestReg = MI.getOperand(0).getReg();
509
3
  const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
510
3
  if (!MRI.constrainRegClass(DestReg, PreviousClass))
511
0
    return nullptr;
512
3
513
3
  // Create a new predicated version of DefMI.
514
3
  MachineInstrBuilder NewMI =
515
3
      BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
516
3
517
3
  // Copy all the DefMI operands, excluding its (null) predicate.
518
3
  const MCInstrDesc &DefDesc = DefMI->getDesc();
519
3
  for (unsigned i = 1, e = DefDesc.getNumOperands();
520
9
       i != e && !DefDesc.OpInfo[i].isPredicate(); 
++i6
)
521
6
    NewMI.add(DefMI->getOperand(i));
522
3
523
3
  unsigned CondCode = MI.getOperand(3).getImm();
524
3
  if (Invert)
525
2
    NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
526
1
  else
527
1
    NewMI.addImm(CondCode);
528
3
  NewMI.copyImplicitOps(MI);
529
3
530
3
  // The output register value when the predicate is false is an implicit
531
3
  // register operand tied to the first def.  The tie makes the register
532
3
  // allocator ensure the FalseReg is allocated the same register as operand 0.
533
3
  FalseReg.setImplicit();
534
3
  NewMI.add(FalseReg);
535
3
  NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
536
3
537
3
  // Update SeenMIs set: register newly created MI and erase removed DefMI.
538
3
  SeenMIs.insert(NewMI);
539
3
  SeenMIs.erase(DefMI);
540
3
541
3
  // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
542
3
  // DefMI would be invalid when transferred inside the loop.  Checking for a
543
3
  // loop is expensive, but at least remove kill flags if they are in different
544
3
  // BBs.
545
3
  if (DefMI->getParent() != MI.getParent())
546
0
    NewMI->clearKillInfo();
547
3
548
3
  // The caller will erase MI, but not DefMI.
549
3
  DefMI->eraseFromParent();
550
3
  return NewMI;
551
3
}
552
553
// The analyzeBranch function is used to examine conditional instructions and
554
// remove unnecessary instructions. This method is used by BranchFolder and
555
// IfConverter machine function passes to improve the CFG.
556
// - TrueBlock is set to the destination if condition evaluates true (it is the
557
//   nullptr if the destination is the fall-through branch);
558
// - FalseBlock is set to the destination if condition evaluates to false (it
559
//   is the nullptr if the branch is unconditional);
560
// - condition is populated with machine operands needed to generate the branch
561
//   to insert in insertBranch;
562
// Returns: false if branch could successfully be analyzed.
563
bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
564
                                   MachineBasicBlock *&TrueBlock,
565
                                   MachineBasicBlock *&FalseBlock,
566
                                   SmallVectorImpl<MachineOperand> &Condition,
567
873
                                   bool AllowModify) const {
568
873
  // Iterator to current instruction being considered.
569
873
  MachineBasicBlock::iterator Instruction = MBB.end();
570
873
571
873
  // Start from the bottom of the block and work up, examining the
572
873
  // terminator instructions.
573
1.33k
  while (Instruction != MBB.begin()) {
574
1.30k
    --Instruction;
575
1.30k
576
1.30k
    // Skip over debug instructions.
577
1.30k
    if (Instruction->isDebugInstr())
578
0
      continue;
579
1.30k
580
1.30k
    // Working from the bottom, when we see a non-terminator
581
1.30k
    // instruction, we're done.
582
1.30k
    if (!isUnpredicatedTerminator(*Instruction))
583
559
      break;
584
750
585
750
    // A terminator that isn't a branch can't easily be handled
586
750
    // by this analysis.
587
750
    if (!Instruction->isBranch())
588
291
      return true;
589
459
590
459
    // Handle unconditional branches.
591
459
    if (Instruction->getOpcode() == Lanai::BT) {
592
163
      if (!AllowModify) {
593
51
        TrueBlock = Instruction->getOperand(0).getMBB();
594
51
        continue;
595
51
      }
596
112
597
112
      // If the block has any instructions after a branch, delete them.
598
112
      while (std::next(Instruction) != MBB.end()) {
599
0
        std::next(Instruction)->eraseFromParent();
600
0
      }
601
112
602
112
      Condition.clear();
603
112
      FalseBlock = nullptr;
604
112
605
112
      // Delete the jump if it's equivalent to a fall-through.
606
112
      if (MBB.isLayoutSuccessor(Instruction->getOperand(0).getMBB())) {
607
16
        TrueBlock = nullptr;
608
16
        Instruction->eraseFromParent();
609
16
        Instruction = MBB.end();
610
16
        continue;
611
16
      }
612
96
613
96
      // TrueBlock is used to indicate the unconditional destination.
614
96
      TrueBlock = Instruction->getOperand(0).getMBB();
615
96
      continue;
616
96
    }
617
296
618
296
    // Handle conditional branches
619
296
    unsigned Opcode = Instruction->getOpcode();
620
296
    if (Opcode != Lanai::BRCC)
621
0
      return true; // Unknown opcode.
622
296
623
296
    // Multiple conditional branches are not handled here so only proceed if
624
296
    // there are no conditions enqueued.
625
296
    if (Condition.empty()) {
626
296
      LPCC::CondCode BranchCond =
627
296
          static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm());
628
296
629
296
      // TrueBlock is the target of the previously seen unconditional branch.
630
296
      FalseBlock = TrueBlock;
631
296
      TrueBlock = Instruction->getOperand(0).getMBB();
632
296
      Condition.push_back(MachineOperand::CreateImm(BranchCond));
633
296
      continue;
634
296
    }
635
0
636
0
    // Multiple conditional branches are not handled.
637
0
    return true;
638
0
  }
639
873
640
873
  // Return false indicating branch successfully analyzed.
641
873
  
return false582
;
642
873
}
643
644
// reverseBranchCondition - Reverses the branch condition of the specified
645
// condition list, returning false on success and true if it cannot be
646
// reversed.
647
bool LanaiInstrInfo::reverseBranchCondition(
648
36
    SmallVectorImpl<llvm::MachineOperand> &Condition) const {
649
36
  assert((Condition.size() == 1) &&
650
36
         "Lanai branch conditions should have one component.");
651
36
652
36
  LPCC::CondCode BranchCond =
653
36
      static_cast<LPCC::CondCode>(Condition[0].getImm());
654
36
  Condition[0].setImm(getOppositeCondition(BranchCond));
655
36
  return false;
656
36
}
657
658
// Insert the branch with condition specified in condition and given targets
659
// (TrueBlock and FalseBlock). This function returns the number of machine
660
// instructions inserted.
661
unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
662
                                      MachineBasicBlock *TrueBlock,
663
                                      MachineBasicBlock *FalseBlock,
664
                                      ArrayRef<MachineOperand> Condition,
665
                                      const DebugLoc &DL,
666
81
                                      int *BytesAdded) const {
667
81
  // Shouldn't be a fall through.
668
81
  assert(TrueBlock && "insertBranch must not be told to insert a fallthrough");
669
81
  assert(!BytesAdded && "code size not handled");
670
81
671
81
  // If condition is empty then an unconditional branch is being inserted.
672
81
  if (Condition.empty()) {
673
40
    assert(!FalseBlock && "Unconditional branch with multiple successors!");
674
40
    BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
675
40
    return 1;
676
40
  }
677
41
678
41
  // Else a conditional branch is inserted.
679
41
  assert((Condition.size() == 1) &&
680
41
         "Lanai branch conditions should have one component.");
681
41
  unsigned ConditionalCode = Condition[0].getImm();
682
41
  BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
683
41
684
41
  // If no false block, then false behavior is fall through and no branch needs
685
41
  // to be inserted.
686
41
  if (!FalseBlock)
687
40
    return 1;
688
1
689
1
  BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
690
1
  return 2;
691
1
}
692
693
unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
694
64
                                      int *BytesRemoved) const {
695
64
  assert(!BytesRemoved && "code size not handled");
696
64
697
64
  MachineBasicBlock::iterator Instruction = MBB.end();
698
64
  unsigned Count = 0;
699
64
700
146
  while (Instruction != MBB.begin()) {
701
144
    --Instruction;
702
144
    if (Instruction->isDebugInstr())
703
0
      continue;
704
144
    if (Instruction->getOpcode() != Lanai::BT &&
705
144
        
Instruction->getOpcode() != Lanai::BRCC103
) {
706
62
      break;
707
62
    }
708
82
709
82
    // Remove the branch.
710
82
    Instruction->eraseFromParent();
711
82
    Instruction = MBB.end();
712
82
    ++Count;
713
82
  }
714
64
715
64
  return Count;
716
64
}
717
718
unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
719
192
                                             int &FrameIndex) const {
720
192
  if (MI.getOpcode() == Lanai::LDW_RI)
721
144
    if (MI.getOperand(1).isFI() && 
MI.getOperand(2).isImm()34
&&
722
144
        
MI.getOperand(2).getImm() == 034
) {
723
34
      FrameIndex = MI.getOperand(1).getIndex();
724
34
      return MI.getOperand(0).getReg();
725
34
    }
726
158
  return 0;
727
158
}
728
729
unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
730
658
                                                   int &FrameIndex) const {
731
658
  if (MI.getOpcode() == Lanai::LDW_RI) {
732
106
    unsigned Reg;
733
106
    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
734
0
      return Reg;
735
106
    // Check for post-frame index elimination operations
736
106
    SmallVector<const MachineMemOperand *, 1> Accesses;
737
106
    if (hasLoadFromStackSlot(MI, Accesses)){
738
21
      FrameIndex =
739
21
          cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
740
21
              ->getFrameIndex();
741
21
      return 1;
742
21
    }
743
637
  }
744
637
  return 0;
745
637
}
746
747
unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
748
36
                                            int &FrameIndex) const {
749
36
  if (MI.getOpcode() == Lanai::SW_RI)
750
2
    if (MI.getOperand(0).isFI() && 
MI.getOperand(1).isImm()0
&&
751
2
        
MI.getOperand(1).getImm() == 00
) {
752
0
      FrameIndex = MI.getOperand(0).getIndex();
753
0
      return MI.getOperand(2).getReg();
754
0
    }
755
36
  return 0;
756
36
}
757
758
bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
759
    const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
760
10
    unsigned &Width, const TargetRegisterInfo * /*TRI*/) const {
761
10
  // Handle only loads/stores with base register followed by immediate offset
762
10
  // and with add as ALU op.
763
10
  if (LdSt.getNumOperands() != 4)
764
0
    return false;
765
10
  if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
766
10
      !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
767
0
    return false;
768
10
769
10
  switch (LdSt.getOpcode()) {
770
10
  default:
771
0
    return false;
772
10
  case Lanai::LDW_RI:
773
0
  case Lanai::LDW_RR:
774
0
  case Lanai::SW_RR:
775
0
  case Lanai::SW_RI:
776
0
    Width = 4;
777
0
    break;
778
10
  case Lanai::LDHs_RI:
779
10
  case Lanai::LDHz_RI:
780
10
  case Lanai::STH_RI:
781
10
    Width = 2;
782
10
    break;
783
10
  case Lanai::LDBs_RI:
784
0
  case Lanai::LDBz_RI:
785
0
  case Lanai::STB_RI:
786
0
    Width = 1;
787
0
    break;
788
10
  }
789
10
790
10
  BaseOp = &LdSt.getOperand(1);
791
10
  Offset = LdSt.getOperand(2).getImm();
792
10
  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
793
10
                            "operands of type register.");
794
10
  return true;
795
10
}
796
797
bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt,
798
                                        const MachineOperand *&BaseOp,
799
                                        int64_t &Offset,
800
                                        const TargetRegisterInfo *TRI) const {
801
  switch (LdSt.getOpcode()) {
802
  default:
803
    return false;
804
  case Lanai::LDW_RI:
805
  case Lanai::LDW_RR:
806
  case Lanai::SW_RR:
807
  case Lanai::SW_RI:
808
  case Lanai::LDHs_RI:
809
  case Lanai::LDHz_RI:
810
  case Lanai::STH_RI:
811
  case Lanai::LDBs_RI:
812
  case Lanai::LDBz_RI:
813
    unsigned Width;
814
    return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI);
815
  }
816
}