Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
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//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file defines an instruction selector for the MSP430 target.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MSP430.h"
14
#include "MSP430TargetMachine.h"
15
#include "llvm/CodeGen/MachineFrameInfo.h"
16
#include "llvm/CodeGen/MachineFunction.h"
17
#include "llvm/CodeGen/MachineInstrBuilder.h"
18
#include "llvm/CodeGen/MachineRegisterInfo.h"
19
#include "llvm/CodeGen/SelectionDAG.h"
20
#include "llvm/CodeGen/SelectionDAGISel.h"
21
#include "llvm/CodeGen/TargetLowering.h"
22
#include "llvm/Config/llvm-config.h"
23
#include "llvm/IR/CallingConv.h"
24
#include "llvm/IR/Constants.h"
25
#include "llvm/IR/DerivedTypes.h"
26
#include "llvm/IR/Function.h"
27
#include "llvm/IR/Intrinsics.h"
28
#include "llvm/Support/Debug.h"
29
#include "llvm/Support/ErrorHandling.h"
30
#include "llvm/Support/raw_ostream.h"
31
using namespace llvm;
32
33
#define DEBUG_TYPE "msp430-isel"
34
35
namespace {
36
  struct MSP430ISelAddressMode {
37
    enum {
38
      RegBase,
39
      FrameIndexBase
40
    } BaseType;
41
42
    struct {            // This is really a union, discriminated by BaseType!
43
      SDValue Reg;
44
      int FrameIndex;
45
    } Base;
46
47
    int16_t Disp;
48
    const GlobalValue *GV;
49
    const Constant *CP;
50
    const BlockAddress *BlockAddr;
51
    const char *ES;
52
    int JT;
53
    unsigned Align;    // CP alignment.
54
55
    MSP430ISelAddressMode()
56
      : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
57
1.27k
        BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
58
1.27k
    }
59
60
997
    bool hasSymbolicDisplacement() const {
61
997
      return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
62
997
    }
63
64
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
65
    LLVM_DUMP_METHOD void dump() {
66
      errs() << "MSP430ISelAddressMode " << this << '\n';
67
      if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
68
        errs() << "Base.Reg ";
69
        Base.Reg.getNode()->dump();
70
      } else if (BaseType == FrameIndexBase) {
71
        errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
72
      }
73
      errs() << " Disp " << Disp << '\n';
74
      if (GV) {
75
        errs() << "GV ";
76
        GV->dump();
77
      } else if (CP) {
78
        errs() << " CP ";
79
        CP->dump();
80
        errs() << " Align" << Align << '\n';
81
      } else if (ES) {
82
        errs() << "ES ";
83
        errs() << ES << '\n';
84
      } else if (JT != -1)
85
        errs() << " JT" << JT << " Align" << Align << '\n';
86
    }
87
#endif
88
  };
89
}
90
91
/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
92
/// instructions for SelectionDAG operations.
93
///
94
namespace {
95
  class MSP430DAGToDAGISel : public SelectionDAGISel {
96
  public:
97
    MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
98
73
        : SelectionDAGISel(TM, OptLevel) {}
99
100
  private:
101
318
    StringRef getPassName() const override {
102
318
      return "MSP430 DAG->DAG Pattern Instruction Selection";
103
318
    }
104
105
    bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
106
    bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
107
    bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
108
109
    bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
110
                                      std::vector<SDValue> &OutOps) override;
111
112
    // Include the pieces autogenerated from the target description.
113
  #include "MSP430GenDAGISel.inc"
114
115
    // Main method to transform nodes into machine nodes.
116
    void Select(SDNode *N) override;
117
118
    bool tryIndexedLoad(SDNode *Op);
119
    bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
120
                         unsigned Opc16);
121
122
    bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
123
  };
124
}  // end anonymous namespace
125
126
/// createMSP430ISelDag - This pass converts a legalized DAG into a
127
/// MSP430-specific DAG, ready for instruction scheduling.
128
///
129
FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
130
73
                                        CodeGenOpt::Level OptLevel) {
131
73
  return new MSP430DAGToDAGISel(TM, OptLevel);
132
73
}
133
134
135
/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
136
/// These wrap things that will resolve down into a symbol reference.  If no
137
/// match is possible, this returns true, otherwise it returns false.
138
997
bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
139
997
  // If the addressing mode already has a symbol as the displacement, we can
140
997
  // never match another symbol.
141
997
  if (AM.hasSymbolicDisplacement())
142
0
    return true;
143
997
144
997
  SDValue N0 = N.getOperand(0);
145
997
146
997
  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
147
995
    AM.GV = G->getGlobal();
148
995
    AM.Disp += G->getOffset();
149
995
    //AM.SymbolFlags = G->getTargetFlags();
150
995
  } else 
if (ConstantPoolSDNode *2
CP2
= dyn_cast<ConstantPoolSDNode>(N0)) {
151
0
    AM.CP = CP->getConstVal();
152
0
    AM.Align = CP->getAlignment();
153
0
    AM.Disp += CP->getOffset();
154
0
    //AM.SymbolFlags = CP->getTargetFlags();
155
2
  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
156
0
    AM.ES = S->getSymbol();
157
0
    //AM.SymbolFlags = S->getTargetFlags();
158
2
  } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
159
2
    AM.JT = J->getIndex();
160
2
    //AM.SymbolFlags = J->getTargetFlags();
161
2
  } else {
162
0
    AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
163
0
    //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
164
0
  }
165
997
  return false;
166
997
}
167
168
/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
169
/// specified addressing mode without any further recursion.
170
92
bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
171
92
  // Is the base register already occupied?
172
92
  if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
173
0
    // If so, we cannot select it.
174
0
    return true;
175
0
  }
176
92
177
92
  // Default, generate it as a register.
178
92
  AM.BaseType = MSP430ISelAddressMode::RegBase;
179
92
  AM.Base.Reg = N;
180
92
  return false;
181
92
}
182
183
1.50k
bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
184
1.50k
  LLVM_DEBUG(errs() << "MatchAddress: "; AM.dump());
185
1.50k
186
1.50k
  switch (N.getOpcode()) {
187
1.50k
  
default: break92
;
188
1.50k
  case ISD::Constant: {
189
102
    uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
190
102
    AM.Disp += Val;
191
102
    return false;
192
1.50k
  }
193
1.50k
194
1.50k
  case MSP430ISD::Wrapper:
195
997
    if (!MatchWrapper(N, AM))
196
997
      return false;
197
0
    break;
198
0
199
190
  case ISD::FrameIndex:
200
190
    if (AM.BaseType == MSP430ISelAddressMode::RegBase
201
190
        && AM.Base.Reg.getNode() == nullptr) {
202
190
      AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
203
190
      AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
204
190
      return false;
205
190
    }
206
0
    break;
207
0
208
109
  case ISD::ADD: {
209
109
    MSP430ISelAddressMode Backup = AM;
210
109
    if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
211
109
        !MatchAddress(N.getNode()->getOperand(1), AM))
212
109
      return false;
213
0
    AM = Backup;
214
0
    if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
215
0
        !MatchAddress(N.getNode()->getOperand(0), AM))
216
0
      return false;
217
0
    AM = Backup;
218
0
219
0
    break;
220
0
  }
221
0
222
12
  case ISD::OR:
223
12
    // Handle "X | C" as "X + C" iff X is known to have C bits clear.
224
12
    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
225
12
      MSP430ISelAddressMode Backup = AM;
226
12
      uint64_t Offset = CN->getSExtValue();
227
12
      // Start with the LHS as an addr mode.
228
12
      if (!MatchAddress(N.getOperand(0), AM) &&
229
12
          // Address could not have picked a GV address for the displacement.
230
12
          AM.GV == nullptr &&
231
12
          // Check to see if the LHS & C is zero.
232
12
          CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
233
12
        AM.Disp += Offset;
234
12
        return false;
235
12
      }
236
0
      AM = Backup;
237
0
    }
238
12
    
break0
;
239
92
  }
240
92
241
92
  return MatchAddressBase(N, AM);
242
92
}
243
244
/// SelectAddr - returns true if it is able pattern match an addressing mode.
245
/// It returns the operands which make up the maximal addressing mode it can
246
/// match by reference.
247
bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
248
1.27k
                                    SDValue &Base, SDValue &Disp) {
249
1.27k
  MSP430ISelAddressMode AM;
250
1.27k
251
1.27k
  if (MatchAddress(N, AM))
252
0
    return false;
253
1.27k
254
1.27k
  if (AM.BaseType == MSP430ISelAddressMode::RegBase)
255
1.08k
    if (!AM.Base.Reg.getNode())
256
990
      AM.Base.Reg = CurDAG->getRegister(MSP430::SR, MVT::i16);
257
1.27k
258
1.27k
  Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
259
1.27k
             ? CurDAG->getTargetFrameIndex(
260
190
                   AM.Base.FrameIndex,
261
190
                   getTargetLowering()->getPointerTy(CurDAG->getDataLayout()))
262
1.27k
             : 
AM.Base.Reg1.08k
;
263
1.27k
264
1.27k
  if (AM.GV)
265
995
    Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
266
995
                                          MVT::i16, AM.Disp,
267
995
                                          0/*AM.SymbolFlags*/);
268
277
  else if (AM.CP)
269
0
    Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
270
0
                                         AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
271
277
  else if (AM.ES)
272
0
    Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
273
277
  else if (AM.JT != -1)
274
2
    Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
275
275
  else if (AM.BlockAddr)
276
0
    Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
277
0
                                         0/*AM.SymbolFlags*/);
278
275
  else
279
275
    Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16);
280
1.27k
281
1.27k
  return true;
282
1.27k
}
283
284
bool MSP430DAGToDAGISel::
285
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
286
11
                             std::vector<SDValue> &OutOps) {
287
11
  SDValue Op0, Op1;
288
11
  switch (ConstraintID) {
289
11
  
default: return true0
;
290
11
  case InlineAsm::Constraint_m: // memory
291
11
    if (!SelectAddr(Op, Op0, Op1))
292
0
      return true;
293
11
    break;
294
11
  }
295
11
296
11
  OutOps.push_back(Op0);
297
11
  OutOps.push_back(Op1);
298
11
  return false;
299
11
}
300
301
331
static bool isValidIndexedLoad(const LoadSDNode *LD) {
302
331
  ISD::MemIndexedMode AM = LD->getAddressingMode();
303
331
  if (AM != ISD::POST_INC || 
LD->getExtensionType() != ISD::NON_EXTLOAD5
)
304
326
    return false;
305
5
306
5
  EVT VT = LD->getMemoryVT();
307
5
308
5
  switch (VT.getSimpleVT().SimpleTy) {
309
5
  case MVT::i8:
310
0
    // Sanity check
311
0
    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
312
0
      return false;
313
0
314
0
    break;
315
5
  case MVT::i16:
316
5
    // Sanity check
317
5
    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
318
0
      return false;
319
5
320
5
    break;
321
5
  default:
322
0
    return false;
323
5
  }
324
5
325
5
  return true;
326
5
}
327
328
311
bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) {
329
311
  LoadSDNode *LD = cast<LoadSDNode>(N);
330
311
  if (!isValidIndexedLoad(LD))
331
311
    return false;
332
0
333
0
  MVT VT = LD->getMemoryVT().getSimpleVT();
334
0
335
0
  unsigned Opcode = 0;
336
0
  switch (VT.SimpleTy) {
337
0
  case MVT::i8:
338
0
    Opcode = MSP430::MOV8rp;
339
0
    break;
340
0
  case MVT::i16:
341
0
    Opcode = MSP430::MOV16rp;
342
0
    break;
343
0
  default:
344
0
    return false;
345
0
  }
346
0
347
0
  ReplaceNode(N,
348
0
              CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other,
349
0
                                     LD->getBasePtr(), LD->getChain()));
350
0
  return true;
351
0
}
352
353
bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
354
242
                                         unsigned Opc8, unsigned Opc16) {
355
242
  if (N1.getOpcode() == ISD::LOAD &&
356
242
      
N1.hasOneUse()38
&&
357
242
      
IsLegalToFold(N1, Op, Op, OptLevel)23
) {
358
20
    LoadSDNode *LD = cast<LoadSDNode>(N1);
359
20
    if (!isValidIndexedLoad(LD))
360
15
      return false;
361
5
362
5
    MVT VT = LD->getMemoryVT().getSimpleVT();
363
5
    unsigned Opc = (VT == MVT::i16 ? Opc16 : 
Opc80
);
364
5
    MachineMemOperand *MemRef = cast<MemSDNode>(N1)->getMemOperand();
365
5
    SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
366
5
    SDNode *ResNode =
367
5
      CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
368
5
    CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {MemRef});
369
5
    // Transfer chain.
370
5
    ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
371
5
    // Transfer writeback.
372
5
    ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
373
5
    return true;
374
5
  }
375
222
376
222
  return false;
377
222
}
378
379
380
6.15k
void MSP430DAGToDAGISel::Select(SDNode *Node) {
381
6.15k
  SDLoc dl(Node);
382
6.15k
383
6.15k
  // If we have a custom node, we already have selected!
384
6.15k
  if (Node->isMachineOpcode()) {
385
0
    LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
386
0
    Node->setNodeId(-1);
387
0
    return;
388
0
  }
389
6.15k
390
6.15k
  // Few custom selection stuff.
391
6.15k
  switch (Node->getOpcode()) {
392
6.15k
  
default: break5.71k
;
393
6.15k
  case ISD::FrameIndex: {
394
3
    assert(Node->getValueType(0) == MVT::i16);
395
3
    int FI = cast<FrameIndexSDNode>(Node)->getIndex();
396
3
    SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
397
3
    if (Node->hasOneUse()) {
398
3
      CurDAG->SelectNodeTo(Node, MSP430::ADDframe, MVT::i16, TFI,
399
3
                           CurDAG->getTargetConstant(0, dl, MVT::i16));
400
3
      return;
401
3
    }
402
0
    ReplaceNode(Node, CurDAG->getMachineNode(
403
0
                          MSP430::ADDframe, dl, MVT::i16, TFI,
404
0
                          CurDAG->getTargetConstant(0, dl, MVT::i16)));
405
0
    return;
406
0
  }
407
311
  case ISD::LOAD:
408
311
    if (tryIndexedLoad(Node))
409
0
      return;
410
311
    // Other cases are autogenerated.
411
311
    break;
412
311
  case ISD::ADD:
413
26
    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
414
26
                        MSP430::ADD8rp, MSP430::ADD16rp))
415
1
      return;
416
25
    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
417
25
                             MSP430::ADD8rp, MSP430::ADD16rp))
418
0
      return;
419
25
420
25
    // Other cases are autogenerated.
421
25
    break;
422
25
  case ISD::SUB:
423
2
    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
424
2
                        MSP430::SUB8rp, MSP430::SUB16rp))
425
1
      return;
426
1
427
1
    // Other cases are autogenerated.
428
1
    break;
429
62
  case ISD::AND:
430
62
    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
431
62
                        MSP430::AND8rp, MSP430::AND16rp))
432
1
      return;
433
61
    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
434
61
                             MSP430::AND8rp, MSP430::AND16rp))
435
0
      return;
436
61
437
61
    // Other cases are autogenerated.
438
61
    break;
439
61
  case ISD::OR:
440
22
    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
441
22
                        MSP430::BIS8rp, MSP430::BIS16rp))
442
1
      return;
443
21
    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
444
21
                             MSP430::BIS8rp, MSP430::BIS16rp))
445
0
      return;
446
21
447
21
    // Other cases are autogenerated.
448
21
    break;
449
21
  case ISD::XOR:
450
12
    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
451
12
                        MSP430::XOR8rp, MSP430::XOR16rp))
452
1
      return;
453
11
    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
454
11
                             MSP430::XOR8rp, MSP430::XOR16rp))
455
0
      return;
456
11
457
11
    // Other cases are autogenerated.
458
11
    break;
459
6.14k
  }
460
6.14k
461
6.14k
  // Select the default instruction
462
6.14k
  SelectCode(Node);
463
6.14k
}