Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
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//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MSP430TargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430ISelLowering.h"
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#include "MSP430.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430Subtarget.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "msp430-lower"
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MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
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                                           const MSP430Subtarget &STI)
42
77
    : TargetLowering(TM) {
43
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  // Set up the register classes.
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77
  addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
46
77
  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
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48
77
  // Compute derived properties from the register classes
49
77
  computeRegisterProperties(STI.getRegisterInfo());
50
77
51
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  // Provide all sorts of operation actions
52
77
  setStackPointerRegisterToSaveRestore(MSP430::SP);
53
77
  setBooleanContents(ZeroOrOneBooleanContent);
54
77
  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
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77
56
77
  // We have post-incremented loads / stores.
57
77
  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
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77
  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
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462
  for (MVT VT : MVT::integer_valuetypes()) {
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462
    setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
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462
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
63
462
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
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462
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8,  Expand);
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462
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
66
462
  }
67
77
68
77
  // We don't have any truncstores
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  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
70
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71
77
  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
72
77
  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
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77
  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
74
77
  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
75
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  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
76
77
  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
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77
  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
78
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  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
79
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  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
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  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
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  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
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  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
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  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
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  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
85
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  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
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  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
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  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
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  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
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  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
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  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
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  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
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  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
93
77
  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
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  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
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  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
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  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
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  setOperationAction(ISD::STACKSAVE,        MVT::Other, Expand);
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  setOperationAction(ISD::STACKRESTORE,     MVT::Other, Expand);
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  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
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  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
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  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
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  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
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  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
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  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
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  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
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  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
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  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
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  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
111
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  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
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  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
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  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
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  // FIXME: Implement efficiently multiplication by a constant
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  setOperationAction(ISD::MUL,              MVT::i8,    Promote);
118
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  setOperationAction(ISD::MULHS,            MVT::i8,    Promote);
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  setOperationAction(ISD::MULHU,            MVT::i8,    Promote);
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  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Promote);
121
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  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Promote);
122
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  setOperationAction(ISD::MUL,              MVT::i16,   LibCall);
123
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  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
124
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  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
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  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
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  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
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77
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  setOperationAction(ISD::UDIV,             MVT::i8,    Promote);
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  setOperationAction(ISD::UDIVREM,          MVT::i8,    Promote);
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  setOperationAction(ISD::UREM,             MVT::i8,    Promote);
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  setOperationAction(ISD::SDIV,             MVT::i8,    Promote);
132
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  setOperationAction(ISD::SDIVREM,          MVT::i8,    Promote);
133
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  setOperationAction(ISD::SREM,             MVT::i8,    Promote);
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  setOperationAction(ISD::UDIV,             MVT::i16,   LibCall);
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  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
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  setOperationAction(ISD::UREM,             MVT::i16,   LibCall);
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  setOperationAction(ISD::SDIV,             MVT::i16,   LibCall);
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  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
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  setOperationAction(ISD::SREM,             MVT::i16,   LibCall);
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  // varargs support
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  setOperationAction(ISD::VASTART,          MVT::Other, Custom);
143
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  setOperationAction(ISD::VAARG,            MVT::Other, Expand);
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  setOperationAction(ISD::VAEND,            MVT::Other, Expand);
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  setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
146
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  setOperationAction(ISD::JumpTable,        MVT::i16,   Custom);
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148
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  // EABI Libcalls - EABI Section 6.2
149
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  const struct {
150
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    const RTLIB::Libcall Op;
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    const char * const Name;
152
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    const ISD::CondCode Cond;
153
77
  } LibraryCalls[] = {
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    // Floating point conversions - EABI Table 6
155
77
    { RTLIB::FPROUND_F64_F32,   "__mspabi_cvtdf",   ISD::SETCC_INVALID },
156
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    { RTLIB::FPEXT_F32_F64,     "__mspabi_cvtfd",   ISD::SETCC_INVALID },
157
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    // The following is NOT implemented in libgcc
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    //{ RTLIB::FPTOSINT_F64_I16,  "__mspabi_fixdi", ISD::SETCC_INVALID },
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    { RTLIB::FPTOSINT_F64_I32,  "__mspabi_fixdli",  ISD::SETCC_INVALID },
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    { RTLIB::FPTOSINT_F64_I64,  "__mspabi_fixdlli", ISD::SETCC_INVALID },
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    // The following is NOT implemented in libgcc
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    //{ RTLIB::FPTOUINT_F64_I16,  "__mspabi_fixdu", ISD::SETCC_INVALID },
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    { RTLIB::FPTOUINT_F64_I32,  "__mspabi_fixdul",  ISD::SETCC_INVALID },
164
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    { RTLIB::FPTOUINT_F64_I64,  "__mspabi_fixdull", ISD::SETCC_INVALID },
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    // The following is NOT implemented in libgcc
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    //{ RTLIB::FPTOSINT_F32_I16,  "__mspabi_fixfi", ISD::SETCC_INVALID },
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    { RTLIB::FPTOSINT_F32_I32,  "__mspabi_fixfli",  ISD::SETCC_INVALID },
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    { RTLIB::FPTOSINT_F32_I64,  "__mspabi_fixflli", ISD::SETCC_INVALID },
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    // The following is NOT implemented in libgcc
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    //{ RTLIB::FPTOUINT_F32_I16,  "__mspabi_fixfu", ISD::SETCC_INVALID },
171
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    { RTLIB::FPTOUINT_F32_I32,  "__mspabi_fixful",  ISD::SETCC_INVALID },
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    { RTLIB::FPTOUINT_F32_I64,  "__mspabi_fixfull", ISD::SETCC_INVALID },
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    // TODO The following IS implemented in libgcc
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    //{ RTLIB::SINTTOFP_I16_F64,  "__mspabi_fltid", ISD::SETCC_INVALID },
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    { RTLIB::SINTTOFP_I32_F64,  "__mspabi_fltlid",  ISD::SETCC_INVALID },
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    // TODO The following IS implemented in libgcc but is not in the EABI
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    { RTLIB::SINTTOFP_I64_F64,  "__mspabi_fltllid", ISD::SETCC_INVALID },
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    // TODO The following IS implemented in libgcc
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    //{ RTLIB::UINTTOFP_I16_F64,  "__mspabi_fltud", ISD::SETCC_INVALID },
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    { RTLIB::UINTTOFP_I32_F64,  "__mspabi_fltuld",  ISD::SETCC_INVALID },
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    // The following IS implemented in libgcc but is not in the EABI
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    { RTLIB::UINTTOFP_I64_F64,  "__mspabi_fltulld", ISD::SETCC_INVALID },
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    // TODO The following IS implemented in libgcc
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    //{ RTLIB::SINTTOFP_I16_F32,  "__mspabi_fltif", ISD::SETCC_INVALID },
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    { RTLIB::SINTTOFP_I32_F32,  "__mspabi_fltlif",  ISD::SETCC_INVALID },
186
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    // TODO The following IS implemented in libgcc but is not in the EABI
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    { RTLIB::SINTTOFP_I64_F32,  "__mspabi_fltllif", ISD::SETCC_INVALID },
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    // TODO The following IS implemented in libgcc
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    //{ RTLIB::UINTTOFP_I16_F32,  "__mspabi_fltuf", ISD::SETCC_INVALID },
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    { RTLIB::UINTTOFP_I32_F32,  "__mspabi_fltulf",  ISD::SETCC_INVALID },
191
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    // The following IS implemented in libgcc but is not in the EABI
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    { RTLIB::UINTTOFP_I64_F32,  "__mspabi_fltullf", ISD::SETCC_INVALID },
193
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194
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    // Floating point comparisons - EABI Table 7
195
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    { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
196
77
    { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
197
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    { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
198
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    { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
199
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    { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
200
77
    { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
201
77
    { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
202
77
    { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
203
77
    { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
204
77
    { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
205
77
    { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
206
77
    { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
207
77
208
77
    // Floating point arithmetic - EABI Table 8
209
77
    { RTLIB::ADD_F64,  "__mspabi_addd", ISD::SETCC_INVALID },
210
77
    { RTLIB::ADD_F32,  "__mspabi_addf", ISD::SETCC_INVALID },
211
77
    { RTLIB::DIV_F64,  "__mspabi_divd", ISD::SETCC_INVALID },
212
77
    { RTLIB::DIV_F32,  "__mspabi_divf", ISD::SETCC_INVALID },
213
77
    { RTLIB::MUL_F64,  "__mspabi_mpyd", ISD::SETCC_INVALID },
214
77
    { RTLIB::MUL_F32,  "__mspabi_mpyf", ISD::SETCC_INVALID },
215
77
    { RTLIB::SUB_F64,  "__mspabi_subd", ISD::SETCC_INVALID },
216
77
    { RTLIB::SUB_F32,  "__mspabi_subf", ISD::SETCC_INVALID },
217
77
    // The following are NOT implemented in libgcc
218
77
    // { RTLIB::NEG_F64,  "__mspabi_negd", ISD::SETCC_INVALID },
219
77
    // { RTLIB::NEG_F32,  "__mspabi_negf", ISD::SETCC_INVALID },
220
77
221
77
    // Universal Integer Operations - EABI Table 9
222
77
    { RTLIB::SDIV_I16,   "__mspabi_divi", ISD::SETCC_INVALID },
223
77
    { RTLIB::SDIV_I32,   "__mspabi_divli", ISD::SETCC_INVALID },
224
77
    { RTLIB::SDIV_I64,   "__mspabi_divlli", ISD::SETCC_INVALID },
225
77
    { RTLIB::UDIV_I16,   "__mspabi_divu", ISD::SETCC_INVALID },
226
77
    { RTLIB::UDIV_I32,   "__mspabi_divul", ISD::SETCC_INVALID },
227
77
    { RTLIB::UDIV_I64,   "__mspabi_divull", ISD::SETCC_INVALID },
228
77
    { RTLIB::SREM_I16,   "__mspabi_remi", ISD::SETCC_INVALID },
229
77
    { RTLIB::SREM_I32,   "__mspabi_remli", ISD::SETCC_INVALID },
230
77
    { RTLIB::SREM_I64,   "__mspabi_remlli", ISD::SETCC_INVALID },
231
77
    { RTLIB::UREM_I16,   "__mspabi_remu", ISD::SETCC_INVALID },
232
77
    { RTLIB::UREM_I32,   "__mspabi_remul", ISD::SETCC_INVALID },
233
77
    { RTLIB::UREM_I64,   "__mspabi_remull", ISD::SETCC_INVALID },
234
77
235
77
    // Bitwise Operations - EABI Table 10
236
77
    // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
237
77
    { RTLIB::SRL_I32,    "__mspabi_srll", ISD::SETCC_INVALID },
238
77
    { RTLIB::SRA_I32,    "__mspabi_sral", ISD::SETCC_INVALID },
239
77
    { RTLIB::SHL_I32,    "__mspabi_slll", ISD::SETCC_INVALID },
240
77
    // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
241
77
242
77
  };
243
77
244
4.08k
  for (const auto &LC : LibraryCalls) {
245
4.08k
    setLibcallName(LC.Op, LC.Name);
246
4.08k
    if (LC.Cond != ISD::SETCC_INVALID)
247
924
      setCmpLibcallCC(LC.Op, LC.Cond);
248
4.08k
  }
249
77
250
77
  if (STI.hasHWMult16()) {
251
2
    const struct {
252
2
      const RTLIB::Libcall Op;
253
2
      const char * const Name;
254
2
    } LibraryCalls[] = {
255
2
      // Integer Multiply - EABI Table 9
256
2
      { RTLIB::MUL_I16,   "__mspabi_mpyi_hw" },
257
2
      { RTLIB::MUL_I32,   "__mspabi_mpyl_hw" },
258
2
      { RTLIB::MUL_I64,   "__mspabi_mpyll_hw" },
259
2
      // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
260
2
      // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
261
2
    };
262
6
    for (const auto &LC : LibraryCalls) {
263
6
      setLibcallName(LC.Op, LC.Name);
264
6
    }
265
75
  } else if (STI.hasHWMult32()) {
266
2
    const struct {
267
2
      const RTLIB::Libcall Op;
268
2
      const char * const Name;
269
2
    } LibraryCalls[] = {
270
2
      // Integer Multiply - EABI Table 9
271
2
      { RTLIB::MUL_I16,   "__mspabi_mpyi_hw" },
272
2
      { RTLIB::MUL_I32,   "__mspabi_mpyl_hw32" },
273
2
      { RTLIB::MUL_I64,   "__mspabi_mpyll_hw32" },
274
2
      // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
275
2
      // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
276
2
    };
277
6
    for (const auto &LC : LibraryCalls) {
278
6
      setLibcallName(LC.Op, LC.Name);
279
6
    }
280
73
  } else if (STI.hasHWMultF5()) {
281
2
    const struct {
282
2
      const RTLIB::Libcall Op;
283
2
      const char * const Name;
284
2
    } LibraryCalls[] = {
285
2
      // Integer Multiply - EABI Table 9
286
2
      { RTLIB::MUL_I16,   "__mspabi_mpyi_f5hw" },
287
2
      { RTLIB::MUL_I32,   "__mspabi_mpyl_f5hw" },
288
2
      { RTLIB::MUL_I64,   "__mspabi_mpyll_f5hw" },
289
2
      // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
290
2
      // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
291
2
    };
292
6
    for (const auto &LC : LibraryCalls) {
293
6
      setLibcallName(LC.Op, LC.Name);
294
6
    }
295
71
  } else { // NoHWMult
296
71
    const struct {
297
71
      const RTLIB::Libcall Op;
298
71
      const char * const Name;
299
71
    } LibraryCalls[] = {
300
71
      // Integer Multiply - EABI Table 9
301
71
      { RTLIB::MUL_I16,   "__mspabi_mpyi" },
302
71
      { RTLIB::MUL_I32,   "__mspabi_mpyl" },
303
71
      { RTLIB::MUL_I64,   "__mspabi_mpyll" },
304
71
      // The __mspabi_mpysl* functions are NOT implemented in libgcc
305
71
      // The __mspabi_mpyul* functions are NOT implemented in libgcc
306
71
    };
307
213
    for (const auto &LC : LibraryCalls) {
308
213
      setLibcallName(LC.Op, LC.Name);
309
213
    }
310
71
    setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::MSP430_BUILTIN);
311
71
  }
312
77
313
77
  // Several of the runtime library functions use a special calling conv
314
77
  setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::MSP430_BUILTIN);
315
77
  setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::MSP430_BUILTIN);
316
77
  setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::MSP430_BUILTIN);
317
77
  setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::MSP430_BUILTIN);
318
77
  setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::MSP430_BUILTIN);
319
77
  setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::MSP430_BUILTIN);
320
77
  setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::MSP430_BUILTIN);
321
77
  setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::MSP430_BUILTIN);
322
77
  setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::MSP430_BUILTIN);
323
77
  setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::MSP430_BUILTIN);
324
77
  setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::MSP430_BUILTIN);
325
77
  setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::MSP430_BUILTIN);
326
77
  setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::MSP430_BUILTIN);
327
77
  setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN);
328
77
  // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
329
77
330
77
  setMinFunctionAlignment(1);
331
77
  setPrefFunctionAlignment(1);
332
77
}
333
334
SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
335
511
                                             SelectionDAG &DAG) const {
336
511
  switch (Op.getOpcode()) {
337
511
  case ISD::SHL: // FALLTHROUGH
338
38
  case ISD::SRL:
339
38
  case ISD::SRA:              return LowerShifts(Op, DAG);
340
367
  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
341
38
  
case ISD::BlockAddress: return LowerBlockAddress(Op, DAG)1
;
342
38
  
case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG)0
;
343
57
  case ISD::SETCC:            return LowerSETCC(Op, DAG);
344
38
  
case ISD::BR_CC: return LowerBR_CC(Op, DAG)30
;
345
38
  
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG)12
;
346
38
  
case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG)2
;
347
38
  
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG)0
;
348
38
  
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG)1
;
349
38
  
case ISD::VASTART: return LowerVASTART(Op, DAG)1
;
350
38
  
case ISD::JumpTable: return LowerJumpTable(Op, DAG)2
;
351
38
  default:
352
0
    llvm_unreachable("unimplemented operand");
353
511
  }
354
511
}
355
356
//===----------------------------------------------------------------------===//
357
//                       MSP430 Inline Assembly Support
358
//===----------------------------------------------------------------------===//
359
360
/// getConstraintType - Given a constraint letter, return the type of
361
/// constraint it is for this target.
362
TargetLowering::ConstraintType
363
372
MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
364
372
  if (Constraint.size() == 1) {
365
368
    switch (Constraint[0]) {
366
368
    case 'r':
367
213
      return C_RegisterClass;
368
368
    default:
369
155
      break;
370
159
    }
371
159
  }
372
159
  return TargetLowering::getConstraintType(Constraint);
373
159
}
374
375
std::pair<unsigned, const TargetRegisterClass *>
376
MSP430TargetLowering::getRegForInlineAsmConstraint(
377
66
    const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
378
66
  if (Constraint.size() == 1) {
379
64
    // GCC Constraint Letters
380
64
    switch (Constraint[0]) {
381
64
    
default: break12
;
382
64
    case 'r':   // GENERAL_REGS
383
52
      if (VT == MVT::i8)
384
1
        return std::make_pair(0U, &MSP430::GR8RegClass);
385
51
386
51
      return std::make_pair(0U, &MSP430::GR16RegClass);
387
64
    }
388
64
  }
389
14
390
14
  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
391
14
}
392
393
//===----------------------------------------------------------------------===//
394
//                      Calling Convention Implementation
395
//===----------------------------------------------------------------------===//
396
397
#include "MSP430GenCallingConv.inc"
398
399
/// For each argument in a function store the number of pieces it is composed
400
/// of.
401
template<typename ArgT>
402
static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
403
415
                              SmallVectorImpl<unsigned> &Out) {
404
415
  unsigned CurrentArgIndex;
405
415
406
415
  if (Args.empty())
407
175
    return;
408
240
409
240
  CurrentArgIndex = Args[0].OrigArgIndex;
410
240
  Out.push_back(0);
411
240
412
673
  for (auto &Arg : Args) {
413
673
    if (CurrentArgIndex == Arg.OrigArgIndex) {
414
519
      Out.back() += 1;
415
519
    } else {
416
154
      Out.push_back(1);
417
154
      CurrentArgIndex = Arg.OrigArgIndex;
418
154
    }
419
673
  }
420
240
}
MSP430ISelLowering.cpp:void ParseFunctionArgs<llvm::ISD::InputArg>(llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SmallVectorImpl<unsigned int>&)
Line
Count
Source
403
314
                              SmallVectorImpl<unsigned> &Out) {
404
314
  unsigned CurrentArgIndex;
405
314
406
314
  if (Args.empty())
407
170
    return;
408
144
409
144
  CurrentArgIndex = Args[0].OrigArgIndex;
410
144
  Out.push_back(0);
411
144
412
255
  for (auto &Arg : Args) {
413
255
    if (CurrentArgIndex == Arg.OrigArgIndex) {
414
177
      Out.back() += 1;
415
177
    } else {
416
78
      Out.push_back(1);
417
78
      CurrentArgIndex = Arg.OrigArgIndex;
418
78
    }
419
255
  }
420
144
}
MSP430ISelLowering.cpp:void ParseFunctionArgs<llvm::ISD::OutputArg>(llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, llvm::SmallVectorImpl<unsigned int>&)
Line
Count
Source
403
101
                              SmallVectorImpl<unsigned> &Out) {
404
101
  unsigned CurrentArgIndex;
405
101
406
101
  if (Args.empty())
407
5
    return;
408
96
409
96
  CurrentArgIndex = Args[0].OrigArgIndex;
410
96
  Out.push_back(0);
411
96
412
418
  for (auto &Arg : Args) {
413
418
    if (CurrentArgIndex == Arg.OrigArgIndex) {
414
342
      Out.back() += 1;
415
342
    } else {
416
76
      Out.push_back(1);
417
76
      CurrentArgIndex = Arg.OrigArgIndex;
418
76
    }
419
418
  }
420
96
}
421
422
static void AnalyzeVarArgs(CCState &State,
423
0
                           const SmallVectorImpl<ISD::OutputArg> &Outs) {
424
0
  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
425
0
}
426
427
static void AnalyzeVarArgs(CCState &State,
428
1
                           const SmallVectorImpl<ISD::InputArg> &Ins) {
429
1
  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
430
1
}
431
432
/// Analyze incoming and outgoing function arguments. We need custom C++ code
433
/// to handle special constraints in the ABI like reversing the order of the
434
/// pieces of splitted arguments. In addition, all pieces of a certain argument
435
/// have to be passed either using registers or the stack but never mixing both.
436
template<typename ArgT>
437
static void AnalyzeArguments(CCState &State,
438
                             SmallVectorImpl<CCValAssign> &ArgLocs,
439
416
                             const SmallVectorImpl<ArgT> &Args) {
440
416
  static const MCPhysReg CRegList[] = {
441
416
    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
442
416
  };
443
416
  static const unsigned CNbRegs = array_lengthof(CRegList);
444
416
  static const MCPhysReg BuiltinRegList[] = {
445
416
    MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
446
416
    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
447
416
  };
448
416
  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
449
416
450
416
  ArrayRef<MCPhysReg> RegList;
451
416
  unsigned NbRegs;
452
416
453
416
  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
454
416
  if (Builtin) {
455
17
    RegList = BuiltinRegList;
456
17
    NbRegs = BuiltinNbRegs;
457
399
  } else {
458
399
    RegList = CRegList;
459
399
    NbRegs = CNbRegs;
460
399
  }
461
416
462
416
  if (State.isVarArg()) {
463
1
    AnalyzeVarArgs(State, Args);
464
1
    return;
465
1
  }
466
415
467
415
  SmallVector<unsigned, 4> ArgsParts;
468
415
  ParseFunctionArgs(Args, ArgsParts);
469
415
470
415
  if (Builtin) {
471
17
    assert(ArgsParts.size() == 2 &&
472
17
        "Builtin calling convention requires two arguments");
473
17
  }
474
415
475
415
  unsigned RegsLeft = NbRegs;
476
415
  bool UsedStack = false;
477
415
  unsigned ValNo = 0;
478
415
479
809
  for (unsigned i = 0, e = ArgsParts.size(); i != e; 
i++394
) {
480
394
    MVT ArgVT = Args[ValNo].VT;
481
394
    ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
482
394
    MVT LocVT = ArgVT;
483
394
    CCValAssign::LocInfo LocInfo = CCValAssign::Full;
484
394
485
394
    // Promote i8 to i16
486
394
    if (LocVT == MVT::i8) {
487
58
      LocVT = MVT::i16;
488
58
      if (ArgFlags.isSExt())
489
5
          LocInfo = CCValAssign::SExt;
490
53
      else if (ArgFlags.isZExt())
491
10
          LocInfo = CCValAssign::ZExt;
492
43
      else
493
43
          LocInfo = CCValAssign::AExt;
494
58
    }
495
394
496
394
    // Handle byval arguments
497
394
    if (ArgFlags.isByVal()) {
498
3
      State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
499
3
      continue;
500
3
    }
501
391
502
391
    unsigned Parts = ArgsParts[i];
503
391
504
391
    if (Builtin) {
505
34
      assert(Parts == 4 &&
506
34
          "Builtin calling convention requires 64-bit arguments");
507
34
    }
508
391
509
391
    if (!UsedStack && 
Parts == 2385
&&
RegsLeft == 168
) {
510
2
      // Special case for 32-bit register split, see EABI section 3.3.3
511
2
      unsigned Reg = State.AllocateReg(RegList);
512
2
      State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
513
2
      RegsLeft -= 1;
514
2
515
2
      UsedStack = true;
516
2
      CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
517
389
    } else if (Parts <= RegsLeft) {
518
984
      for (unsigned j = 0; j < Parts; 
j++610
) {
519
610
        unsigned Reg = State.AllocateReg(RegList);
520
610
        State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
521
610
        RegsLeft--;
522
610
      }
523
374
    } else {
524
15
      UsedStack = true;
525
71
      for (unsigned j = 0; j < Parts; 
j++56
)
526
56
        CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
527
15
    }
528
391
  }
529
415
}
MSP430ISelLowering.cpp:void AnalyzeArguments<llvm::ISD::InputArg>(llvm::CCState&, llvm::SmallVectorImpl<llvm::CCValAssign>&, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&)
Line
Count
Source
439
315
                             const SmallVectorImpl<ArgT> &Args) {
440
315
  static const MCPhysReg CRegList[] = {
441
315
    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
442
315
  };
443
315
  static const unsigned CNbRegs = array_lengthof(CRegList);
444
315
  static const MCPhysReg BuiltinRegList[] = {
445
315
    MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
446
315
    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
447
315
  };
448
315
  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
449
315
450
315
  ArrayRef<MCPhysReg> RegList;
451
315
  unsigned NbRegs;
452
315
453
315
  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
454
315
  if (Builtin) {
455
0
    RegList = BuiltinRegList;
456
0
    NbRegs = BuiltinNbRegs;
457
315
  } else {
458
315
    RegList = CRegList;
459
315
    NbRegs = CNbRegs;
460
315
  }
461
315
462
315
  if (State.isVarArg()) {
463
1
    AnalyzeVarArgs(State, Args);
464
1
    return;
465
1
  }
466
314
467
314
  SmallVector<unsigned, 4> ArgsParts;
468
314
  ParseFunctionArgs(Args, ArgsParts);
469
314
470
314
  if (Builtin) {
471
0
    assert(ArgsParts.size() == 2 &&
472
0
        "Builtin calling convention requires two arguments");
473
0
  }
474
314
475
314
  unsigned RegsLeft = NbRegs;
476
314
  bool UsedStack = false;
477
314
  unsigned ValNo = 0;
478
314
479
536
  for (unsigned i = 0, e = ArgsParts.size(); i != e; 
i++222
) {
480
222
    MVT ArgVT = Args[ValNo].VT;
481
222
    ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
482
222
    MVT LocVT = ArgVT;
483
222
    CCValAssign::LocInfo LocInfo = CCValAssign::Full;
484
222
485
222
    // Promote i8 to i16
486
222
    if (LocVT == MVT::i8) {
487
54
      LocVT = MVT::i16;
488
54
      if (ArgFlags.isSExt())
489
4
          LocInfo = CCValAssign::SExt;
490
50
      else if (ArgFlags.isZExt())
491
8
          LocInfo = CCValAssign::ZExt;
492
42
      else
493
42
          LocInfo = CCValAssign::AExt;
494
54
    }
495
222
496
222
    // Handle byval arguments
497
222
    if (ArgFlags.isByVal()) {
498
2
      State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
499
2
      continue;
500
2
    }
501
220
502
220
    unsigned Parts = ArgsParts[i];
503
220
504
220
    if (Builtin) {
505
0
      assert(Parts == 4 &&
506
0
          "Builtin calling convention requires 64-bit arguments");
507
0
    }
508
220
509
220
    if (!UsedStack && 
Parts == 2217
&&
RegsLeft == 17
) {
510
1
      // Special case for 32-bit register split, see EABI section 3.3.3
511
1
      unsigned Reg = State.AllocateReg(RegList);
512
1
      State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
513
1
      RegsLeft -= 1;
514
1
515
1
      UsedStack = true;
516
1
      CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
517
219
    } else if (Parts <= RegsLeft) {
518
447
      for (unsigned j = 0; j < Parts; 
j++233
) {
519
233
        unsigned Reg = State.AllocateReg(RegList);
520
233
        State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
521
233
        RegsLeft--;
522
233
      }
523
214
    } else {
524
5
      UsedStack = true;
525
23
      for (unsigned j = 0; j < Parts; 
j++18
)
526
18
        CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
527
5
    }
528
220
  }
529
314
}
MSP430ISelLowering.cpp:void AnalyzeArguments<llvm::ISD::OutputArg>(llvm::CCState&, llvm::SmallVectorImpl<llvm::CCValAssign>&, llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&)
Line
Count
Source
439
101
                             const SmallVectorImpl<ArgT> &Args) {
440
101
  static const MCPhysReg CRegList[] = {
441
101
    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
442
101
  };
443
101
  static const unsigned CNbRegs = array_lengthof(CRegList);
444
101
  static const MCPhysReg BuiltinRegList[] = {
445
101
    MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
446
101
    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
447
101
  };
448
101
  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
449
101
450
101
  ArrayRef<MCPhysReg> RegList;
451
101
  unsigned NbRegs;
452
101
453
101
  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
454
101
  if (Builtin) {
455
17
    RegList = BuiltinRegList;
456
17
    NbRegs = BuiltinNbRegs;
457
84
  } else {
458
84
    RegList = CRegList;
459
84
    NbRegs = CNbRegs;
460
84
  }
461
101
462
101
  if (State.isVarArg()) {
463
0
    AnalyzeVarArgs(State, Args);
464
0
    return;
465
0
  }
466
101
467
101
  SmallVector<unsigned, 4> ArgsParts;
468
101
  ParseFunctionArgs(Args, ArgsParts);
469
101
470
101
  if (Builtin) {
471
17
    assert(ArgsParts.size() == 2 &&
472
17
        "Builtin calling convention requires two arguments");
473
17
  }
474
101
475
101
  unsigned RegsLeft = NbRegs;
476
101
  bool UsedStack = false;
477
101
  unsigned ValNo = 0;
478
101
479
273
  for (unsigned i = 0, e = ArgsParts.size(); i != e; 
i++172
) {
480
172
    MVT ArgVT = Args[ValNo].VT;
481
172
    ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
482
172
    MVT LocVT = ArgVT;
483
172
    CCValAssign::LocInfo LocInfo = CCValAssign::Full;
484
172
485
172
    // Promote i8 to i16
486
172
    if (LocVT == MVT::i8) {
487
4
      LocVT = MVT::i16;
488
4
      if (ArgFlags.isSExt())
489
1
          LocInfo = CCValAssign::SExt;
490
3
      else if (ArgFlags.isZExt())
491
2
          LocInfo = CCValAssign::ZExt;
492
1
      else
493
1
          LocInfo = CCValAssign::AExt;
494
4
    }
495
172
496
172
    // Handle byval arguments
497
172
    if (ArgFlags.isByVal()) {
498
1
      State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
499
1
      continue;
500
1
    }
501
171
502
171
    unsigned Parts = ArgsParts[i];
503
171
504
171
    if (Builtin) {
505
34
      assert(Parts == 4 &&
506
34
          "Builtin calling convention requires 64-bit arguments");
507
34
    }
508
171
509
171
    if (!UsedStack && 
Parts == 2168
&&
RegsLeft == 161
) {
510
1
      // Special case for 32-bit register split, see EABI section 3.3.3
511
1
      unsigned Reg = State.AllocateReg(RegList);
512
1
      State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
513
1
      RegsLeft -= 1;
514
1
515
1
      UsedStack = true;
516
1
      CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
517
170
    } else if (Parts <= RegsLeft) {
518
537
      for (unsigned j = 0; j < Parts; 
j++377
) {
519
377
        unsigned Reg = State.AllocateReg(RegList);
520
377
        State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
521
377
        RegsLeft--;
522
377
      }
523
160
    } else {
524
10
      UsedStack = true;
525
48
      for (unsigned j = 0; j < Parts; 
j++38
)
526
38
        CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
527
10
    }
528
171
  }
529
101
}
530
531
static void AnalyzeRetResult(CCState &State,
532
101
                             const SmallVectorImpl<ISD::InputArg> &Ins) {
533
101
  State.AnalyzeCallResult(Ins, RetCC_MSP430);
534
101
}
535
536
static void AnalyzeRetResult(CCState &State,
537
320
                             const SmallVectorImpl<ISD::OutputArg> &Outs) {
538
320
  State.AnalyzeReturn(Outs, RetCC_MSP430);
539
320
}
540
541
template<typename ArgT>
542
static void AnalyzeReturnValues(CCState &State,
543
                                SmallVectorImpl<CCValAssign> &RVLocs,
544
421
                                const SmallVectorImpl<ArgT> &Args) {
545
421
  AnalyzeRetResult(State, Args);
546
421
}
MSP430ISelLowering.cpp:void AnalyzeReturnValues<llvm::ISD::OutputArg>(llvm::CCState&, llvm::SmallVectorImpl<llvm::CCValAssign>&, llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&)
Line
Count
Source
544
320
                                const SmallVectorImpl<ArgT> &Args) {
545
320
  AnalyzeRetResult(State, Args);
546
320
}
MSP430ISelLowering.cpp:void AnalyzeReturnValues<llvm::ISD::InputArg>(llvm::CCState&, llvm::SmallVectorImpl<llvm::CCValAssign>&, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&)
Line
Count
Source
544
101
                                const SmallVectorImpl<ArgT> &Args) {
545
101
  AnalyzeRetResult(State, Args);
546
101
}
547
548
SDValue MSP430TargetLowering::LowerFormalArguments(
549
    SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
550
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
551
318
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
552
318
553
318
  switch (CallConv) {
554
318
  default:
555
0
    report_fatal_error("Unsupported calling convention");
556
318
  case CallingConv::C:
557
315
  case CallingConv::Fast:
558
315
    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
559
315
  case CallingConv::MSP430_INTR:
560
3
    if (Ins.empty())
561
3
      return Chain;
562
0
    report_fatal_error("ISRs cannot have arguments");
563
318
  }
564
318
}
565
566
SDValue
567
MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
568
101
                                SmallVectorImpl<SDValue> &InVals) const {
569
101
  SelectionDAG &DAG                     = CLI.DAG;
570
101
  SDLoc &dl                             = CLI.DL;
571
101
  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
572
101
  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
573
101
  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
574
101
  SDValue Chain                         = CLI.Chain;
575
101
  SDValue Callee                        = CLI.Callee;
576
101
  bool &isTailCall                      = CLI.IsTailCall;
577
101
  CallingConv::ID CallConv              = CLI.CallConv;
578
101
  bool isVarArg                         = CLI.IsVarArg;
579
101
580
101
  // MSP430 target does not yet support tail call optimization.
581
101
  isTailCall = false;
582
101
583
101
  switch (CallConv) {
584
101
  default:
585
0
    report_fatal_error("Unsupported calling convention");
586
101
  case CallingConv::MSP430_BUILTIN:
587
101
  case CallingConv::Fast:
588
101
  case CallingConv::C:
589
101
    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
590
101
                          Outs, OutVals, Ins, dl, DAG, InVals);
591
101
  case CallingConv::MSP430_INTR:
592
0
    report_fatal_error("ISRs cannot be called directly");
593
101
  }
594
101
}
595
596
/// LowerCCCArguments - transform physical registers into virtual registers and
597
/// generate load operations for arguments places on the stack.
598
// FIXME: struct return stuff
599
SDValue MSP430TargetLowering::LowerCCCArguments(
600
    SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
601
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
602
315
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
603
315
  MachineFunction &MF = DAG.getMachineFunction();
604
315
  MachineFrameInfo &MFI = MF.getFrameInfo();
605
315
  MachineRegisterInfo &RegInfo = MF.getRegInfo();
606
315
  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
607
315
608
315
  // Assign locations to all of the incoming arguments.
609
315
  SmallVector<CCValAssign, 16> ArgLocs;
610
315
  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
611
315
                 *DAG.getContext());
612
315
  AnalyzeArguments(CCInfo, ArgLocs, Ins);
613
315
614
315
  // Create frame index for the start of the first vararg value
615
315
  if (isVarArg) {
616
1
    unsigned Offset = CCInfo.getNextStackOffset();
617
1
    FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
618
1
  }
619
315
620
571
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i256
) {
621
256
    CCValAssign &VA = ArgLocs[i];
622
256
    if (VA.isRegLoc()) {
623
234
      // Arguments passed in registers
624
234
      EVT RegVT = VA.getLocVT();
625
234
      switch (RegVT.getSimpleVT().SimpleTy) {
626
234
      default:
627
0
        {
628
#ifndef NDEBUG
629
          errs() << "LowerFormalArguments Unhandled argument type: "
630
               << RegVT.getEVTString() << "\n";
631
#endif
632
0
          llvm_unreachable(nullptr);
633
234
        }
634
234
      case MVT::i16:
635
234
        unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
636
234
        RegInfo.addLiveIn(VA.getLocReg(), VReg);
637
234
        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
638
234
639
234
        // If this is an 8-bit value, it is really passed promoted to 16
640
234
        // bits. Insert an assert[sz]ext to capture this, then truncate to the
641
234
        // right size.
642
234
        if (VA.getLocInfo() == CCValAssign::SExt)
643
4
          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
644
4
                                 DAG.getValueType(VA.getValVT()));
645
230
        else if (VA.getLocInfo() == CCValAssign::ZExt)
646
8
          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
647
8
                                 DAG.getValueType(VA.getValVT()));
648
234
649
234
        if (VA.getLocInfo() != CCValAssign::Full)
650
54
          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
651
234
652
234
        InVals.push_back(ArgValue);
653
234
      }
654
234
    } else {
655
22
      // Sanity check
656
22
      assert(VA.isMemLoc());
657
22
658
22
      SDValue InVal;
659
22
      ISD::ArgFlagsTy Flags = Ins[i].Flags;
660
22
661
22
      if (Flags.isByVal()) {
662
2
        int FI = MFI.CreateFixedObject(Flags.getByValSize(),
663
2
                                       VA.getLocMemOffset(), true);
664
2
        InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
665
20
      } else {
666
20
        // Load the argument to a virtual register
667
20
        unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
668
20
        if (ObjSize > 2) {
669
0
            errs() << "LowerFormalArguments Unhandled argument type: "
670
0
                << EVT(VA.getLocVT()).getEVTString()
671
0
                << "\n";
672
0
        }
673
20
        // Create the frame index object for this incoming parameter...
674
20
        int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
675
20
676
20
        // Create the SelectionDAG nodes corresponding to a load
677
20
        //from this parameter
678
20
        SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
679
20
        InVal = DAG.getLoad(
680
20
            VA.getLocVT(), dl, Chain, FIN,
681
20
            MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
682
20
      }
683
22
684
22
      InVals.push_back(InVal);
685
22
    }
686
256
  }
687
315
688
571
  
for (unsigned i = 0, e = ArgLocs.size(); 315
i != e;
++i256
) {
689
256
    if (Ins[i].Flags.isSRet()) {
690
2
      unsigned Reg = FuncInfo->getSRetReturnReg();
691
2
      if (!Reg) {
692
2
        Reg = MF.getRegInfo().createVirtualRegister(
693
2
            getRegClassFor(MVT::i16));
694
2
        FuncInfo->setSRetReturnReg(Reg);
695
2
      }
696
2
      SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
697
2
      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
698
2
    }
699
256
  }
700
315
701
315
  return Chain;
702
315
}
703
704
bool
705
MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
706
                                     MachineFunction &MF,
707
                                     bool IsVarArg,
708
                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
709
419
                                     LLVMContext &Context) const {
710
419
  SmallVector<CCValAssign, 16> RVLocs;
711
419
  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
712
419
  return CCInfo.CheckReturn(Outs, RetCC_MSP430);
713
419
}
714
715
SDValue
716
MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
717
                                  bool isVarArg,
718
                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
719
                                  const SmallVectorImpl<SDValue> &OutVals,
720
320
                                  const SDLoc &dl, SelectionDAG &DAG) const {
721
320
722
320
  MachineFunction &MF = DAG.getMachineFunction();
723
320
724
320
  // CCValAssign - represent the assignment of the return value to a location
725
320
  SmallVector<CCValAssign, 16> RVLocs;
726
320
727
320
  // ISRs cannot return any value.
728
320
  if (CallConv == CallingConv::MSP430_INTR && 
!Outs.empty()3
)
729
0
    report_fatal_error("ISRs cannot return any value");
730
320
731
320
  // CCState - Info about the registers and stack slot.
732
320
  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
733
320
                 *DAG.getContext());
734
320
735
320
  // Analize return values.
736
320
  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
737
320
738
320
  SDValue Flag;
739
320
  SmallVector<SDValue, 4> RetOps(1, Chain);
740
320
741
320
  // Copy the result values into the output registers.
742
635
  for (unsigned i = 0; i != RVLocs.size(); 
++i315
) {
743
315
    CCValAssign &VA = RVLocs[i];
744
315
    assert(VA.isRegLoc() && "Can only return in registers!");
745
315
746
315
    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
747
315
                             OutVals[i], Flag);
748
315
749
315
    // Guarantee that all emitted copies are stuck together,
750
315
    // avoiding something bad.
751
315
    Flag = Chain.getValue(1);
752
315
    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
753
315
  }
754
320
755
320
  if (MF.getFunction().hasStructRetAttr()) {
756
1
    MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
757
1
    unsigned Reg = FuncInfo->getSRetReturnReg();
758
1
759
1
    if (!Reg)
760
1
      
llvm_unreachable0
("sret virtual register not created in entry block");
761
1
762
1
    SDValue Val =
763
1
      DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
764
1
    unsigned R12 = MSP430::R12;
765
1
766
1
    Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
767
1
    Flag = Chain.getValue(1);
768
1
    RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
769
1
  }
770
320
771
320
  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
772
317
                  
MSP430ISD::RETI_FLAG3
: MSP430ISD::RET_FLAG);
773
320
774
320
  RetOps[0] = Chain;  // Update chain.
775
320
776
320
  // Add the flag if we have it.
777
320
  if (Flag.getNode())
778
196
    RetOps.push_back(Flag);
779
320
780
320
  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
781
320
}
782
783
/// LowerCCCCallTo - functions arguments are copied from virtual regs to
784
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
785
SDValue MSP430TargetLowering::LowerCCCCallTo(
786
    SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
787
    bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
788
    const SmallVectorImpl<SDValue> &OutVals,
789
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
790
101
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
791
101
  // Analyze operands of the call, assigning locations to each operand.
792
101
  SmallVector<CCValAssign, 16> ArgLocs;
793
101
  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
794
101
                 *DAG.getContext());
795
101
  AnalyzeArguments(CCInfo, ArgLocs, Outs);
796
101
797
101
  // Get a count of how many bytes are to be pushed on the stack.
798
101
  unsigned NumBytes = CCInfo.getNextStackOffset();
799
101
  auto PtrVT = getPointerTy(DAG.getDataLayout());
800
101
801
101
  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
802
101
803
101
  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
804
101
  SmallVector<SDValue, 12> MemOpChains;
805
101
  SDValue StackPtr;
806
101
807
101
  // Walk the register/memloc assignments, inserting copies/loads.
808
519
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i418
) {
809
418
    CCValAssign &VA = ArgLocs[i];
810
418
811
418
    SDValue Arg = OutVals[i];
812
418
813
418
    // Promote the value if needed.
814
418
    switch (VA.getLocInfo()) {
815
418
      
default: 0
llvm_unreachable0
("Unknown loc info!");
816
418
      
case CCValAssign::Full: break414
;
817
418
      case CCValAssign::SExt:
818
1
        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
819
1
        break;
820
418
      case CCValAssign::ZExt:
821
2
        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
822
2
        break;
823
418
      case CCValAssign::AExt:
824
1
        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
825
1
        break;
826
418
    }
827
418
828
418
    // Arguments that can be passed on register must be kept at RegsToPass
829
418
    // vector
830
418
    if (VA.isRegLoc()) {
831
378
      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
832
378
    } else {
833
40
      assert(VA.isMemLoc());
834
40
835
40
      if (!StackPtr.getNode())
836
11
        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
837
40
838
40
      SDValue PtrOff =
839
40
          DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
840
40
                      DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
841
40
842
40
      SDValue MemOp;
843
40
      ISD::ArgFlagsTy Flags = Outs[i].Flags;
844
40
845
40
      if (Flags.isByVal()) {
846
1
        SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
847
1
        MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
848
1
                              Flags.getByValAlign(),
849
1
                              /*isVolatile*/false,
850
1
                              /*AlwaysInline=*/true,
851
1
                              /*isTailCall=*/false,
852
1
                              MachinePointerInfo(),
853
1
                              MachinePointerInfo());
854
39
      } else {
855
39
        MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
856
39
      }
857
40
858
40
      MemOpChains.push_back(MemOp);
859
40
    }
860
418
  }
861
101
862
101
  // Transform all store nodes into one single node because all store nodes are
863
101
  // independent of each other.
864
101
  if (!MemOpChains.empty())
865
11
    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
866
101
867
101
  // Build a sequence of copy-to-reg nodes chained together with token chain and
868
101
  // flag operands which copy the outgoing args into registers.  The InFlag in
869
101
  // necessary since all emitted instructions must be stuck together.
870
101
  SDValue InFlag;
871
479
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i378
) {
872
378
    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
873
378
                             RegsToPass[i].second, InFlag);
874
378
    InFlag = Chain.getValue(1);
875
378
  }
876
101
877
101
  // If the callee is a GlobalAddress node (quite common, every direct call is)
878
101
  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
879
101
  // Likewise ExternalSymbol -> TargetExternalSymbol.
880
101
  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
881
20
    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
882
81
  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
883
80
    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
884
101
885
101
  // Returns a chain & a flag for retval copy to use.
886
101
  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
887
101
  SmallVector<SDValue, 8> Ops;
888
101
  Ops.push_back(Chain);
889
101
  Ops.push_back(Callee);
890
101
891
101
  // Add argument registers to the end of the list so that they are
892
101
  // known live into the call.
893
479
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i378
)
894
378
    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
895
378
                                  RegsToPass[i].second.getValueType()));
896
101
897
101
  if (InFlag.getNode())
898
95
    Ops.push_back(InFlag);
899
101
900
101
  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
901
101
  InFlag = Chain.getValue(1);
902
101
903
101
  // Create the CALLSEQ_END node.
904
101
  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
905
101
                             DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
906
101
  InFlag = Chain.getValue(1);
907
101
908
101
  // Handle result values, copying them out of physregs into vregs that we
909
101
  // return.
910
101
  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
911
101
                         DAG, InVals);
912
101
}
913
914
/// LowerCallResult - Lower the result values of a call into the
915
/// appropriate copies out of appropriate physical registers.
916
///
917
SDValue MSP430TargetLowering::LowerCallResult(
918
    SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
919
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
920
101
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
921
101
922
101
  // Assign locations to each value returned by this call.
923
101
  SmallVector<CCValAssign, 16> RVLocs;
924
101
  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
925
101
                 *DAG.getContext());
926
101
927
101
  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
928
101
929
101
  // Copy all of the result registers out of their specified physreg.
930
313
  for (unsigned i = 0; i != RVLocs.size(); 
++i212
) {
931
212
    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
932
212
                               RVLocs[i].getValVT(), InFlag).getValue(1);
933
212
    InFlag = Chain.getValue(2);
934
212
    InVals.push_back(Chain.getValue(0));
935
212
  }
936
101
937
101
  return Chain;
938
101
}
939
940
SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
941
38
                                          SelectionDAG &DAG) const {
942
38
  unsigned Opc = Op.getOpcode();
943
38
  SDNode* N = Op.getNode();
944
38
  EVT VT = Op.getValueType();
945
38
  SDLoc dl(N);
946
38
947
38
  // Expand non-constant shifts to loops:
948
38
  if (!isa<ConstantSDNode>(N->getOperand(1)))
949
12
    return Op;
950
26
951
26
  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
952
26
953
26
  // Expand the stuff into sequence of shifts.
954
26
  SDValue Victim = N->getOperand(0);
955
26
956
26
  if (ShiftAmount >= 8) {
957
4
    assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
958
4
    switch(Opc) {
959
4
    default:
960
0
      llvm_unreachable("Unknown shift");
961
4
    case ISD::SHL:
962
1
      // foo << (8 + N) => swpb(zext(foo)) << N
963
1
      Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
964
1
      Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
965
1
      break;
966
4
    case ISD::SRA:
967
3
    case ISD::SRL:
968
3
      // foo >> (8 + N) => sxt(swpb(foo)) >> N
969
3
      Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
970
3
      Victim = (Opc == ISD::SRA)
971
3
                   ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
972
1
                                 DAG.getValueType(MVT::i8))
973
3
                   : 
DAG.getZeroExtendInReg(Victim, dl, MVT::i8)2
;
974
3
      break;
975
4
    }
976
4
    ShiftAmount -= 8;
977
4
  }
978
26
979
26
  if (Opc == ISD::SRL && 
ShiftAmount5
) {
980
5
    // Emit a special goodness here:
981
5
    // srl A, 1 => clrc; rrc A
982
5
    Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
983
5
    ShiftAmount -= 1;
984
5
  }
985
26
986
57
  while (ShiftAmount--)
987
31
    Victim = DAG.getNode((Opc == ISD::SHL ? 
MSP430ISD::RLA7
:
MSP430ISD::RRA24
),
988
31
                         dl, VT, Victim);
989
26
990
26
  return Victim;
991
26
}
992
993
SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
994
367
                                                 SelectionDAG &DAG) const {
995
367
  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
996
367
  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
997
367
  auto PtrVT = getPointerTy(DAG.getDataLayout());
998
367
999
367
  // Create the TargetGlobalAddress node, folding in the constant offset.
1000
367
  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1001
367
  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1002
367
}
1003
1004
SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
1005
0
                                                  SelectionDAG &DAG) const {
1006
0
  SDLoc dl(Op);
1007
0
  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1008
0
  auto PtrVT = getPointerTy(DAG.getDataLayout());
1009
0
  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1010
0
1011
0
  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1012
0
}
1013
1014
SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
1015
1
                                                SelectionDAG &DAG) const {
1016
1
  SDLoc dl(Op);
1017
1
  auto PtrVT = getPointerTy(DAG.getDataLayout());
1018
1
  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1019
1
  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1020
1
1021
1
  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1022
1
}
1023
1024
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1025
99
                       ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1026
99
  // FIXME: Handle bittests someday
1027
99
  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1028
99
1029
99
  // FIXME: Handle jump negative someday
1030
99
  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
1031
99
  switch (CC) {
1032
99
  
default: 0
llvm_unreachable0
("Invalid integer condition!");
1033
99
  case ISD::SETEQ:
1034
26
    TCC = MSP430CC::COND_E;     // aka COND_Z
1035
26
    // Minor optimization: if LHS is a constant, swap operands, then the
1036
26
    // constant can be folded into comparison.
1037
26
    if (LHS.getOpcode() == ISD::Constant)
1038
0
      std::swap(LHS, RHS);
1039
26
    break;
1040
99
  case ISD::SETNE:
1041
37
    TCC = MSP430CC::COND_NE;    // aka COND_NZ
1042
37
    // Minor optimization: if LHS is a constant, swap operands, then the
1043
37
    // constant can be folded into comparison.
1044
37
    if (LHS.getOpcode() == ISD::Constant)
1045
7
      std::swap(LHS, RHS);
1046
37
    break;
1047
99
  case ISD::SETULE:
1048
1
    std::swap(LHS, RHS);
1049
1
    LLVM_FALLTHROUGH;
1050
4
  case ISD::SETUGE:
1051
4
    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1052
4
    // fold constant into instruction.
1053
4
    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1054
0
      LHS = RHS;
1055
0
      RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1056
0
      TCC = MSP430CC::COND_LO;
1057
0
      break;
1058
0
    }
1059
4
    TCC = MSP430CC::COND_HS;    // aka COND_C
1060
4
    break;
1061
4
  case ISD::SETUGT:
1062
4
    std::swap(LHS, RHS);
1063
4
    LLVM_FALLTHROUGH;
1064
18
  case ISD::SETULT:
1065
18
    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1066
18
    // fold constant into instruction.
1067
18
    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1068
3
      LHS = RHS;
1069
3
      RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1070
3
      TCC = MSP430CC::COND_HS;
1071
3
      break;
1072
3
    }
1073
15
    TCC = MSP430CC::COND_LO;    // aka COND_NC
1074
15
    break;
1075
15
  case ISD::SETLE:
1076
3
    std::swap(LHS, RHS);
1077
3
    LLVM_FALLTHROUGH;
1078
4
  case ISD::SETGE:
1079
4
    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1080
4
    // fold constant into instruction.
1081
4
    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1082
0
      LHS = RHS;
1083
0
      RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1084
0
      TCC = MSP430CC::COND_L;
1085
0
      break;
1086
0
    }
1087
4
    TCC = MSP430CC::COND_GE;
1088
4
    break;
1089
5
  case ISD::SETGT:
1090
5
    std::swap(LHS, RHS);
1091
5
    LLVM_FALLTHROUGH;
1092
10
  case ISD::SETLT:
1093
10
    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1094
10
    // fold constant into instruction.
1095
10
    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1096
4
      LHS = RHS;
1097
4
      RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1098
4
      TCC = MSP430CC::COND_GE;
1099
4
      break;
1100
4
    }
1101
6
    TCC = MSP430CC::COND_L;
1102
6
    break;
1103
99
  }
1104
99
1105
99
  TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1106
99
  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1107
99
}
1108
1109
1110
30
SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1111
30
  SDValue Chain = Op.getOperand(0);
1112
30
  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1113
30
  SDValue LHS   = Op.getOperand(2);
1114
30
  SDValue RHS   = Op.getOperand(3);
1115
30
  SDValue Dest  = Op.getOperand(4);
1116
30
  SDLoc dl  (Op);
1117
30
1118
30
  SDValue TargetCC;
1119
30
  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1120
30
1121
30
  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1122
30
                     Chain, Dest, TargetCC, Flag);
1123
30
}
1124
1125
57
SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1126
57
  SDValue LHS   = Op.getOperand(0);
1127
57
  SDValue RHS   = Op.getOperand(1);
1128
57
  SDLoc dl  (Op);
1129
57
1130
57
  // If we are doing an AND and testing against zero, then the CMP
1131
57
  // will not be generated.  The AND (or BIT) will generate the condition codes,
1132
57
  // but they are different from CMP.
1133
57
  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1134
57
  // lowering & isel wouldn't diverge.
1135
57
  bool andCC = false;
1136
57
  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1137
35
    if (RHSC->isNullValue() && 
LHS.hasOneUse()31
&&
1138
35
        
(28
LHS.getOpcode() == ISD::AND28
||
1139
28
         
(11
LHS.getOpcode() == ISD::TRUNCATE11
&&
1140
18
          
LHS.getOperand(0).getOpcode() == ISD::AND1
))) {
1141
18
      andCC = true;
1142
18
    }
1143
35
  }
1144
57
  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1145
57
  SDValue TargetCC;
1146
57
  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1147
57
1148
57
  // Get the condition codes directly from the status register, if its easy.
1149
57
  // Otherwise a branch will be generated.  Note that the AND and BIT
1150
57
  // instructions generate different flags than CMP, the carry bit can be used
1151
57
  // for NE/EQ.
1152
57
  bool Invert = false;
1153
57
  bool Shift = false;
1154
57
  bool Convert = true;
1155
57
  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1156
57
   default:
1157
12
    Convert = false;
1158
12
    break;
1159
57
   case MSP430CC::COND_HS:
1160
2
     // Res = SR & 1, no processing is required
1161
2
     break;
1162
57
   case MSP430CC::COND_LO:
1163
14
     // Res = ~(SR & 1)
1164
14
     Invert = true;
1165
14
     break;
1166
57
   case MSP430CC::COND_NE:
1167
23
     if (andCC) {
1168
17
       // C = ~Z, thus Res = SR & 1, no processing is required
1169
17
     } else {
1170
6
       // Res = ~((SR >> 1) & 1)
1171
6
       Shift = true;
1172
6
       Invert = true;
1173
6
     }
1174
23
     break;
1175
57
   case MSP430CC::COND_E:
1176
6
     Shift = true;
1177
6
     // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1178
6
     // Res = (SR >> 1) & 1 is 1 word shorter.
1179
6
     break;
1180
57
  }
1181
57
  EVT VT = Op.getValueType();
1182
57
  SDValue One  = DAG.getConstant(1, dl, VT);
1183
57
  if (Convert) {
1184
45
    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1185
45
                                    MVT::i16, Flag);
1186
45
    if (Shift)
1187
12
      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1188
12
      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1189
45
    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1190
45
    if (Invert)
1191
20
      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1192
45
    return SR;
1193
45
  } else {
1194
12
    SDValue Zero = DAG.getConstant(0, dl, VT);
1195
12
    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1196
12
    SDValue Ops[] = {One, Zero, TargetCC, Flag};
1197
12
    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1198
12
  }
1199
57
}
1200
1201
SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
1202
12
                                             SelectionDAG &DAG) const {
1203
12
  SDValue LHS    = Op.getOperand(0);
1204
12
  SDValue RHS    = Op.getOperand(1);
1205
12
  SDValue TrueV  = Op.getOperand(2);
1206
12
  SDValue FalseV = Op.getOperand(3);
1207
12
  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1208
12
  SDLoc dl   (Op);
1209
12
1210
12
  SDValue TargetCC;
1211
12
  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1212
12
1213
12
  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1214
12
  SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1215
12
1216
12
  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1217
12
}
1218
1219
SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1220
2
                                               SelectionDAG &DAG) const {
1221
2
  SDValue Val = Op.getOperand(0);
1222
2
  EVT VT      = Op.getValueType();
1223
2
  SDLoc dl(Op);
1224
2
1225
2
  assert(VT == MVT::i16 && "Only support i16 for now!");
1226
2
1227
2
  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1228
2
                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1229
2
                     DAG.getValueType(Val.getValueType()));
1230
2
}
1231
1232
SDValue
1233
0
MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1234
0
  MachineFunction &MF = DAG.getMachineFunction();
1235
0
  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1236
0
  int ReturnAddrIndex = FuncInfo->getRAIndex();
1237
0
  auto PtrVT = getPointerTy(MF.getDataLayout());
1238
0
1239
0
  if (ReturnAddrIndex == 0) {
1240
0
    // Set up a frame object for the return address.
1241
0
    uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1242
0
    ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1243
0
                                                           true);
1244
0
    FuncInfo->setRAIndex(ReturnAddrIndex);
1245
0
  }
1246
0
1247
0
  return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1248
0
}
1249
1250
SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1251
0
                                              SelectionDAG &DAG) const {
1252
0
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1253
0
  MFI.setReturnAddressIsTaken(true);
1254
0
1255
0
  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1256
0
    return SDValue();
1257
0
1258
0
  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1259
0
  SDLoc dl(Op);
1260
0
  auto PtrVT = getPointerTy(DAG.getDataLayout());
1261
0
1262
0
  if (Depth > 0) {
1263
0
    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1264
0
    SDValue Offset =
1265
0
        DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16);
1266
0
    return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1267
0
                       DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1268
0
                       MachinePointerInfo());
1269
0
  }
1270
0
1271
0
  // Just load the return address.
1272
0
  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1273
0
  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1274
0
                     MachinePointerInfo());
1275
0
}
1276
1277
SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1278
1
                                             SelectionDAG &DAG) const {
1279
1
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1280
1
  MFI.setFrameAddressIsTaken(true);
1281
1
1282
1
  EVT VT = Op.getValueType();
1283
1
  SDLoc dl(Op);  // FIXME probably not meaningful
1284
1
  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1285
1
  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1286
1
                                         MSP430::FP, VT);
1287
1
  while (Depth--)
1288
0
    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1289
0
                            MachinePointerInfo());
1290
1
  return FrameAddr;
1291
1
}
1292
1293
SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1294
1
                                           SelectionDAG &DAG) const {
1295
1
  MachineFunction &MF = DAG.getMachineFunction();
1296
1
  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1297
1
  auto PtrVT = getPointerTy(DAG.getDataLayout());
1298
1
1299
1
  // Frame index of first vararg argument
1300
1
  SDValue FrameIndex =
1301
1
      DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1302
1
  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1303
1
1304
1
  // Create a store of the frame index to the location operand
1305
1
  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1306
1
                      MachinePointerInfo(SV));
1307
1
}
1308
1309
SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1310
2
                                             SelectionDAG &DAG) const {
1311
2
    JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1312
2
    auto PtrVT = getPointerTy(DAG.getDataLayout());
1313
2
    SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1314
2
    return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1315
2
}
1316
1317
/// getPostIndexedAddressParts - returns true by value, base pointer and
1318
/// offset pointer and addressing mode by reference if this node can be
1319
/// combined with a load / store to form a post-indexed load / store.
1320
bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1321
                                                      SDValue &Base,
1322
                                                      SDValue &Offset,
1323
                                                      ISD::MemIndexedMode &AM,
1324
34
                                                      SelectionDAG &DAG) const {
1325
34
1326
34
  LoadSDNode *LD = cast<LoadSDNode>(N);
1327
34
  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1328
0
    return false;
1329
34
1330
34
  EVT VT = LD->getMemoryVT();
1331
34
  if (VT != MVT::i8 && 
VT != MVT::i1620
)
1332
0
    return false;
1333
34
1334
34
  if (Op->getOpcode() != ISD::ADD)
1335
0
    return false;
1336
34
1337
34
  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1338
34
    uint64_t RHSC = RHS->getZExtValue();
1339
34
    if ((VT == MVT::i16 && 
RHSC != 220
) ||
1340
34
        
(26
VT == MVT::i826
&&
RHSC != 114
))
1341
22
      return false;
1342
12
1343
12
    Base = Op->getOperand(0);
1344
12
    Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1345
12
    AM = ISD::POST_INC;
1346
12
    return true;
1347
12
  }
1348
0
1349
0
  return false;
1350
0
}
1351
1352
1353
0
const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1354
0
  switch ((MSP430ISD::NodeType)Opcode) {
1355
0
  case MSP430ISD::FIRST_NUMBER:       break;
1356
0
  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1357
0
  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1358
0
  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1359
0
  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1360
0
  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1361
0
  case MSP430ISD::RRCL:               return "MSP430ISD::RRCL";
1362
0
  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1363
0
  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1364
0
  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1365
0
  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1366
0
  case MSP430ISD::SETCC:              return "MSP430ISD::SETCC";
1367
0
  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1368
0
  case MSP430ISD::DADD:               return "MSP430ISD::DADD";
1369
0
  }
1370
0
  return nullptr;
1371
0
}
1372
1373
bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1374
10
                                          Type *Ty2) const {
1375
10
  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1376
0
    return false;
1377
10
1378
10
  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1379
10
}
1380
1381
147
bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1382
147
  if (!VT1.isInteger() || !VT2.isInteger())
1383
0
    return false;
1384
147
1385
147
  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1386
147
}
1387
1388
0
bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1389
0
  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1390
0
  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1391
0
}
1392
1393
244
bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1394
244
  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1395
244
  return 0 && 
VT1 == MVT::i80
&&
VT2 == MVT::i160
;
1396
244
}
1397
1398
61
bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1399
61
  return isZExtFree(Val.getValueType(), VT2);
1400
61
}
1401
1402
//===----------------------------------------------------------------------===//
1403
//  Other Lowering Code
1404
//===----------------------------------------------------------------------===//
1405
1406
MachineBasicBlock *
1407
MSP430TargetLowering::EmitShiftInstr(MachineInstr &MI,
1408
11
                                     MachineBasicBlock *BB) const {
1409
11
  MachineFunction *F = BB->getParent();
1410
11
  MachineRegisterInfo &RI = F->getRegInfo();
1411
11
  DebugLoc dl = MI.getDebugLoc();
1412
11
  const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1413
11
1414
11
  unsigned Opc;
1415
11
  bool ClearCarry = false;
1416
11
  const TargetRegisterClass * RC;
1417
11
  switch (MI.getOpcode()) {
1418
11
  
default: 0
llvm_unreachable0
("Invalid shift opcode!");
1419
11
  case MSP430::Shl8:
1420
1
    Opc = MSP430::ADD8rr;
1421
1
    RC = &MSP430::GR8RegClass;
1422
1
    break;
1423
11
  case MSP430::Shl16:
1424
1
    Opc = MSP430::ADD16rr;
1425
1
    RC = &MSP430::GR16RegClass;
1426
1
    break;
1427
11
  case MSP430::Sra8:
1428
1
    Opc = MSP430::RRA8r;
1429
1
    RC = &MSP430::GR8RegClass;
1430
1
    break;
1431
11
  case MSP430::Sra16:
1432
1
    Opc = MSP430::RRA16r;
1433
1
    RC = &MSP430::GR16RegClass;
1434
1
    break;
1435
11
  case MSP430::Srl8:
1436
1
    ClearCarry = true;
1437
1
    Opc = MSP430::RRC8r;
1438
1
    RC = &MSP430::GR8RegClass;
1439
1
    break;
1440
11
  case MSP430::Srl16:
1441
1
    ClearCarry = true;
1442
1
    Opc = MSP430::RRC16r;
1443
1
    RC = &MSP430::GR16RegClass;
1444
1
    break;
1445
11
  case MSP430::Rrcl8:
1446
5
  case MSP430::Rrcl16: {
1447
5
    BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1448
5
      .addReg(MSP430::SR).addImm(1);
1449
5
    unsigned SrcReg = MI.getOperand(1).getReg();
1450
5
    unsigned DstReg = MI.getOperand(0).getReg();
1451
5
    unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1452
5
                    ? 
MSP430::RRC16r4
:
MSP430::RRC8r1
;
1453
5
    BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1454
5
      .addReg(SrcReg);
1455
5
    MI.eraseFromParent(); // The pseudo instruction is gone now.
1456
5
    return BB;
1457
6
  }
1458
6
  }
1459
6
1460
6
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1461
6
  MachineFunction::iterator I = ++BB->getIterator();
1462
6
1463
6
  // Create loop block
1464
6
  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1465
6
  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1466
6
1467
6
  F->insert(I, LoopBB);
1468
6
  F->insert(I, RemBB);
1469
6
1470
6
  // Update machine-CFG edges by transferring all successors of the current
1471
6
  // block to the block containing instructions after shift.
1472
6
  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1473
6
                BB->end());
1474
6
  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1475
6
1476
6
  // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1477
6
  BB->addSuccessor(LoopBB);
1478
6
  BB->addSuccessor(RemBB);
1479
6
  LoopBB->addSuccessor(RemBB);
1480
6
  LoopBB->addSuccessor(LoopBB);
1481
6
1482
6
  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1483
6
  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1484
6
  unsigned ShiftReg = RI.createVirtualRegister(RC);
1485
6
  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1486
6
  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1487
6
  unsigned SrcReg = MI.getOperand(1).getReg();
1488
6
  unsigned DstReg = MI.getOperand(0).getReg();
1489
6
1490
6
  // BB:
1491
6
  // cmp 0, N
1492
6
  // je RemBB
1493
6
  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1494
6
    .addReg(ShiftAmtSrcReg).addImm(0);
1495
6
  BuildMI(BB, dl, TII.get(MSP430::JCC))
1496
6
    .addMBB(RemBB)
1497
6
    .addImm(MSP430CC::COND_E);
1498
6
1499
6
  // LoopBB:
1500
6
  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1501
6
  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1502
6
  // ShiftReg2 = shift ShiftReg
1503
6
  // ShiftAmt2 = ShiftAmt - 1;
1504
6
  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1505
6
    .addReg(SrcReg).addMBB(BB)
1506
6
    .addReg(ShiftReg2).addMBB(LoopBB);
1507
6
  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1508
6
    .addReg(ShiftAmtSrcReg).addMBB(BB)
1509
6
    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1510
6
  if (ClearCarry)
1511
2
    BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1512
2
      .addReg(MSP430::SR).addImm(1);
1513
6
  if (Opc == MSP430::ADD8rr || 
Opc == MSP430::ADD16rr5
)
1514
2
    BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1515
2
      .addReg(ShiftReg)
1516
2
      .addReg(ShiftReg);
1517
4
  else
1518
4
    BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1519
4
      .addReg(ShiftReg);
1520
6
  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1521
6
    .addReg(ShiftAmtReg).addImm(1);
1522
6
  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1523
6
    .addMBB(LoopBB)
1524
6
    .addImm(MSP430CC::COND_NE);
1525
6
1526
6
  // RemBB:
1527
6
  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1528
6
  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1529
6
    .addReg(SrcReg).addMBB(BB)
1530
6
    .addReg(ShiftReg2).addMBB(LoopBB);
1531
6
1532
6
  MI.eraseFromParent(); // The pseudo instruction is gone now.
1533
6
  return RemBB;
1534
6
}
1535
1536
MachineBasicBlock *
1537
MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1538
35
                                                  MachineBasicBlock *BB) const {
1539
35
  unsigned Opc = MI.getOpcode();
1540
35
1541
35
  if (Opc == MSP430::Shl8  || 
Opc == MSP430::Shl1634
||
1542
35
      
Opc == MSP430::Sra833
||
Opc == MSP430::Sra1632
||
1543
35
      
Opc == MSP430::Srl831
||
Opc == MSP430::Srl1630
||
1544
35
      
Opc == MSP430::Rrcl829
||
Opc == MSP430::Rrcl1628
)
1545
11
    return EmitShiftInstr(MI, BB);
1546
24
1547
24
  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1548
24
  DebugLoc dl = MI.getDebugLoc();
1549
24
1550
24
  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1551
24
         "Unexpected instr type to insert");
1552
24
1553
24
  // To "insert" a SELECT instruction, we actually have to insert the diamond
1554
24
  // control-flow pattern.  The incoming instruction knows the destination vreg
1555
24
  // to set, the condition code register to branch on, the true/false values to
1556
24
  // select between, and a branch opcode to use.
1557
24
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1558
24
  MachineFunction::iterator I = ++BB->getIterator();
1559
24
1560
24
  //  thisMBB:
1561
24
  //  ...
1562
24
  //   TrueVal = ...
1563
24
  //   cmpTY ccX, r1, r2
1564
24
  //   jCC copy1MBB
1565
24
  //   fallthrough --> copy0MBB
1566
24
  MachineBasicBlock *thisMBB = BB;
1567
24
  MachineFunction *F = BB->getParent();
1568
24
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1569
24
  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1570
24
  F->insert(I, copy0MBB);
1571
24
  F->insert(I, copy1MBB);
1572
24
  // Update machine-CFG edges by transferring all successors of the current
1573
24
  // block to the new block which will contain the Phi node for the select.
1574
24
  copy1MBB->splice(copy1MBB->begin(), BB,
1575
24
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1576
24
  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1577
24
  // Next, add the true and fallthrough blocks as its successors.
1578
24
  BB->addSuccessor(copy0MBB);
1579
24
  BB->addSuccessor(copy1MBB);
1580
24
1581
24
  BuildMI(BB, dl, TII.get(MSP430::JCC))
1582
24
      .addMBB(copy1MBB)
1583
24
      .addImm(MI.getOperand(3).getImm());
1584
24
1585
24
  //  copy0MBB:
1586
24
  //   %FalseValue = ...
1587
24
  //   # fallthrough to copy1MBB
1588
24
  BB = copy0MBB;
1589
24
1590
24
  // Update machine-CFG edges
1591
24
  BB->addSuccessor(copy1MBB);
1592
24
1593
24
  //  copy1MBB:
1594
24
  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1595
24
  //  ...
1596
24
  BB = copy1MBB;
1597
24
  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1598
24
      .addReg(MI.getOperand(2).getReg())
1599
24
      .addMBB(copy0MBB)
1600
24
      .addReg(MI.getOperand(1).getReg())
1601
24
      .addMBB(thisMBB);
1602
24
1603
24
  MI.eraseFromParent(); // The pseudo instruction is gone now.
1604
24
  return BB;
1605
24
}