Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
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//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430RegisterInfo.h"
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#include "MSP430.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "msp430-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "MSP430GenRegisterInfo.inc"
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// FIXME: Provide proper call frame setup / destroy opcodes.
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MSP430RegisterInfo::MSP430RegisterInfo()
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  : MSP430GenRegisterInfo(MSP430::PC) {}
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const MCPhysReg*
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MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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  const MSP430FrameLowering *TFI = getFrameLowering(*MF);
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  const Function* F = &MF->getFunction();
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  static const MCPhysReg CalleeSavedRegs[] = {
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    MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
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    MSP430::R8, MSP430::R9, MSP430::R10,
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    0
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  };
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  static const MCPhysReg CalleeSavedRegsFP[] = {
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    MSP430::R5, MSP430::R6, MSP430::R7,
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    MSP430::R8, MSP430::R9, MSP430::R10,
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    0
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  };
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  static const MCPhysReg CalleeSavedRegsIntr[] = {
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    MSP430::FP,  MSP430::R5,  MSP430::R6,  MSP430::R7,
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    MSP430::R8,  MSP430::R9,  MSP430::R10, MSP430::R11,
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    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
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    0
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  };
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  static const MCPhysReg CalleeSavedRegsIntrFP[] = {
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    MSP430::R5,  MSP430::R6,  MSP430::R7,
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    MSP430::R8,  MSP430::R9,  MSP430::R10, MSP430::R11,
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    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
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    0
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  };
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  if (TFI->hasFP(*MF))
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    return (F->getCallingConv() == CallingConv::MSP430_INTR ?
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CalleeSavedRegsIntrFP8
: CalleeSavedRegsFP);
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  else
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    return (F->getCallingConv() == CallingConv::MSP430_INTR ?
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CalleeSavedRegsIntr5
: CalleeSavedRegs);
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}
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BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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  BitVector Reserved(getNumRegs());
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  const MSP430FrameLowering *TFI = getFrameLowering(MF);
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  // Mark 4 special registers with subregisters as reserved.
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  Reserved.set(MSP430::PCB);
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  Reserved.set(MSP430::SPB);
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  Reserved.set(MSP430::SRB);
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  Reserved.set(MSP430::CGB);
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  Reserved.set(MSP430::PC);
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  Reserved.set(MSP430::SP);
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  Reserved.set(MSP430::SR);
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  Reserved.set(MSP430::CG);
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  // Mark frame pointer as reserved if needed.
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  if (TFI->hasFP(MF)) {
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    Reserved.set(MSP430::FPB);
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    Reserved.set(MSP430::FP);
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  }
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  return Reserved;
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}
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const TargetRegisterClass *
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MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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                                                                         const {
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  return &MSP430::GR16RegClass;
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}
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void
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MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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                                        int SPAdj, unsigned FIOperandNum,
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                                        RegScavenger *RS) const {
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  assert(SPAdj == 0 && "Unexpected");
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  MachineInstr &MI = *II;
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  MachineBasicBlock &MBB = *MI.getParent();
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  MachineFunction &MF = *MBB.getParent();
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  const MSP430FrameLowering *TFI = getFrameLowering(MF);
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  DebugLoc dl = MI.getDebugLoc();
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  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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  unsigned BasePtr = (TFI->hasFP(MF) ? 
MSP430::FP16
:
MSP430::SP346
);
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  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
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  // Skip the saved PC
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  Offset += 2;
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  if (!TFI->hasFP(MF))
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    Offset += MF.getFrameInfo().getStackSize();
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  else
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    Offset += 2; // Skip the saved FP
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  // Fold imm into offset
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  Offset += MI.getOperand(FIOperandNum + 1).getImm();
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  if (MI.getOpcode() == MSP430::ADDframe) {
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    // This is actually "load effective address" of the stack slot
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    // instruction. We have only two-address instructions, thus we need to
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    // expand it into mov + add
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    const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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    MI.setDesc(TII.get(MSP430::MOV16rr));
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    MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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    if (Offset == 0)
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      return;
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    // We need to materialize the offset via add instruction.
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    unsigned DstReg = MI.getOperand(0).getReg();
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    if (Offset < 0)
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      BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
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        .addReg(DstReg).addImm(-Offset);
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    else
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      BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
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        .addReg(DstReg).addImm(Offset);
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    return;
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  }
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  MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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  const MSP430FrameLowering *TFI = getFrameLowering(MF);
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  return TFI->hasFP(MF) ? 
MSP430::FP0
: MSP430::SP;
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}