Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
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Source (jump to first uncovered line)
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//===-- MipsAsmBackend.cpp - Mips Asm Backend  ----------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the MipsAsmBackend class.
10
//
11
//===----------------------------------------------------------------------===//
12
//
13
14
#include "MCTargetDesc/MipsAsmBackend.h"
15
#include "MCTargetDesc/MipsABIInfo.h"
16
#include "MCTargetDesc/MipsFixupKinds.h"
17
#include "MCTargetDesc/MipsMCExpr.h"
18
#include "MCTargetDesc/MipsMCTargetDesc.h"
19
#include "llvm/ADT/STLExtras.h"
20
#include "llvm/MC/MCAsmBackend.h"
21
#include "llvm/MC/MCAssembler.h"
22
#include "llvm/MC/MCContext.h"
23
#include "llvm/MC/MCDirectives.h"
24
#include "llvm/MC/MCELFObjectWriter.h"
25
#include "llvm/MC/MCFixupKindInfo.h"
26
#include "llvm/MC/MCObjectWriter.h"
27
#include "llvm/MC/MCSubtargetInfo.h"
28
#include "llvm/MC/MCTargetOptions.h"
29
#include "llvm/MC/MCValue.h"
30
#include "llvm/Support/ErrorHandling.h"
31
#include "llvm/Support/Format.h"
32
#include "llvm/Support/MathExtras.h"
33
#include "llvm/Support/raw_ostream.h"
34
35
using namespace llvm;
36
37
// Prepare value for the target space for it
38
static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
39
12.0k
                                 MCContext &Ctx) {
40
12.0k
41
12.0k
  unsigned Kind = Fixup.getKind();
42
12.0k
43
12.0k
  // Add/subtract and shift
44
12.0k
  switch (Kind) {
45
12.0k
  default:
46
10.2k
    return 0;
47
12.0k
  case FK_Data_2:
48
379
  case Mips::fixup_Mips_LO16:
49
379
  case Mips::fixup_Mips_GPREL16:
50
379
  case Mips::fixup_Mips_GPOFF_HI:
51
379
  case Mips::fixup_Mips_GPOFF_LO:
52
379
  case Mips::fixup_Mips_GOT_PAGE:
53
379
  case Mips::fixup_Mips_GOT_OFST:
54
379
  case Mips::fixup_Mips_GOT_DISP:
55
379
  case Mips::fixup_Mips_GOT_LO16:
56
379
  case Mips::fixup_Mips_CALL_LO16:
57
379
  case Mips::fixup_MICROMIPS_GPOFF_HI:
58
379
  case Mips::fixup_MICROMIPS_GPOFF_LO:
59
379
  case Mips::fixup_MICROMIPS_LO16:
60
379
  case Mips::fixup_MICROMIPS_GOT_PAGE:
61
379
  case Mips::fixup_MICROMIPS_GOT_OFST:
62
379
  case Mips::fixup_MICROMIPS_GOT_DISP:
63
379
  case Mips::fixup_MIPS_PCLO16:
64
379
    Value &= 0xffff;
65
379
    break;
66
943
  case FK_DTPRel_4:
67
943
  case FK_DTPRel_8:
68
943
  case FK_TPRel_4:
69
943
  case FK_TPRel_8:
70
943
  case FK_GPRel_4:
71
943
  case FK_Data_4:
72
943
  case FK_Data_8:
73
943
  case Mips::fixup_Mips_SUB:
74
943
  case Mips::fixup_MICROMIPS_SUB:
75
943
    break;
76
943
  case Mips::fixup_Mips_PC16:
77
80
    // The displacement is then divided by 4 to give us an 18 bit
78
80
    // address range. Forcing a signed division because Value can be negative.
79
80
    Value = (int64_t)Value / 4;
80
80
    // We now check if Value can be encoded as a 16-bit signed immediate.
81
80
    if (!isInt<16>(Value)) {
82
2
      Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
83
2
      return 0;
84
2
    }
85
78
    break;
86
78
  case Mips::fixup_MIPS_PC19_S2:
87
19
  case Mips::fixup_MICROMIPS_PC19_S2:
88
19
    // Forcing a signed division because Value can be negative.
89
19
    Value = (int64_t)Value / 4;
90
19
    // We now check if Value can be encoded as a 19-bit signed immediate.
91
19
    if (!isInt<19>(Value)) {
92
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup");
93
0
      return 0;
94
0
    }
95
19
    break;
96
67
  case Mips::fixup_Mips_26:
97
67
    // So far we are only using this type for jumps.
98
67
    // The displacement is then divided by 4 to give us an 28 bit
99
67
    // address range.
100
67
    Value >>= 2;
101
67
    break;
102
231
  case Mips::fixup_Mips_HI16:
103
231
  case Mips::fixup_Mips_GOT:
104
231
  case Mips::fixup_MICROMIPS_GOT16:
105
231
  case Mips::fixup_Mips_GOT_HI16:
106
231
  case Mips::fixup_Mips_CALL_HI16:
107
231
  case Mips::fixup_MICROMIPS_HI16:
108
231
  case Mips::fixup_MIPS_PCHI16:
109
231
    // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
110
231
    Value = ((Value + 0x8000) >> 16) & 0xffff;
111
231
    break;
112
231
  case Mips::fixup_Mips_HIGHER:
113
13
  case Mips::fixup_MICROMIPS_HIGHER:
114
13
    // Get the 3rd 16-bits.
115
13
    Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
116
13
    break;
117
13
  case Mips::fixup_Mips_HIGHEST:
118
13
  case Mips::fixup_MICROMIPS_HIGHEST:
119
13
    // Get the 4th 16-bits.
120
13
    Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
121
13
    break;
122
25
  case Mips::fixup_MICROMIPS_26_S1:
123
25
    Value >>= 1;
124
25
    break;
125
13
  case Mips::fixup_MICROMIPS_PC7_S1:
126
4
    Value -= 4;
127
4
    // Forcing a signed division because Value can be negative.
128
4
    Value = (int64_t) Value / 2;
129
4
    // We now check if Value can be encoded as a 7-bit signed immediate.
130
4
    if (!isInt<7>(Value)) {
131
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup");
132
0
      return 0;
133
0
    }
134
4
    break;
135
4
  case Mips::fixup_MICROMIPS_PC10_S1:
136
4
    Value -= 2;
137
4
    // Forcing a signed division because Value can be negative.
138
4
    Value = (int64_t) Value / 2;
139
4
    // We now check if Value can be encoded as a 10-bit signed immediate.
140
4
    if (!isInt<10>(Value)) {
141
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup");
142
0
      return 0;
143
0
    }
144
4
    break;
145
31
  case Mips::fixup_MICROMIPS_PC16_S1:
146
31
    Value -= 4;
147
31
    // Forcing a signed division because Value can be negative.
148
31
    Value = (int64_t)Value / 2;
149
31
    // We now check if Value can be encoded as a 16-bit signed immediate.
150
31
    if (!isInt<16>(Value)) {
151
2
      Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
152
2
      return 0;
153
2
    }
154
29
    break;
155
29
  case Mips::fixup_MIPS_PC18_S3:
156
5
    // Forcing a signed division because Value can be negative.
157
5
    Value = (int64_t)Value / 8;
158
5
    // We now check if Value can be encoded as a 18-bit signed immediate.
159
5
    if (!isInt<18>(Value)) {
160
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
161
0
      return 0;
162
0
    }
163
5
    break;
164
5
  case Mips::fixup_MICROMIPS_PC18_S3:
165
0
    // Check alignment.
166
0
    if ((Value & 7)) {
167
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
168
0
    }
169
0
    // Forcing a signed division because Value can be negative.
170
0
    Value = (int64_t)Value / 8;
171
0
    // We now check if Value can be encoded as a 18-bit signed immediate.
172
0
    if (!isInt<18>(Value)) {
173
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
174
0
      return 0;
175
0
    }
176
0
    break;
177
16
  case Mips::fixup_MIPS_PC21_S2:
178
16
    // Forcing a signed division because Value can be negative.
179
16
    Value = (int64_t) Value / 4;
180
16
    // We now check if Value can be encoded as a 21-bit signed immediate.
181
16
    if (!isInt<21>(Value)) {
182
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
183
0
      return 0;
184
0
    }
185
16
    break;
186
16
  case Mips::fixup_MIPS_PC26_S2:
187
11
    // Forcing a signed division because Value can be negative.
188
11
    Value = (int64_t) Value / 4;
189
11
    // We now check if Value can be encoded as a 26-bit signed immediate.
190
11
    if (!isInt<26>(Value)) {
191
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup");
192
0
      return 0;
193
0
    }
194
11
    break;
195
11
  case Mips::fixup_MICROMIPS_PC26_S1:
196
9
    // Forcing a signed division because Value can be negative.
197
9
    Value = (int64_t)Value / 2;
198
9
    // We now check if Value can be encoded as a 26-bit signed immediate.
199
9
    if (!isInt<26>(Value)) {
200
0
      Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
201
0
      return 0;
202
0
    }
203
9
    break;
204
9
  case Mips::fixup_MICROMIPS_PC21_S1:
205
4
    // Forcing a signed division because Value can be negative.
206
4
    Value = (int64_t)Value / 2;
207
4
    // We now check if Value can be encoded as a 21-bit signed immediate.
208
4
    if (!isInt<21>(Value)) {
209
0
      Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
210
0
      return 0;
211
0
    }
212
4
    break;
213
1.85k
  }
214
1.85k
215
1.85k
  return Value;
216
1.85k
}
217
218
std::unique_ptr<MCObjectTargetWriter>
219
3.19k
MipsAsmBackend::createObjectTargetWriter() const {
220
3.19k
  return createMipsELFObjectWriter(TheTriple, IsN32);
221
3.19k
}
222
223
// Little-endian fixup data byte ordering:
224
//   mips32r2:   a | b | x | x
225
//   microMIPS:  x | x | a | b
226
227
713
static bool needsMMLEByteOrder(unsigned Kind) {
228
713
  return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
229
713
         
Kind >= Mips::fixup_MICROMIPS_26_S1709
&&
230
713
         
Kind < Mips::LastTargetFixupKind73
;
231
713
}
232
233
// Calculate index for microMIPS specific little endian byte order
234
112
static unsigned calculateMMLEIndex(unsigned i) {
235
112
  assert(i <= 3 && "Index out of range!");
236
112
237
112
  return (1 - i / 2) * 2 + i % 2;
238
112
}
239
240
/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
241
/// data fragment, at the offset specified by the fixup and following the
242
/// fixup kind as appropriate.
243
void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
244
                                const MCValue &Target,
245
                                MutableArrayRef<char> Data, uint64_t Value,
246
                                bool IsResolved,
247
12.0k
                                const MCSubtargetInfo *STI) const {
248
12.0k
  MCFixupKind Kind = Fixup.getKind();
249
12.0k
  MCContext &Ctx = Asm.getContext();
250
12.0k
  Value = adjustFixupValue(Fixup, Value, Ctx);
251
12.0k
252
12.0k
  if (!Value)
253
11.3k
    return; // Doesn't change encoding.
254
713
255
713
  // Where do we start in the object
256
713
  unsigned Offset = Fixup.getOffset();
257
713
  // Number of bytes we need to fixup
258
713
  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
259
713
  // Used to point to big endian bytes
260
713
  unsigned FullSize;
261
713
262
713
  switch ((unsigned)Kind) {
263
713
  case FK_Data_2:
264
7
  case Mips::fixup_Mips_16:
265
7
  case Mips::fixup_MICROMIPS_PC10_S1:
266
7
    FullSize = 2;
267
7
    break;
268
20
  case FK_Data_8:
269
20
  case Mips::fixup_Mips_64:
270
20
    FullSize = 8;
271
20
    break;
272
424
  case FK_Data_4:
273
686
  default:
274
686
    FullSize = 4;
275
686
    break;
276
713
  }
277
713
278
713
  // Grab current value, if any, from bits.
279
713
  uint64_t CurVal = 0;
280
713
281
713
  bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
282
713
283
3.18k
  for (unsigned i = 0; i != NumBytes; 
++i2.47k
) {
284
2.47k
    unsigned Idx = Endian == support::little
285
2.47k
                       ? 
(microMipsLEByteOrder 678
?
calculateMMLEIndex(i)56
:
i622
)
286
2.47k
                       : 
(FullSize - 1 - i)1.79k
;
287
2.47k
    CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
288
2.47k
  }
289
713
290
713
  uint64_t Mask = ((uint64_t)(-1) >>
291
713
                    (64 - getFixupKindInfo(Kind).TargetSize));
292
713
  CurVal |= Value & Mask;
293
713
294
713
  // Write out the fixed up bytes back to the code/data bits.
295
3.18k
  for (unsigned i = 0; i != NumBytes; 
++i2.47k
) {
296
2.47k
    unsigned Idx = Endian == support::little
297
2.47k
                       ? 
(microMipsLEByteOrder 678
?
calculateMMLEIndex(i)56
:
i622
)
298
2.47k
                       : 
(FullSize - 1 - i)1.79k
;
299
2.47k
    Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
300
2.47k
  }
301
713
}
302
303
164
Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
304
164
  return StringSwitch<Optional<MCFixupKind>>(Name)
305
164
      .Case("R_MIPS_NONE", FK_NONE)
306
164
      .Case("R_MIPS_32", FK_Data_4)
307
164
      .Case("R_MIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_Mips_GOT_PAGE)
308
164
      .Case("R_MIPS_CALL_HI16", (MCFixupKind)Mips::fixup_Mips_CALL_HI16)
309
164
      .Case("R_MIPS_CALL_LO16", (MCFixupKind)Mips::fixup_Mips_CALL_LO16)
310
164
      .Case("R_MIPS_CALL16", (MCFixupKind)Mips::fixup_Mips_CALL16)
311
164
      .Case("R_MIPS_GOT16", (MCFixupKind)Mips::fixup_Mips_GOT)
312
164
      .Case("R_MIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_Mips_GOT_PAGE)
313
164
      .Case("R_MIPS_GOT_OFST", (MCFixupKind)Mips::fixup_Mips_GOT_OFST)
314
164
      .Case("R_MIPS_GOT_DISP", (MCFixupKind)Mips::fixup_Mips_GOT_DISP)
315
164
      .Case("R_MIPS_GOT_HI16", (MCFixupKind)Mips::fixup_Mips_GOT_HI16)
316
164
      .Case("R_MIPS_GOT_LO16", (MCFixupKind)Mips::fixup_Mips_GOT_LO16)
317
164
      .Case("R_MIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_Mips_GOTTPREL)
318
164
      .Case("R_MIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_Mips_DTPREL_HI)
319
164
      .Case("R_MIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_Mips_DTPREL_LO)
320
164
      .Case("R_MIPS_TLS_GD", (MCFixupKind)Mips::fixup_Mips_TLSGD)
321
164
      .Case("R_MIPS_TLS_LDM", (MCFixupKind)Mips::fixup_Mips_TLSLDM)
322
164
      .Case("R_MIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_Mips_TPREL_HI)
323
164
      .Case("R_MIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_Mips_TPREL_LO)
324
164
      .Case("R_MICROMIPS_CALL16", (MCFixupKind)Mips::fixup_MICROMIPS_CALL16)
325
164
      .Case("R_MICROMIPS_GOT_DISP", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_DISP)
326
164
      .Case("R_MICROMIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_PAGE)
327
164
      .Case("R_MICROMIPS_GOT_OFST", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_OFST)
328
164
      .Case("R_MICROMIPS_GOT16", (MCFixupKind)Mips::fixup_MICROMIPS_GOT16)
329
164
      .Case("R_MICROMIPS_TLS_GOTTPREL",
330
164
            (MCFixupKind)Mips::fixup_MICROMIPS_GOTTPREL)
331
164
      .Case("R_MICROMIPS_TLS_DTPREL_HI16",
332
164
            (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_HI16)
333
164
      .Case("R_MICROMIPS_TLS_DTPREL_LO16",
334
164
            (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
335
164
      .Case("R_MICROMIPS_TLS_GD", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD)
336
164
      .Case("R_MICROMIPS_TLS_LDM", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM)
337
164
      .Case("R_MICROMIPS_TLS_TPREL_HI16",
338
164
            (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
339
164
      .Case("R_MICROMIPS_TLS_TPREL_LO16",
340
164
            (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
341
164
      .Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR)
342
164
      .Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR)
343
164
      .Default(MCAsmBackend::getFixupKind(Name));
344
164
}
345
346
const MCFixupKindInfo &MipsAsmBackend::
347
39.8k
getFixupKindInfo(MCFixupKind Kind) const {
348
39.8k
  const static MCFixupKindInfo LittleEndianInfos[] = {
349
39.8k
    // This table *must* be in same the order of fixup_* kinds in
350
39.8k
    // MipsFixupKinds.h.
351
39.8k
    //
352
39.8k
    // name                    offset  bits  flags
353
39.8k
    { "fixup_Mips_16",           0,     16,   0 },
354
39.8k
    { "fixup_Mips_32",           0,     32,   0 },
355
39.8k
    { "fixup_Mips_REL32",        0,     32,   0 },
356
39.8k
    { "fixup_Mips_26",           0,     26,   0 },
357
39.8k
    { "fixup_Mips_HI16",         0,     16,   0 },
358
39.8k
    { "fixup_Mips_LO16",         0,     16,   0 },
359
39.8k
    { "fixup_Mips_GPREL16",      0,     16,   0 },
360
39.8k
    { "fixup_Mips_LITERAL",      0,     16,   0 },
361
39.8k
    { "fixup_Mips_GOT",          0,     16,   0 },
362
39.8k
    { "fixup_Mips_PC16",         0,     16,  MCFixupKindInfo::FKF_IsPCRel },
363
39.8k
    { "fixup_Mips_CALL16",       0,     16,   0 },
364
39.8k
    { "fixup_Mips_GPREL32",      0,     32,   0 },
365
39.8k
    { "fixup_Mips_SHIFT5",       6,      5,   0 },
366
39.8k
    { "fixup_Mips_SHIFT6",       6,      5,   0 },
367
39.8k
    { "fixup_Mips_64",           0,     64,   0 },
368
39.8k
    { "fixup_Mips_TLSGD",        0,     16,   0 },
369
39.8k
    { "fixup_Mips_GOTTPREL",     0,     16,   0 },
370
39.8k
    { "fixup_Mips_TPREL_HI",     0,     16,   0 },
371
39.8k
    { "fixup_Mips_TPREL_LO",     0,     16,   0 },
372
39.8k
    { "fixup_Mips_TLSLDM",       0,     16,   0 },
373
39.8k
    { "fixup_Mips_DTPREL_HI",    0,     16,   0 },
374
39.8k
    { "fixup_Mips_DTPREL_LO",    0,     16,   0 },
375
39.8k
    { "fixup_Mips_Branch_PCRel", 0,     16,  MCFixupKindInfo::FKF_IsPCRel },
376
39.8k
    { "fixup_Mips_GPOFF_HI",     0,     16,   0 },
377
39.8k
    { "fixup_MICROMIPS_GPOFF_HI",0,     16,   0 },
378
39.8k
    { "fixup_Mips_GPOFF_LO",     0,     16,   0 },
379
39.8k
    { "fixup_MICROMIPS_GPOFF_LO",0,     16,   0 },
380
39.8k
    { "fixup_Mips_GOT_PAGE",     0,     16,   0 },
381
39.8k
    { "fixup_Mips_GOT_OFST",     0,     16,   0 },
382
39.8k
    { "fixup_Mips_GOT_DISP",     0,     16,   0 },
383
39.8k
    { "fixup_Mips_HIGHER",       0,     16,   0 },
384
39.8k
    { "fixup_MICROMIPS_HIGHER",  0,     16,   0 },
385
39.8k
    { "fixup_Mips_HIGHEST",      0,     16,   0 },
386
39.8k
    { "fixup_MICROMIPS_HIGHEST", 0,     16,   0 },
387
39.8k
    { "fixup_Mips_GOT_HI16",     0,     16,   0 },
388
39.8k
    { "fixup_Mips_GOT_LO16",     0,     16,   0 },
389
39.8k
    { "fixup_Mips_CALL_HI16",    0,     16,   0 },
390
39.8k
    { "fixup_Mips_CALL_LO16",    0,     16,   0 },
391
39.8k
    { "fixup_Mips_PC18_S3",      0,     18,  MCFixupKindInfo::FKF_IsPCRel },
392
39.8k
    { "fixup_MIPS_PC19_S2",      0,     19,  MCFixupKindInfo::FKF_IsPCRel },
393
39.8k
    { "fixup_MIPS_PC21_S2",      0,     21,  MCFixupKindInfo::FKF_IsPCRel },
394
39.8k
    { "fixup_MIPS_PC26_S2",      0,     26,  MCFixupKindInfo::FKF_IsPCRel },
395
39.8k
    { "fixup_MIPS_PCHI16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
396
39.8k
    { "fixup_MIPS_PCLO16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
397
39.8k
    { "fixup_MICROMIPS_26_S1",   0,     26,   0 },
398
39.8k
    { "fixup_MICROMIPS_HI16",    0,     16,   0 },
399
39.8k
    { "fixup_MICROMIPS_LO16",    0,     16,   0 },
400
39.8k
    { "fixup_MICROMIPS_GOT16",   0,     16,   0 },
401
39.8k
    { "fixup_MICROMIPS_PC7_S1",  0,      7,   MCFixupKindInfo::FKF_IsPCRel },
402
39.8k
    { "fixup_MICROMIPS_PC10_S1", 0,     10,   MCFixupKindInfo::FKF_IsPCRel },
403
39.8k
    { "fixup_MICROMIPS_PC16_S1", 0,     16,   MCFixupKindInfo::FKF_IsPCRel },
404
39.8k
    { "fixup_MICROMIPS_PC26_S1", 0,     26,   MCFixupKindInfo::FKF_IsPCRel },
405
39.8k
    { "fixup_MICROMIPS_PC19_S2", 0,     19,   MCFixupKindInfo::FKF_IsPCRel },
406
39.8k
    { "fixup_MICROMIPS_PC18_S3", 0,     18,   MCFixupKindInfo::FKF_IsPCRel },
407
39.8k
    { "fixup_MICROMIPS_PC21_S1", 0,     21,   MCFixupKindInfo::FKF_IsPCRel },
408
39.8k
    { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
409
39.8k
    { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
410
39.8k
    { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
411
39.8k
    { "fixup_MICROMIPS_GOT_OFST",        0,     16,   0 },
412
39.8k
    { "fixup_MICROMIPS_TLS_GD",          0,     16,   0 },
413
39.8k
    { "fixup_MICROMIPS_TLS_LDM",         0,     16,   0 },
414
39.8k
    { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0,     16,   0 },
415
39.8k
    { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0,     16,   0 },
416
39.8k
    { "fixup_MICROMIPS_GOTTPREL",        0,     16,   0 },
417
39.8k
    { "fixup_MICROMIPS_TLS_TPREL_HI16",  0,     16,   0 },
418
39.8k
    { "fixup_MICROMIPS_TLS_TPREL_LO16",  0,     16,   0 },
419
39.8k
    { "fixup_Mips_SUB",                  0,     64,   0 },
420
39.8k
    { "fixup_MICROMIPS_SUB",             0,     64,   0 },
421
39.8k
    { "fixup_Mips_JALR",                 0,     32,   0 },
422
39.8k
    { "fixup_MICROMIPS_JALR",            0,     32,   0 }
423
39.8k
  };
424
39.8k
  static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds,
425
39.8k
                "Not all MIPS little endian fixup kinds added!");
426
39.8k
427
39.8k
  const static MCFixupKindInfo BigEndianInfos[] = {
428
39.8k
    // This table *must* be in same the order of fixup_* kinds in
429
39.8k
    // MipsFixupKinds.h.
430
39.8k
    //
431
39.8k
    // name                    offset  bits  flags
432
39.8k
    { "fixup_Mips_16",          16,     16,   0 },
433
39.8k
    { "fixup_Mips_32",           0,     32,   0 },
434
39.8k
    { "fixup_Mips_REL32",        0,     32,   0 },
435
39.8k
    { "fixup_Mips_26",           6,     26,   0 },
436
39.8k
    { "fixup_Mips_HI16",        16,     16,   0 },
437
39.8k
    { "fixup_Mips_LO16",        16,     16,   0 },
438
39.8k
    { "fixup_Mips_GPREL16",     16,     16,   0 },
439
39.8k
    { "fixup_Mips_LITERAL",     16,     16,   0 },
440
39.8k
    { "fixup_Mips_GOT",         16,     16,   0 },
441
39.8k
    { "fixup_Mips_PC16",        16,     16,  MCFixupKindInfo::FKF_IsPCRel },
442
39.8k
    { "fixup_Mips_CALL16",      16,     16,   0 },
443
39.8k
    { "fixup_Mips_GPREL32",      0,     32,   0 },
444
39.8k
    { "fixup_Mips_SHIFT5",      21,      5,   0 },
445
39.8k
    { "fixup_Mips_SHIFT6",      21,      5,   0 },
446
39.8k
    { "fixup_Mips_64",           0,     64,   0 },
447
39.8k
    { "fixup_Mips_TLSGD",       16,     16,   0 },
448
39.8k
    { "fixup_Mips_GOTTPREL",    16,     16,   0 },
449
39.8k
    { "fixup_Mips_TPREL_HI",    16,     16,   0 },
450
39.8k
    { "fixup_Mips_TPREL_LO",    16,     16,   0 },
451
39.8k
    { "fixup_Mips_TLSLDM",      16,     16,   0 },
452
39.8k
    { "fixup_Mips_DTPREL_HI",   16,     16,   0 },
453
39.8k
    { "fixup_Mips_DTPREL_LO",   16,     16,   0 },
454
39.8k
    { "fixup_Mips_Branch_PCRel",16,     16,  MCFixupKindInfo::FKF_IsPCRel },
455
39.8k
    { "fixup_Mips_GPOFF_HI",    16,     16,   0 },
456
39.8k
    { "fixup_MICROMIPS_GPOFF_HI", 16,     16,   0 },
457
39.8k
    { "fixup_Mips_GPOFF_LO",    16,     16,   0 },
458
39.8k
    { "fixup_MICROMIPS_GPOFF_LO", 16,     16,   0 },
459
39.8k
    { "fixup_Mips_GOT_PAGE",    16,     16,   0 },
460
39.8k
    { "fixup_Mips_GOT_OFST",    16,     16,   0 },
461
39.8k
    { "fixup_Mips_GOT_DISP",    16,     16,   0 },
462
39.8k
    { "fixup_Mips_HIGHER",      16,     16,   0 },
463
39.8k
    { "fixup_MICROMIPS_HIGHER", 16,     16,   0 },
464
39.8k
    { "fixup_Mips_HIGHEST",     16,     16,   0 },
465
39.8k
    { "fixup_MICROMIPS_HIGHEST",16,     16,   0 },
466
39.8k
    { "fixup_Mips_GOT_HI16",    16,     16,   0 },
467
39.8k
    { "fixup_Mips_GOT_LO16",    16,     16,   0 },
468
39.8k
    { "fixup_Mips_CALL_HI16",   16,     16,   0 },
469
39.8k
    { "fixup_Mips_CALL_LO16",   16,     16,   0 },
470
39.8k
    { "fixup_Mips_PC18_S3",     14,     18,  MCFixupKindInfo::FKF_IsPCRel },
471
39.8k
    { "fixup_MIPS_PC19_S2",     13,     19,  MCFixupKindInfo::FKF_IsPCRel },
472
39.8k
    { "fixup_MIPS_PC21_S2",     11,     21,  MCFixupKindInfo::FKF_IsPCRel },
473
39.8k
    { "fixup_MIPS_PC26_S2",      6,     26,  MCFixupKindInfo::FKF_IsPCRel },
474
39.8k
    { "fixup_MIPS_PCHI16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
475
39.8k
    { "fixup_MIPS_PCLO16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
476
39.8k
    { "fixup_MICROMIPS_26_S1",   6,     26,   0 },
477
39.8k
    { "fixup_MICROMIPS_HI16",   16,     16,   0 },
478
39.8k
    { "fixup_MICROMIPS_LO16",   16,     16,   0 },
479
39.8k
    { "fixup_MICROMIPS_GOT16",  16,     16,   0 },
480
39.8k
    { "fixup_MICROMIPS_PC7_S1",  9,      7,   MCFixupKindInfo::FKF_IsPCRel },
481
39.8k
    { "fixup_MICROMIPS_PC10_S1", 6,     10,   MCFixupKindInfo::FKF_IsPCRel },
482
39.8k
    { "fixup_MICROMIPS_PC16_S1",16,     16,   MCFixupKindInfo::FKF_IsPCRel },
483
39.8k
    { "fixup_MICROMIPS_PC26_S1", 6,     26,   MCFixupKindInfo::FKF_IsPCRel },
484
39.8k
    { "fixup_MICROMIPS_PC19_S2",13,     19,   MCFixupKindInfo::FKF_IsPCRel },
485
39.8k
    { "fixup_MICROMIPS_PC18_S3",14,     18,   MCFixupKindInfo::FKF_IsPCRel },
486
39.8k
    { "fixup_MICROMIPS_PC21_S1",11,     21,   MCFixupKindInfo::FKF_IsPCRel },
487
39.8k
    { "fixup_MICROMIPS_CALL16", 16,     16,   0 },
488
39.8k
    { "fixup_MICROMIPS_GOT_DISP",        16,     16,   0 },
489
39.8k
    { "fixup_MICROMIPS_GOT_PAGE",        16,     16,   0 },
490
39.8k
    { "fixup_MICROMIPS_GOT_OFST",        16,     16,   0 },
491
39.8k
    { "fixup_MICROMIPS_TLS_GD",          16,     16,   0 },
492
39.8k
    { "fixup_MICROMIPS_TLS_LDM",         16,     16,   0 },
493
39.8k
    { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16,     16,   0 },
494
39.8k
    { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16,     16,   0 },
495
39.8k
    { "fixup_MICROMIPS_GOTTPREL",        16,     16,   0 },
496
39.8k
    { "fixup_MICROMIPS_TLS_TPREL_HI16",  16,     16,   0 },
497
39.8k
    { "fixup_MICROMIPS_TLS_TPREL_LO16",  16,     16,   0 },
498
39.8k
    { "fixup_Mips_SUB",                   0,     64,   0 },
499
39.8k
    { "fixup_MICROMIPS_SUB",              0,     64,   0 },
500
39.8k
    { "fixup_Mips_JALR",                  0,     32,   0 },
501
39.8k
    { "fixup_MICROMIPS_JALR",             0,     32,   0 }
502
39.8k
  };
503
39.8k
  static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds,
504
39.8k
                "Not all MIPS big endian fixup kinds added!");
505
39.8k
506
39.8k
  if (Kind < FirstTargetFixupKind)
507
3.42k
    return MCAsmBackend::getFixupKindInfo(Kind);
508
36.4k
509
36.4k
  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
510
36.4k
          "Invalid kind!");
511
36.4k
512
36.4k
  if (Endian == support::little)
513
2.11k
    return LittleEndianInfos[Kind - FirstTargetFixupKind];
514
34.2k
  return BigEndianInfos[Kind - FirstTargetFixupKind];
515
34.2k
}
516
517
/// WriteNopData - Write an (optimal) nop sequence of Count bytes
518
/// to the given output. If the target cannot generate such a sequence,
519
/// it should return an error.
520
///
521
/// \return - True on success.
522
750
bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
523
750
  // Check for a less than instruction size number of bytes
524
750
  // FIXME: 16 bit instructions are not handled yet here.
525
750
  // We shouldn't be using a hard coded number for instruction size.
526
750
527
750
  // If the count is not 4-byte aligned, we must be writing data into the text
528
750
  // section (otherwise we have unaligned instructions, and thus have far
529
750
  // bigger problems), so just write zeros instead.
530
750
  OS.write_zeros(Count);
531
750
  return true;
532
750
}
533
534
bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
535
                                           const MCFixup &Fixup,
536
589
                                           const MCValue &Target) {
537
589
  const unsigned FixupKind = Fixup.getKind();
538
589
  switch (FixupKind) {
539
589
  default:
540
499
    return false;
541
589
  // All these relocations require special processing
542
589
  // at linking time. Delegate this work to a linker.
543
589
  case Mips::fixup_Mips_CALL_HI16:
544
90
  case Mips::fixup_Mips_CALL_LO16:
545
90
  case Mips::fixup_Mips_CALL16:
546
90
  case Mips::fixup_Mips_GOT:
547
90
  case Mips::fixup_Mips_GOT_PAGE:
548
90
  case Mips::fixup_Mips_GOT_OFST:
549
90
  case Mips::fixup_Mips_GOT_DISP:
550
90
  case Mips::fixup_Mips_GOT_HI16:
551
90
  case Mips::fixup_Mips_GOT_LO16:
552
90
  case Mips::fixup_Mips_GOTTPREL:
553
90
  case Mips::fixup_Mips_DTPREL_HI:
554
90
  case Mips::fixup_Mips_DTPREL_LO:
555
90
  case Mips::fixup_Mips_TLSGD:
556
90
  case Mips::fixup_Mips_TLSLDM:
557
90
  case Mips::fixup_Mips_TPREL_HI:
558
90
  case Mips::fixup_Mips_TPREL_LO:
559
90
  case Mips::fixup_Mips_JALR:
560
90
  case Mips::fixup_MICROMIPS_CALL16:
561
90
  case Mips::fixup_MICROMIPS_GOT_DISP:
562
90
  case Mips::fixup_MICROMIPS_GOT_PAGE:
563
90
  case Mips::fixup_MICROMIPS_GOT_OFST:
564
90
  case Mips::fixup_MICROMIPS_GOT16:
565
90
  case Mips::fixup_MICROMIPS_GOTTPREL:
566
90
  case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16:
567
90
  case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16:
568
90
  case Mips::fixup_MICROMIPS_TLS_GD:
569
90
  case Mips::fixup_MICROMIPS_TLS_LDM:
570
90
  case Mips::fixup_MICROMIPS_TLS_TPREL_HI16:
571
90
  case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
572
90
  case Mips::fixup_MICROMIPS_JALR:
573
90
    return true;
574
589
  }
575
589
}
576
577
947
bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const {
578
947
  if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) {
579
947
    if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS)
580
64
      return true;
581
883
  }
582
883
  return false;
583
883
}
584
585
MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
586
                                         const MCSubtargetInfo &STI,
587
                                         const MCRegisterInfo &MRI,
588
3.19k
                                         const MCTargetOptions &Options) {
589
3.19k
  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options);
590
3.19k
  return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), ABI.IsN32());
591
3.19k
}