Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
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1
//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
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//===----------------------------------------------------------------------===//
8
//
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// This class prints an Mips MCInst to a .s file.
10
//
11
//===----------------------------------------------------------------------===//
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13
#include "MipsInstPrinter.h"
14
#include "MipsInstrInfo.h"
15
#include "MipsMCExpr.h"
16
#include "llvm/ADT/StringExtras.h"
17
#include "llvm/MC/MCExpr.h"
18
#include "llvm/MC/MCInst.h"
19
#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSymbol.h"
21
#include "llvm/Support/ErrorHandling.h"
22
#include "llvm/Support/raw_ostream.h"
23
using namespace llvm;
24
25
#define DEBUG_TYPE "asm-printer"
26
27
#define PRINT_ALIAS_INSTR
28
#include "MipsGenAsmWriter.inc"
29
30
template<unsigned R>
31
5.38k
static bool isReg(const MCInst &MI, unsigned OpNo) {
32
5.38k
  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
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5.38k
  return MI.getOperand(OpNo).getReg() == R;
34
5.38k
}
MipsInstPrinter.cpp:bool isReg<21u>(llvm::MCInst const&, unsigned int)
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31
3.96k
static bool isReg(const MCInst &MI, unsigned OpNo) {
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3.96k
  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
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3.96k
  return MI.getOperand(OpNo).getReg() == R;
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3.96k
}
MipsInstPrinter.cpp:bool isReg<379u>(llvm::MCInst const&, unsigned int)
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Source
31
140
static bool isReg(const MCInst &MI, unsigned OpNo) {
32
140
  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33
140
  return MI.getOperand(OpNo).getReg() == R;
34
140
}
MipsInstPrinter.cpp:bool isReg<179u>(llvm::MCInst const&, unsigned int)
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Source
31
100
static bool isReg(const MCInst &MI, unsigned OpNo) {
32
100
  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33
100
  return MI.getOperand(OpNo).getReg() == R;
34
100
}
MipsInstPrinter.cpp:bool isReg<19u>(llvm::MCInst const&, unsigned int)
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Source
31
1.18k
static bool isReg(const MCInst &MI, unsigned OpNo) {
32
1.18k
  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33
1.18k
  return MI.getOperand(OpNo).getReg() == R;
34
1.18k
}
Unexecuted instantiation: MipsInstPrinter.cpp:bool isReg<325u>(llvm::MCInst const&, unsigned int)
35
36
506
const char* Mips::MipsFCCToString(Mips::CondCode CC) {
37
506
  switch (CC) {
38
506
  case FCOND_F:
39
0
  case FCOND_T:   return "f";
40
47
  case FCOND_UN:
41
47
  case FCOND_OR:  return "un";
42
86
  case FCOND_OEQ:
43
86
  case FCOND_UNE: return "eq";
44
86
  case FCOND_UEQ:
45
58
  case FCOND_ONE: return "ueq";
46
92
  case FCOND_OLT:
47
92
  case FCOND_UGE: return "olt";
48
92
  case FCOND_ULT:
49
56
  case FCOND_OGE: return "ult";
50
76
  case FCOND_OLE:
51
76
  case FCOND_UGT: return "ole";
52
91
  case FCOND_ULE:
53
91
  case FCOND_OGT: return "ule";
54
91
  case FCOND_SF:
55
0
  case FCOND_ST:  return "sf";
56
0
  case FCOND_NGLE:
57
0
  case FCOND_GLE: return "ngle";
58
0
  case FCOND_SEQ:
59
0
  case FCOND_SNE: return "seq";
60
0
  case FCOND_NGL:
61
0
  case FCOND_GL:  return "ngl";
62
0
  case FCOND_LT:
63
0
  case FCOND_NLT: return "lt";
64
0
  case FCOND_NGE:
65
0
  case FCOND_GE:  return "nge";
66
0
  case FCOND_LE:
67
0
  case FCOND_NLE: return "le";
68
0
  case FCOND_NGT:
69
0
  case FCOND_GT:  return "ngt";
70
0
  }
71
0
  llvm_unreachable("Impossible condition code!");
72
0
}
73
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300k
void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
75
300k
  OS << '$' << StringRef(getRegisterName(RegNo)).lower();
76
300k
}
77
78
void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
79
165k
                                StringRef Annot, const MCSubtargetInfo &STI) {
80
165k
  switch (MI->getOpcode()) {
81
165k
  default:
82
164k
    break;
83
165k
  case Mips::RDHWR:
84
97
  case Mips::RDHWR64:
85
97
    O << "\t.set\tpush\n";
86
97
    O << "\t.set\tmips32r2\n";
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97
    break;
88
175
  case Mips::Save16:
89
175
    O << "\tsave\t";
90
175
    printSaveRestore(MI, O);
91
175
    O << " # 16 bit inst\n";
92
175
    return;
93
97
  case Mips::SaveX16:
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72
    O << "\tsave\t";
95
72
    printSaveRestore(MI, O);
96
72
    O << "\n";
97
72
    return;
98
180
  case Mips::Restore16:
99
180
    O << "\trestore\t";
100
180
    printSaveRestore(MI, O);
101
180
    O << " # 16 bit inst\n";
102
180
    return;
103
97
  case Mips::RestoreX16:
104
72
    O << "\trestore\t";
105
72
    printSaveRestore(MI, O);
106
72
    O << "\n";
107
72
    return;
108
164k
  }
109
164k
110
164k
  // Try to print any aliases first.
111
164k
  if (!printAliasInstr(MI, O) && 
!printAlias(*MI, O)150k
)
112
147k
    printInstruction(MI, O);
113
164k
  printAnnotation(O, Annot);
114
164k
115
164k
  switch (MI->getOpcode()) {
116
164k
  default:
117
164k
    break;
118
164k
  case Mips::RDHWR:
119
97
  case Mips::RDHWR64:
120
97
    O << "\n\t.set\tpop";
121
164k
  }
122
164k
}
123
124
void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
125
379k
                                   raw_ostream &O) {
126
379k
  const MCOperand &Op = MI->getOperand(OpNo);
127
379k
  if (Op.isReg()) {
128
298k
    printRegName(O, Op.getReg());
129
298k
    return;
130
298k
  }
131
80.4k
132
80.4k
  if (Op.isImm()) {
133
51.3k
    O << formatImm(Op.getImm());
134
51.3k
    return;
135
51.3k
  }
136
29.0k
137
29.0k
  assert(Op.isExpr() && "unknown operand kind in printOperand");
138
29.0k
  Op.getExpr()->print(O, &MAI, true);
139
29.0k
}
140
141
template <unsigned Bits, unsigned Offset>
142
27.7k
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
27.7k
  const MCOperand &MO = MI->getOperand(opNum);
144
27.7k
  if (MO.isImm()) {
145
20.3k
    uint64_t Imm = MO.getImm();
146
20.3k
    Imm -= Offset;
147
20.3k
    Imm &= (1 << Bits) - 1;
148
20.3k
    Imm += Offset;
149
20.3k
    O << formatImm(Imm);
150
20.3k
    return;
151
20.3k
  }
152
7.44k
153
7.44k
  printOperand(MI, opNum, O);
154
7.44k
}
void llvm::MipsInstPrinter::printUImm<10u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
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Source
142
971
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
971
  const MCOperand &MO = MI->getOperand(opNum);
144
971
  if (MO.isImm()) {
145
971
    uint64_t Imm = MO.getImm();
146
971
    Imm -= Offset;
147
971
    Imm &= (1 << Bits) - 1;
148
971
    Imm += Offset;
149
971
    O << formatImm(Imm);
150
971
    return;
151
971
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<4u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
362
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
362
  const MCOperand &MO = MI->getOperand(opNum);
144
362
  if (MO.isImm()) {
145
362
    uint64_t Imm = MO.getImm();
146
362
    Imm -= Offset;
147
362
    Imm &= (1 << Bits) - 1;
148
362
    Imm += Offset;
149
362
    O << formatImm(Imm);
150
362
    return;
151
362
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<5u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
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Count
Source
142
5.14k
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
5.14k
  const MCOperand &MO = MI->getOperand(opNum);
144
5.14k
  if (MO.isImm()) {
145
5.14k
    uint64_t Imm = MO.getImm();
146
5.14k
    Imm -= Offset;
147
5.14k
    Imm &= (1 << Bits) - 1;
148
5.14k
    Imm += Offset;
149
5.14k
    O << formatImm(Imm);
150
5.14k
    return;
151
5.14k
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<26u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
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Count
Source
142
417
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
417
  const MCOperand &MO = MI->getOperand(opNum);
144
417
  if (MO.isImm()) {
145
0
    uint64_t Imm = MO.getImm();
146
0
    Imm -= Offset;
147
0
    Imm &= (1 << Bits) - 1;
148
0
    Imm += Offset;
149
0
    O << formatImm(Imm);
150
0
    return;
151
0
  }
152
417
153
417
  printOperand(MI, opNum, O);
154
417
}
void llvm::MipsInstPrinter::printUImm<20u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
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Count
Source
142
59
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
59
  const MCOperand &MO = MI->getOperand(opNum);
144
59
  if (MO.isImm()) {
145
59
    uint64_t Imm = MO.getImm();
146
59
    Imm -= Offset;
147
59
    Imm &= (1 << Bits) - 1;
148
59
    Imm += Offset;
149
59
    O << formatImm(Imm);
150
59
    return;
151
59
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<16u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
14.8k
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
14.8k
  const MCOperand &MO = MI->getOperand(opNum);
144
14.8k
  if (MO.isImm()) {
145
7.87k
    uint64_t Imm = MO.getImm();
146
7.87k
    Imm -= Offset;
147
7.87k
    Imm &= (1 << Bits) - 1;
148
7.87k
    Imm += Offset;
149
7.87k
    O << formatImm(Imm);
150
7.87k
    return;
151
7.87k
  }
152
7.02k
153
7.02k
  printOperand(MI, opNum, O);
154
7.02k
}
void llvm::MipsInstPrinter::printUImm<2u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
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Count
Source
142
883
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
883
  const MCOperand &MO = MI->getOperand(opNum);
144
883
  if (MO.isImm()) {
145
883
    uint64_t Imm = MO.getImm();
146
883
    Imm -= Offset;
147
883
    Imm &= (1 << Bits) - 1;
148
883
    Imm += Offset;
149
883
    O << formatImm(Imm);
150
883
    return;
151
883
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<1u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
609
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
609
  const MCOperand &MO = MI->getOperand(opNum);
144
609
  if (MO.isImm()) {
145
609
    uint64_t Imm = MO.getImm();
146
609
    Imm -= Offset;
147
609
    Imm &= (1 << Bits) - 1;
148
609
    Imm += Offset;
149
609
    O << formatImm(Imm);
150
609
    return;
151
609
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<3u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
1.01k
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
1.01k
  const MCOperand &MO = MI->getOperand(opNum);
144
1.01k
  if (MO.isImm()) {
145
1.01k
    uint64_t Imm = MO.getImm();
146
1.01k
    Imm -= Offset;
147
1.01k
    Imm &= (1 << Bits) - 1;
148
1.01k
    Imm += Offset;
149
1.01k
    O << formatImm(Imm);
150
1.01k
    return;
151
1.01k
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<0u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
52
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
52
  const MCOperand &MO = MI->getOperand(opNum);
144
52
  if (MO.isImm()) {
145
52
    uint64_t Imm = MO.getImm();
146
52
    Imm -= Offset;
147
52
    Imm &= (1 << Bits) - 1;
148
52
    Imm += Offset;
149
52
    O << formatImm(Imm);
150
52
    return;
151
52
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<7u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
6
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
6
  const MCOperand &MO = MI->getOperand(opNum);
144
6
  if (MO.isImm()) {
145
6
    uint64_t Imm = MO.getImm();
146
6
    Imm -= Offset;
147
6
    Imm &= (1 << Bits) - 1;
148
6
    Imm += Offset;
149
6
    O << formatImm(Imm);
150
6
    return;
151
6
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<8u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
197
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
197
  const MCOperand &MO = MI->getOperand(opNum);
144
197
  if (MO.isImm()) {
145
197
    uint64_t Imm = MO.getImm();
146
197
    Imm -= Offset;
147
197
    Imm &= (1 << Bits) - 1;
148
197
    Imm += Offset;
149
197
    O << formatImm(Imm);
150
197
    return;
151
197
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<2u, 1u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
43
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
43
  const MCOperand &MO = MI->getOperand(opNum);
144
43
  if (MO.isImm()) {
145
43
    uint64_t Imm = MO.getImm();
146
43
    Imm -= Offset;
147
43
    Imm &= (1 << Bits) - 1;
148
43
    Imm += Offset;
149
43
    O << formatImm(Imm);
150
43
    return;
151
43
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<6u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
2.93k
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
2.93k
  const MCOperand &MO = MI->getOperand(opNum);
144
2.93k
  if (MO.isImm()) {
145
2.93k
    uint64_t Imm = MO.getImm();
146
2.93k
    Imm -= Offset;
147
2.93k
    Imm &= (1 << Bits) - 1;
148
2.93k
    Imm += Offset;
149
2.93k
    O << formatImm(Imm);
150
2.93k
    return;
151
2.93k
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<5u, 32u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
39
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
39
  const MCOperand &MO = MI->getOperand(opNum);
144
39
  if (MO.isImm()) {
145
39
    uint64_t Imm = MO.getImm();
146
39
    Imm -= Offset;
147
39
    Imm &= (1 << Bits) - 1;
148
39
    Imm += Offset;
149
39
    O << formatImm(Imm);
150
39
    return;
151
39
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<5u, 1u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
76
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
76
  const MCOperand &MO = MI->getOperand(opNum);
144
76
  if (MO.isImm()) {
145
76
    uint64_t Imm = MO.getImm();
146
76
    Imm -= Offset;
147
76
    Imm &= (1 << Bits) - 1;
148
76
    Imm += Offset;
149
76
    O << formatImm(Imm);
150
76
    return;
151
76
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<6u, 1u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
43
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
43
  const MCOperand &MO = MI->getOperand(opNum);
144
43
  if (MO.isImm()) {
145
43
    uint64_t Imm = MO.getImm();
146
43
    Imm -= Offset;
147
43
    Imm &= (1 << Bits) - 1;
148
43
    Imm += Offset;
149
43
    O << formatImm(Imm);
150
43
    return;
151
43
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<5u, 33u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
9
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
9
  const MCOperand &MO = MI->getOperand(opNum);
144
9
  if (MO.isImm()) {
145
9
    uint64_t Imm = MO.getImm();
146
9
    Imm -= Offset;
147
9
    Imm &= (1 << Bits) - 1;
148
9
    Imm += Offset;
149
9
    O << formatImm(Imm);
150
9
    return;
151
9
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
void llvm::MipsInstPrinter::printUImm<6u, 2u>(llvm::MCInst const*, int, llvm::raw_ostream&)
Line
Count
Source
142
10
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143
10
  const MCOperand &MO = MI->getOperand(opNum);
144
10
  if (MO.isImm()) {
145
10
    uint64_t Imm = MO.getImm();
146
10
    Imm -= Offset;
147
10
    Imm &= (1 << Bits) - 1;
148
10
    Imm += Offset;
149
10
    O << formatImm(Imm);
150
10
    return;
151
10
  }
152
0
153
0
  printOperand(MI, opNum, O);
154
0
}
155
156
void MipsInstPrinter::
157
44.6k
printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
158
44.6k
  // Load/Store memory operands -- imm($reg)
159
44.6k
  // If PIC target the target is loaded as the
160
44.6k
  // pattern lw $25,%call16($28)
161
44.6k
162
44.6k
  // opNum can be invalid if instruction had reglist as operand.
163
44.6k
  // MemOperand is always last operand of instruction (base + offset).
164
44.6k
  switch (MI->getOpcode()) {
165
44.6k
  default:
166
44.5k
    break;
167
44.6k
  case Mips::SWM32_MM:
168
78
  case Mips::LWM32_MM:
169
78
  case Mips::SWM16_MM:
170
78
  case Mips::SWM16_MMR6:
171
78
  case Mips::LWM16_MM:
172
78
  case Mips::LWM16_MMR6:
173
78
    opNum = MI->getNumOperands() - 2;
174
78
    break;
175
44.6k
  }
176
44.6k
177
44.6k
  printOperand(MI, opNum+1, O);
178
44.6k
  O << "(";
179
44.6k
  printOperand(MI, opNum, O);
180
44.6k
  O << ")";
181
44.6k
}
182
183
void MipsInstPrinter::
184
243
printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
185
243
  // when using stack locations for not load/store instructions
186
243
  // print the same way as all normal 3 operand instructions.
187
243
  printOperand(MI, opNum, O);
188
243
  O << ", ";
189
243
  printOperand(MI, opNum+1, O);
190
243
}
191
192
void MipsInstPrinter::
193
506
printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
194
506
  const MCOperand& MO = MI->getOperand(opNum);
195
506
  O << MipsFCCToString((Mips::CondCode)MO.getImm());
196
506
}
197
198
void MipsInstPrinter::
199
0
printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
200
0
  llvm_unreachable("TODO");
201
0
}
202
203
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
204
2.71k
                                 unsigned OpNo, raw_ostream &OS) {
205
2.71k
  OS << "\t" << Str << "\t";
206
2.71k
  printOperand(&MI, OpNo, OS);
207
2.71k
  return true;
208
2.71k
}
209
210
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
211
                                 unsigned OpNo0, unsigned OpNo1,
212
1.27k
                                 raw_ostream &OS) {
213
1.27k
  printAlias(Str, MI, OpNo0, OS);
214
1.27k
  OS << ", ";
215
1.27k
  printOperand(&MI, OpNo1, OS);
216
1.27k
  return true;
217
1.27k
}
218
219
150k
bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
220
150k
  switch (MI.getOpcode()) {
221
150k
  case Mips::BEQ:
222
782
  case Mips::BEQ_MM:
223
782
    // beq $zero, $zero, $L2 => b $L2
224
782
    // beq $r0, $zero, $L2 => beqz $r0, $L2
225
782
    return (isReg<Mips::ZERO>(MI, 0) && 
isReg<Mips::ZERO>(MI, 1)298
&&
226
782
            
printAlias("b", MI, 2, OS)286
) ||
227
782
           
(496
isReg<Mips::ZERO>(MI, 1)496
&&
printAlias("beqz", MI, 0, 2, OS)395
);
228
782
  case Mips::BEQ64:
229
64
    // beq $r0, $zero, $L2 => beqz $r0, $L2
230
64
    return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
231
782
  case Mips::BNE:
232
700
  case Mips::BNE_MM:
233
700
    // bne $r0, $zero, $L2 => bnez $r0, $L2
234
700
    return isReg<Mips::ZERO>(MI, 1) && 
printAlias("bnez", MI, 0, 2, OS)495
;
235
700
  case Mips::BNE64:
236
10
    // bne $r0, $zero, $L2 => bnez $r0, $L2
237
10
    return isReg<Mips::ZERO_64>(MI, 1) && 
printAlias("bnez", MI, 0, 2, OS)2
;
238
700
  case Mips::BGEZAL:
239
64
    // bgezal $zero, $L1 => bal $L1
240
64
    return isReg<Mips::ZERO>(MI, 0) && 
printAlias("bal", MI, 1, OS)0
;
241
700
  case Mips::BC1T:
242
50
    // bc1t $fcc0, $L1 => bc1t $L1
243
50
    return isReg<Mips::FCC0>(MI, 0) && 
printAlias("bc1t", MI, 1, OS)0
;
244
700
  case Mips::BC1F:
245
50
    // bc1f $fcc0, $L1 => bc1f $L1
246
50
    return isReg<Mips::FCC0>(MI, 0) && 
printAlias("bc1f", MI, 1, OS)0
;
247
1.18k
  case Mips::JALR:
248
1.18k
    // jalr $ra, $r1 => jalr $r1
249
1.18k
    return isReg<Mips::RA>(MI, 0) && 
printAlias("jalr", MI, 1, OS)1.14k
;
250
700
  case Mips::JALR64:
251
0
    // jalr $ra, $r1 => jalr $r1
252
0
    return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
253
700
  case Mips::NOR:
254
646
  case Mips::NOR_MM:
255
646
  case Mips::NOR_MMR6:
256
646
    // nor $r0, $r1, $zero => not $r0, $r1
257
646
    return isReg<Mips::ZERO>(MI, 2) && 
printAlias("not", MI, 0, 1, OS)314
;
258
646
  case Mips::NOR64:
259
66
    // nor $r0, $r1, $zero => not $r0, $r1
260
66
    return isReg<Mips::ZERO_64>(MI, 2) && 
printAlias("not", MI, 0, 1, OS)0
;
261
975
  case Mips::OR:
262
975
    // or $r0, $r1, $zero => move $r0, $r1
263
975
    return isReg<Mips::ZERO>(MI, 2) && 
printAlias("move", MI, 0, 1, OS)8
;
264
145k
  default: return false;
265
150k
  }
266
150k
}
267
268
499
void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
269
2.03k
  for (unsigned i = 0, e = MI->getNumOperands(); i != e; 
++i1.53k
) {
270
1.53k
    if (i != 0) 
O << ", "1.03k
;
271
1.53k
    if (MI->getOperand(i).isReg())
272
1.03k
      printRegName(O, MI->getOperand(i).getReg());
273
499
    else
274
499
      printUImm<16>(MI, i, O);
275
1.53k
  }
276
499
}
277
278
void MipsInstPrinter::
279
78
printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
280
78
  // - 2 because register List is always first operand of instruction and it is
281
78
  // always followed by memory operand (base + offset).
282
384
  for (int i = opNum, e = MI->getNumOperands() - 2; i != e; 
++i306
) {
283
306
    if (i != opNum)
284
228
      O << ", ";
285
306
    printRegName(O, MI->getOperand(i).getReg());
286
306
  }
287
78
}