Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
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//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Mips specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMCTargetDesc.h"
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#include "MipsAsmBackend.h"
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#include "MipsELFStreamer.h"
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#include "MipsInstPrinter.h"
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#include "MipsMCAsmInfo.h"
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#include "MipsMCNaCl.h"
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#include "MipsTargetStreamer.h"
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#include "TargetInfo/MipsTargetInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "MipsGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "MipsGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "MipsGenRegisterInfo.inc"
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/// Select the Mips CPU for the given triple and cpu name.
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/// FIXME: Merge with the copy in MipsSubtarget.cpp
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StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
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  if (CPU.empty() || 
CPU == "generic"10.2k
) {
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    if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) {
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      if (TT.isMIPS32())
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        CPU = "mips32r6";
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      else
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        CPU = "mips64r6";
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    } else {
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      if (TT.isMIPS32())
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        CPU = "mips32";
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      else
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        CPU = "mips64";
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    }
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  }
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  return CPU;
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}
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static MCInstrInfo *createMipsMCInstrInfo() {
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  MCInstrInfo *X = new MCInstrInfo();
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  InitMipsMCInstrInfo(X);
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  return X;
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}
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static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
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  MCRegisterInfo *X = new MCRegisterInfo();
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  InitMipsMCRegisterInfo(X, Mips::RA);
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  return X;
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}
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static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
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                                                  StringRef CPU, StringRef FS) {
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  CPU = MIPS_MC::selectMipsCPU(TT, CPU);
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  return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
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}
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static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
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                                      const Triple &TT) {
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  MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
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  unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
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  MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP);
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  MAI->addInitialFrameState(Inst);
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  return MAI;
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}
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static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
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                                              unsigned SyntaxVariant,
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                                              const MCAsmInfo &MAI,
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                                              const MCInstrInfo &MII,
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                                              const MCRegisterInfo &MRI) {
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  return new MipsInstPrinter(MAI, MII, MRI);
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}
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static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
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                                    std::unique_ptr<MCAsmBackend> &&MAB,
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                                    std::unique_ptr<MCObjectWriter> &&OW,
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                                    std::unique_ptr<MCCodeEmitter> &&Emitter,
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                                    bool RelaxAll) {
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  MCStreamer *S;
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  if (!T.isOSNaCl())
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    S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
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                              std::move(Emitter), RelaxAll);
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  else
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    S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW),
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                                  std::move(Emitter), RelaxAll);
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  return S;
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}
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static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
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                                                     formatted_raw_ostream &OS,
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                                                     MCInstPrinter *InstPrint,
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                                                     bool isVerboseAsm) {
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  return new MipsTargetAsmStreamer(S, OS);
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}
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static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
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  return new MipsTargetStreamer(S);
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}
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static MCTargetStreamer *
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createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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  return new MipsTargetELFStreamer(S, STI);
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}
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namespace {
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class MipsMCInstrAnalysis : public MCInstrAnalysis {
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public:
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  MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
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  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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                      uint64_t &Target) const override {
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    unsigned NumOps = Inst.getNumOperands();
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    if (NumOps == 0)
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      return false;
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    switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
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    case MCOI::OPERAND_UNKNOWN:
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    case MCOI::OPERAND_IMMEDIATE:
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      // jal, bal ...
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      Target = Inst.getOperand(NumOps - 1).getImm();
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      return true;
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    case MCOI::OPERAND_PCREL:
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      // b, j, beq ...
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      Target = Addr + Inst.getOperand(NumOps - 1).getImm();
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      return true;
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    default:
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      return false;
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    }
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  }
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};
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}
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static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
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  return new MipsMCInstrAnalysis(Info);
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}
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extern "C" void LLVMInitializeMipsTargetMC() {
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  for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
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                    &getTheMips64Target(), &getTheMips64elTarget()}) {
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    // Register the MC asm info.
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    RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
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    // Register the MC instruction info.
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    TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
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    // Register the MC register info.
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    TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
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    // Register the elf streamer.
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    TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
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    // Register the asm target streamer.
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    TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
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    TargetRegistry::RegisterNullTargetStreamer(*T,
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                                               createMipsNullTargetStreamer);
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    // Register the MC subtarget info.
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    TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
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    // Register the MC instruction analyzer.
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    TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
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    // Register the MCInstPrinter.
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    TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
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    TargetRegistry::RegisterObjectTargetStreamer(
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        *T, createMipsObjectTargetStreamer);
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    // Register the asm backend.
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    TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend);
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  }
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  // Register the MC Code Emitter
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  for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
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    TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
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  for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
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    TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
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}