/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===- MipsOptionRecord.cpp - Abstraction for storing information ---------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | |
9 | | #include "MipsOptionRecord.h" |
10 | | #include "MipsABIInfo.h" |
11 | | #include "MipsELFStreamer.h" |
12 | | #include "MipsTargetStreamer.h" |
13 | | #include "llvm/BinaryFormat/ELF.h" |
14 | | #include "llvm/MC/MCAssembler.h" |
15 | | #include "llvm/MC/MCContext.h" |
16 | | #include "llvm/MC/MCRegisterInfo.h" |
17 | | #include "llvm/MC/MCSectionELF.h" |
18 | | #include <cassert> |
19 | | |
20 | | using namespace llvm; |
21 | | |
22 | 542 | void MipsRegInfoRecord::EmitMipsOptionRecord() { |
23 | 542 | MCAssembler &MCA = Streamer->getAssembler(); |
24 | 542 | MipsTargetStreamer *MTS = |
25 | 542 | static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer()); |
26 | 542 | |
27 | 542 | Streamer->PushSection(); |
28 | 542 | |
29 | 542 | // We need to distinguish between N64 and the rest because at the moment |
30 | 542 | // we don't emit .Mips.options for other ELFs other than N64. |
31 | 542 | // Since .reginfo has the same information as .Mips.options (ODK_REGINFO), |
32 | 542 | // we can use the same abstraction (MipsRegInfoRecord class) to handle both. |
33 | 542 | if (MTS->getABI().IsN64()) { |
34 | 162 | // The EntrySize value of 1 seems strange since the records are neither |
35 | 162 | // 1-byte long nor fixed length but it matches the value GAS emits. |
36 | 162 | MCSectionELF *Sec = |
37 | 162 | Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS, |
38 | 162 | ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, 1, ""); |
39 | 162 | MCA.registerSection(*Sec); |
40 | 162 | Sec->setAlignment(8); |
41 | 162 | Streamer->SwitchSection(Sec); |
42 | 162 | |
43 | 162 | Streamer->EmitIntValue(ELF::ODK_REGINFO, 1); // kind |
44 | 162 | Streamer->EmitIntValue(40, 1); // size |
45 | 162 | Streamer->EmitIntValue(0, 2); // section |
46 | 162 | Streamer->EmitIntValue(0, 4); // info |
47 | 162 | Streamer->EmitIntValue(ri_gprmask, 4); |
48 | 162 | Streamer->EmitIntValue(0, 4); // pad |
49 | 162 | Streamer->EmitIntValue(ri_cprmask[0], 4); |
50 | 162 | Streamer->EmitIntValue(ri_cprmask[1], 4); |
51 | 162 | Streamer->EmitIntValue(ri_cprmask[2], 4); |
52 | 162 | Streamer->EmitIntValue(ri_cprmask[3], 4); |
53 | 162 | Streamer->EmitIntValue(ri_gp_value, 8); |
54 | 380 | } else { |
55 | 380 | MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, |
56 | 380 | ELF::SHF_ALLOC, 24, ""); |
57 | 380 | MCA.registerSection(*Sec); |
58 | 380 | Sec->setAlignment(MTS->getABI().IsN32() ? 854 : 4326 ); |
59 | 380 | Streamer->SwitchSection(Sec); |
60 | 380 | |
61 | 380 | Streamer->EmitIntValue(ri_gprmask, 4); |
62 | 380 | Streamer->EmitIntValue(ri_cprmask[0], 4); |
63 | 380 | Streamer->EmitIntValue(ri_cprmask[1], 4); |
64 | 380 | Streamer->EmitIntValue(ri_cprmask[2], 4); |
65 | 380 | Streamer->EmitIntValue(ri_cprmask[3], 4); |
66 | 380 | assert((ri_gp_value & 0xffffffff) == ri_gp_value); |
67 | 380 | Streamer->EmitIntValue(ri_gp_value, 4); |
68 | 380 | } |
69 | 542 | |
70 | 542 | Streamer->PopSection(); |
71 | 542 | } |
72 | | |
73 | | void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg, |
74 | 45.5k | const MCRegisterInfo *MCRegInfo) { |
75 | 45.5k | unsigned Value = 0; |
76 | 45.5k | |
77 | 101k | for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid(); |
78 | 56.3k | ++SubRegIt) { |
79 | 56.3k | unsigned CurrentSubReg = *SubRegIt; |
80 | 56.3k | |
81 | 56.3k | unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg); |
82 | 56.3k | Value |= 1 << EncVal; |
83 | 56.3k | |
84 | 56.3k | if (GPR32RegClass->contains(CurrentSubReg) || |
85 | 56.3k | GPR64RegClass->contains(CurrentSubReg)10.9k ) |
86 | 56.1k | ri_gprmask |= Value; |
87 | 240 | else if (COP0RegClass->contains(CurrentSubReg)) |
88 | 2 | ri_cprmask[0] |= Value; |
89 | 238 | // MIPS COP1 is the FPU. |
90 | 238 | else if (FGR32RegClass->contains(CurrentSubReg) || |
91 | 238 | FGR64RegClass->contains(CurrentSubReg)122 || |
92 | 238 | AFGR64RegClass->contains(CurrentSubReg)80 || |
93 | 238 | MSA128BRegClass->contains(CurrentSubReg)60 ) |
94 | 196 | ri_cprmask[1] |= Value; |
95 | 42 | else if (COP2RegClass->contains(CurrentSubReg)) |
96 | 0 | ri_cprmask[2] |= Value; |
97 | 42 | else if (COP3RegClass->contains(CurrentSubReg)) |
98 | 0 | ri_cprmask[3] |= Value; |
99 | 56.3k | } |
100 | 45.5k | } |