Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
Line
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//===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file provides Mips specific target streamer methods.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MipsTargetStreamer.h"
14
#include "MipsInstPrinter.h"
15
#include "MCTargetDesc/MipsABIInfo.h"
16
#include "MipsELFStreamer.h"
17
#include "MipsMCExpr.h"
18
#include "MipsMCTargetDesc.h"
19
#include "MipsTargetObjectFile.h"
20
#include "llvm/BinaryFormat/ELF.h"
21
#include "llvm/MC/MCContext.h"
22
#include "llvm/MC/MCSectionELF.h"
23
#include "llvm/MC/MCSubtargetInfo.h"
24
#include "llvm/MC/MCSymbolELF.h"
25
#include "llvm/Support/CommandLine.h"
26
#include "llvm/Support/ErrorHandling.h"
27
#include "llvm/Support/FormattedStream.h"
28
29
using namespace llvm;
30
31
namespace {
32
static cl::opt<bool> RoundSectionSizes(
33
    "mips-round-section-sizes", cl::init(false),
34
    cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35
} // end anonymous namespace
36
37
MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
38
3.19k
    : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
39
3.19k
  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
40
3.19k
}
41
0
void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
42
1
void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
43
2.78k
void MipsTargetStreamer::setUsesMicroMips() {}
44
0
void MipsTargetStreamer::emitDirectiveSetMips16() {}
45
12.9k
void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
46
14.5k
void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
47
1
void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
48
13.3k
void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
49
12.8k
void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
50
3
void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
51
4
void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
52
2
void MipsTargetStreamer::emitDirectiveSetMt() {}
53
0
void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
54
2
void MipsTargetStreamer::emitDirectiveSetCRC() {}
55
2
void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
56
2
void MipsTargetStreamer::emitDirectiveSetVirt() {}
57
2
void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
58
2
void MipsTargetStreamer::emitDirectiveSetGINV() {}
59
2
void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
60
13.3k
void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
61
45
void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
62
45
  forbidModuleDirective();
63
45
}
64
13.0k
void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
65
1
void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
66
1
void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
67
1
void MipsTargetStreamer::emitDirectiveAbiCalls() {}
68
0
void MipsTargetStreamer::emitDirectiveNaN2008() {}
69
1
void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
70
1
void MipsTargetStreamer::emitDirectiveOptionPic0() {}
71
0
void MipsTargetStreamer::emitDirectiveOptionPic2() {}
72
61
void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
73
void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
74
1
                                   unsigned ReturnReg) {}
75
1
void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
76
1
void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
77
1
}
78
23
void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
79
23
  forbidModuleDirective();
80
23
}
81
12
void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
82
3
void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
83
3
void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
84
4
void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
85
3
void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
86
3
void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
87
11
void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
88
4
void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
89
2
void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
90
2
void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
91
19
void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
92
10
void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
93
6
void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
94
4
void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
95
2
void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
96
15
void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
97
493
void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
98
493
void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
99
3
void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
100
3
  forbidModuleDirective();
101
3
}
102
3
void MipsTargetStreamer::emitDirectiveSetHardFloat() {
103
3
  forbidModuleDirective();
104
3
}
105
6
void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
106
3
void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
107
3
void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
108
0
void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
109
6
void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) {
110
6
  // .cplocal $reg
111
6
  // This directive forces to use the alternate register for context pointer.
112
6
  // For example
113
6
  //   .cplocal $4
114
6
  //   jal foo
115
6
  // expands to
116
6
  //   ld    $25, %call16(foo)($4)
117
6
  //   jalr  $25
118
6
119
6
  if (!getABI().IsN32() && 
!getABI().IsN64()3
)
120
0
    return;
121
6
122
6
  GPReg = RegNo;
123
6
124
6
  forbidModuleDirective();
125
6
}
126
bool MipsTargetStreamer::emitDirectiveCpRestore(
127
    int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
128
29
    const MCSubtargetInfo *STI) {
129
29
  forbidModuleDirective();
130
29
  return true;
131
29
}
132
void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
133
0
                                              const MCSymbol &Sym, bool IsReg) {
134
0
}
135
void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
136
0
                                               bool SaveLocationIsRegister) {}
137
138
20
void MipsTargetStreamer::emitDirectiveModuleFP() {}
139
140
33
void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
141
33
  if (!ABIFlagsSection.OddSPReg && 
!ABIFlagsSection.Is32BitABI14
)
142
0
    report_fatal_error("+nooddspreg is only valid for O32");
143
33
}
144
2
void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
145
1
void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
146
1
void MipsTargetStreamer::emitDirectiveModuleMT() {}
147
1
void MipsTargetStreamer::emitDirectiveModuleCRC() {}
148
1
void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
149
1
void MipsTargetStreamer::emitDirectiveModuleVirt() {}
150
1
void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
151
1
void MipsTargetStreamer::emitDirectiveModuleGINV() {}
152
1
void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
153
void MipsTargetStreamer::emitDirectiveSetFp(
154
11
    MipsABIFlagsSection::FpABIKind Value) {
155
11
  forbidModuleDirective();
156
11
}
157
3
void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
158
2
void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
159
2
  forbidModuleDirective();
160
2
}
161
162
void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
163
423
                               const MCSubtargetInfo *STI) {
164
423
  MCInst TmpInst;
165
423
  TmpInst.setOpcode(Opcode);
166
423
  TmpInst.addOperand(MCOperand::createReg(Reg0));
167
423
  TmpInst.setLoc(IDLoc);
168
423
  getStreamer().EmitInstruction(TmpInst, *STI);
169
423
}
170
171
void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
172
2.16k
                                SMLoc IDLoc, const MCSubtargetInfo *STI) {
173
2.16k
  MCInst TmpInst;
174
2.16k
  TmpInst.setOpcode(Opcode);
175
2.16k
  TmpInst.addOperand(MCOperand::createReg(Reg0));
176
2.16k
  TmpInst.addOperand(Op1);
177
2.16k
  TmpInst.setLoc(IDLoc);
178
2.16k
  getStreamer().EmitInstruction(TmpInst, *STI);
179
2.16k
}
180
181
void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
182
1.31k
                                SMLoc IDLoc, const MCSubtargetInfo *STI) {
183
1.31k
  emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
184
1.31k
}
185
186
void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
187
581
                                SMLoc IDLoc, const MCSubtargetInfo *STI) {
188
581
  emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
189
581
}
190
191
void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
192
133
                                SMLoc IDLoc, const MCSubtargetInfo *STI) {
193
133
  MCInst TmpInst;
194
133
  TmpInst.setOpcode(Opcode);
195
133
  TmpInst.addOperand(MCOperand::createImm(Imm1));
196
133
  TmpInst.addOperand(MCOperand::createImm(Imm2));
197
133
  TmpInst.setLoc(IDLoc);
198
133
  getStreamer().EmitInstruction(TmpInst, *STI);
199
133
}
200
201
void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
202
                                 MCOperand Op2, SMLoc IDLoc,
203
8.77k
                                 const MCSubtargetInfo *STI) {
204
8.77k
  MCInst TmpInst;
205
8.77k
  TmpInst.setOpcode(Opcode);
206
8.77k
  TmpInst.addOperand(MCOperand::createReg(Reg0));
207
8.77k
  TmpInst.addOperand(MCOperand::createReg(Reg1));
208
8.77k
  TmpInst.addOperand(Op2);
209
8.77k
  TmpInst.setLoc(IDLoc);
210
8.77k
  getStreamer().EmitInstruction(TmpInst, *STI);
211
8.77k
}
212
213
void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
214
                                 unsigned Reg2, SMLoc IDLoc,
215
1.43k
                                 const MCSubtargetInfo *STI) {
216
1.43k
  emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
217
1.43k
}
218
219
void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
220
                                 int16_t Imm, SMLoc IDLoc,
221
6.49k
                                 const MCSubtargetInfo *STI) {
222
6.49k
  emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
223
6.49k
}
224
225
void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
226
                                   unsigned Reg1, int16_t Imm0, int16_t Imm1,
227
                                   int16_t Imm2, SMLoc IDLoc,
228
42
                                   const MCSubtargetInfo *STI) {
229
42
  MCInst TmpInst;
230
42
  TmpInst.setOpcode(Opcode);
231
42
  TmpInst.addOperand(MCOperand::createReg(Reg0));
232
42
  TmpInst.addOperand(MCOperand::createReg(Reg1));
233
42
  TmpInst.addOperand(MCOperand::createImm(Imm0));
234
42
  TmpInst.addOperand(MCOperand::createImm(Imm1));
235
42
  TmpInst.addOperand(MCOperand::createImm(Imm2));
236
42
  TmpInst.setLoc(IDLoc);
237
42
  getStreamer().EmitInstruction(TmpInst, *STI);
238
42
}
239
240
void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
241
                                  unsigned TrgReg, bool Is64Bit,
242
0
                                  const MCSubtargetInfo *STI) {
243
0
  emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
244
0
          STI);
245
0
}
246
247
void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
248
                                  int16_t ShiftAmount, SMLoc IDLoc,
249
868
                                  const MCSubtargetInfo *STI) {
250
868
  if (ShiftAmount >= 32) {
251
80
    emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
252
80
    return;
253
80
  }
254
788
255
788
  emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
256
788
}
257
258
void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
259
1.12k
                                            const MCSubtargetInfo *STI) {
260
1.12k
  if (hasShortDelaySlot)
261
87
    emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
262
1.04k
  else
263
1.04k
    emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
264
1.12k
}
265
266
37
void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
267
37
  const FeatureBitset &Features = STI->getFeatureBits();
268
37
  if (Features[Mips::FeatureMicroMips])
269
0
    emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
270
37
  else
271
37
    emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
272
37
}
273
274
/// Emit the $gp restore operation for .cprestore.
275
void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
276
26
                                       const MCSubtargetInfo *STI) {
277
26
  emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
278
26
}
279
280
/// Emit a store instruction with an immediate offset.
281
void MipsTargetStreamer::emitStoreWithImmOffset(
282
    unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
283
    function_ref<unsigned()> GetATReg, SMLoc IDLoc,
284
6
    const MCSubtargetInfo *STI) {
285
6
  if (isInt<16>(Offset)) {
286
5
    emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
287
5
    return;
288
5
  }
289
1
290
1
  // sw $8, offset($8) => lui $at, %hi(offset)
291
1
  //                      add $at, $at, $8
292
1
  //                      sw $8, %lo(offset)($at)
293
1
294
1
  unsigned ATReg = GetATReg();
295
1
  if (!ATReg)
296
1
    return;
297
0
298
0
  unsigned LoOffset = Offset & 0x0000ffff;
299
0
  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
300
0
301
0
  // If msb of LoOffset is 1(negative number) we must increment HiOffset
302
0
  // to account for the sign-extension of the low part.
303
0
  if (LoOffset & 0x8000)
304
0
    HiOffset++;
305
0
306
0
  // Generate the base address in ATReg.
307
0
  emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
308
0
  if (BaseReg != Mips::ZERO)
309
0
    emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
310
0
  // Emit the store with the adjusted base and offset.
311
0
  emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
312
0
}
313
314
/// Emit a store instruction with an symbol offset. Symbols are assumed to be
315
/// out of range for a simm16 will be expanded to appropriate instructions.
316
void MipsTargetStreamer::emitStoreWithSymOffset(
317
    unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
318
    MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
319
9
    const MCSubtargetInfo *STI) {
320
9
  // sw $8, sym => lui $at, %hi(sym)
321
9
  //               sw $8, %lo(sym)($at)
322
9
323
9
  // Generate the base address in ATReg.
324
9
  emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
325
9
  if (BaseReg != Mips::ZERO)
326
3
    emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
327
9
  // Emit the store with the adjusted base and offset.
328
9
  emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
329
9
}
330
331
/// Emit a load instruction with an immediate offset. DstReg and TmpReg are
332
/// permitted to be the same register iff DstReg is distinct from BaseReg and
333
/// DstReg is a GPR. It is the callers responsibility to identify such cases
334
/// and pass the appropriate register in TmpReg.
335
void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
336
                                               unsigned BaseReg, int64_t Offset,
337
                                               unsigned TmpReg, SMLoc IDLoc,
338
26
                                               const MCSubtargetInfo *STI) {
339
26
  if (isInt<16>(Offset)) {
340
23
    emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
341
23
    return;
342
23
  }
343
3
344
3
  // 1) lw $8, offset($9) => lui $8, %hi(offset)
345
3
  //                         add $8, $8, $9
346
3
  //                         lw $8, %lo(offset)($9)
347
3
  // 2) lw $8, offset($8) => lui $at, %hi(offset)
348
3
  //                         add $at, $at, $8
349
3
  //                         lw $8, %lo(offset)($at)
350
3
351
3
  unsigned LoOffset = Offset & 0x0000ffff;
352
3
  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
353
3
354
3
  // If msb of LoOffset is 1(negative number) we must increment HiOffset
355
3
  // to account for the sign-extension of the low part.
356
3
  if (LoOffset & 0x8000)
357
0
    HiOffset++;
358
3
359
3
  // Generate the base address in TmpReg.
360
3
  emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
361
3
  if (BaseReg != Mips::ZERO)
362
3
    emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
363
3
  // Emit the load with the adjusted base and offset.
364
3
  emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
365
3
}
366
367
/// Emit a load instruction with an symbol offset. Symbols are assumed to be
368
/// out of range for a simm16 will be expanded to appropriate instructions.
369
/// DstReg and TmpReg are permitted to be the same register iff DstReg is a
370
/// GPR. It is the callers responsibility to identify such cases and pass the
371
/// appropriate register in TmpReg.
372
void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
373
                                               unsigned BaseReg,
374
                                               MCOperand &HiOperand,
375
                                               MCOperand &LoOperand,
376
                                               unsigned TmpReg, SMLoc IDLoc,
377
12
                                               const MCSubtargetInfo *STI) {
378
12
  // 1) lw $8, sym        => lui $8, %hi(sym)
379
12
  //                         lw $8, %lo(sym)($8)
380
12
  // 2) ldc1 $f0, sym     => lui $at, %hi(sym)
381
12
  //                         ldc1 $f0, %lo(sym)($at)
382
12
383
12
  // Generate the base address in TmpReg.
384
12
  emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
385
12
  if (BaseReg != Mips::ZERO)
386
6
    emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
387
12
  // Emit the load with the adjusted base and offset.
388
12
  emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
389
12
}
390
391
MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
392
                                             formatted_raw_ostream &OS)
393
2.65k
    : MipsTargetStreamer(S), OS(OS) {}
394
395
881
void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
396
881
  OS << "\t.set\tmicromips\n";
397
881
  forbidModuleDirective();
398
881
}
399
400
12.3k
void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
401
12.3k
  OS << "\t.set\tnomicromips\n";
402
12.3k
  forbidModuleDirective();
403
12.3k
}
404
405
384
void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
406
384
  OS << "\t.set\tmips16\n";
407
384
  forbidModuleDirective();
408
384
}
409
410
12.8k
void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
411
12.8k
  OS << "\t.set\tnomips16\n";
412
12.8k
  MipsTargetStreamer::emitDirectiveSetNoMips16();
413
12.8k
}
414
415
14.3k
void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
416
14.3k
  OS << "\t.set\treorder\n";
417
14.3k
  MipsTargetStreamer::emitDirectiveSetReorder();
418
14.3k
}
419
420
13.7k
void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
421
13.7k
  OS << "\t.set\tnoreorder\n";
422
13.7k
  forbidModuleDirective();
423
13.7k
}
424
425
13.2k
void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
426
13.2k
  OS << "\t.set\tmacro\n";
427
13.2k
  MipsTargetStreamer::emitDirectiveSetMacro();
428
13.2k
}
429
430
12.7k
void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
431
12.7k
  OS << "\t.set\tnomacro\n";
432
12.7k
  MipsTargetStreamer::emitDirectiveSetNoMacro();
433
12.7k
}
434
435
3
void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
436
3
  OS << "\t.set\tmsa\n";
437
3
  MipsTargetStreamer::emitDirectiveSetMsa();
438
3
}
439
440
4
void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
441
4
  OS << "\t.set\tnomsa\n";
442
4
  MipsTargetStreamer::emitDirectiveSetNoMsa();
443
4
}
444
445
1
void MipsTargetAsmStreamer::emitDirectiveSetMt() {
446
1
  OS << "\t.set\tmt\n";
447
1
  MipsTargetStreamer::emitDirectiveSetMt();
448
1
}
449
450
0
void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
451
0
  OS << "\t.set\tnomt\n";
452
0
  MipsTargetStreamer::emitDirectiveSetNoMt();
453
0
}
454
455
2
void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
456
2
  OS << "\t.set\tcrc\n";
457
2
  MipsTargetStreamer::emitDirectiveSetCRC();
458
2
}
459
460
2
void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
461
2
  OS << "\t.set\tnocrc\n";
462
2
  MipsTargetStreamer::emitDirectiveSetNoCRC();
463
2
}
464
465
2
void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
466
2
  OS << "\t.set\tvirt\n";
467
2
  MipsTargetStreamer::emitDirectiveSetVirt();
468
2
}
469
470
2
void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
471
2
  OS << "\t.set\tnovirt\n";
472
2
  MipsTargetStreamer::emitDirectiveSetNoVirt();
473
2
}
474
475
2
void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
476
2
  OS << "\t.set\tginv\n";
477
2
  MipsTargetStreamer::emitDirectiveSetGINV();
478
2
}
479
480
2
void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
481
2
  OS << "\t.set\tnoginv\n";
482
2
  MipsTargetStreamer::emitDirectiveSetNoGINV();
483
2
}
484
485
13.2k
void MipsTargetAsmStreamer::emitDirectiveSetAt() {
486
13.2k
  OS << "\t.set\tat\n";
487
13.2k
  MipsTargetStreamer::emitDirectiveSetAt();
488
13.2k
}
489
490
45
void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
491
45
  OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
492
45
  MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
493
45
}
494
495
12.9k
void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
496
12.9k
  OS << "\t.set\tnoat\n";
497
12.9k
  MipsTargetStreamer::emitDirectiveSetNoAt();
498
12.9k
}
499
500
13.2k
void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
501
13.2k
  OS << "\t.end\t" << Name << '\n';
502
13.2k
}
503
504
13.2k
void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
505
13.2k
  OS << "\t.ent\t" << Symbol.getName() << '\n';
506
13.2k
}
507
508
1.59k
void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
509
510
260
void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
511
512
1.69k
void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
513
1.69k
  OS << "\t.nan\tlegacy\n";
514
1.69k
}
515
516
850
void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
517
850
  OS << "\t.option\tpic0\n";
518
850
}
519
520
32
void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
521
32
  OS << "\t.option\tpic2\n";
522
32
}
523
524
45
void MipsTargetAsmStreamer::emitDirectiveInsn() {
525
45
  MipsTargetStreamer::emitDirectiveInsn();
526
45
  OS << "\t.insn\n";
527
45
}
528
529
void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
530
13.0k
                                      unsigned ReturnReg) {
531
13.0k
  OS << "\t.frame\t$"
532
13.0k
     << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
533
13.0k
     << StackSize << ",$"
534
13.0k
     << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
535
13.0k
}
536
537
22
void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
538
22
  OS << "\t.set arch=" << Arch << "\n";
539
22
  MipsTargetStreamer::emitDirectiveSetArch(Arch);
540
22
}
541
542
8
void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
543
8
  OS << "\t.set\tmips0\n";
544
8
  MipsTargetStreamer::emitDirectiveSetMips0();
545
8
}
546
547
3
void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
548
3
  OS << "\t.set\tmips1\n";
549
3
  MipsTargetStreamer::emitDirectiveSetMips1();
550
3
}
551
552
3
void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
553
3
  OS << "\t.set\tmips2\n";
554
3
  MipsTargetStreamer::emitDirectiveSetMips2();
555
3
}
556
557
4
void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
558
4
  OS << "\t.set\tmips3\n";
559
4
  MipsTargetStreamer::emitDirectiveSetMips3();
560
4
}
561
562
3
void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
563
3
  OS << "\t.set\tmips4\n";
564
3
  MipsTargetStreamer::emitDirectiveSetMips4();
565
3
}
566
567
3
void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
568
3
  OS << "\t.set\tmips5\n";
569
3
  MipsTargetStreamer::emitDirectiveSetMips5();
570
3
}
571
572
11
void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
573
11
  OS << "\t.set\tmips32\n";
574
11
  MipsTargetStreamer::emitDirectiveSetMips32();
575
11
}
576
577
4
void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
578
4
  OS << "\t.set\tmips32r2\n";
579
4
  MipsTargetStreamer::emitDirectiveSetMips32R2();
580
4
}
581
582
2
void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
583
2
  OS << "\t.set\tmips32r3\n";
584
2
  MipsTargetStreamer::emitDirectiveSetMips32R3();
585
2
}
586
587
2
void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
588
2
  OS << "\t.set\tmips32r5\n";
589
2
  MipsTargetStreamer::emitDirectiveSetMips32R5();
590
2
}
591
592
15
void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
593
15
  OS << "\t.set\tmips32r6\n";
594
15
  MipsTargetStreamer::emitDirectiveSetMips32R6();
595
15
}
596
597
8
void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
598
8
  OS << "\t.set\tmips64\n";
599
8
  MipsTargetStreamer::emitDirectiveSetMips64();
600
8
}
601
602
6
void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
603
6
  OS << "\t.set\tmips64r2\n";
604
6
  MipsTargetStreamer::emitDirectiveSetMips64R2();
605
6
}
606
607
4
void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
608
4
  OS << "\t.set\tmips64r3\n";
609
4
  MipsTargetStreamer::emitDirectiveSetMips64R3();
610
4
}
611
612
2
void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
613
2
  OS << "\t.set\tmips64r5\n";
614
2
  MipsTargetStreamer::emitDirectiveSetMips64R5();
615
2
}
616
617
12
void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
618
12
  OS << "\t.set\tmips64r6\n";
619
12
  MipsTargetStreamer::emitDirectiveSetMips64R6();
620
12
}
621
622
6
void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
623
6
  OS << "\t.set\tdsp\n";
624
6
  MipsTargetStreamer::emitDirectiveSetDsp();
625
6
}
626
627
3
void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
628
3
  OS << "\t.set\tdspr2\n";
629
3
  MipsTargetStreamer::emitDirectiveSetDspr2();
630
3
}
631
632
3
void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
633
3
  OS << "\t.set\tnodsp\n";
634
3
  MipsTargetStreamer::emitDirectiveSetNoDsp();
635
3
}
636
637
477
void MipsTargetAsmStreamer::emitDirectiveSetPop() {
638
477
  OS << "\t.set\tpop\n";
639
477
  MipsTargetStreamer::emitDirectiveSetPop();
640
477
}
641
642
477
void MipsTargetAsmStreamer::emitDirectiveSetPush() {
643
477
 OS << "\t.set\tpush\n";
644
477
 MipsTargetStreamer::emitDirectiveSetPush();
645
477
}
646
647
3
void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
648
3
  OS << "\t.set\tsoftfloat\n";
649
3
  MipsTargetStreamer::emitDirectiveSetSoftFloat();
650
3
}
651
652
3
void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
653
3
  OS << "\t.set\thardfloat\n";
654
3
  MipsTargetStreamer::emitDirectiveSetHardFloat();
655
3
}
656
657
// Print a 32 bit hex number with all numbers.
658
26.1k
static void printHex32(unsigned Value, raw_ostream &OS) {
659
26.1k
  OS << "0x";
660
235k
  for (int i = 7; i >= 0; 
i--209k
)
661
209k
    OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
662
26.1k
}
663
664
void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
665
13.0k
                                     int CPUTopSavedRegOff) {
666
13.0k
  OS << "\t.mask \t";
667
13.0k
  printHex32(CPUBitmask, OS);
668
13.0k
  OS << ',' << CPUTopSavedRegOff << '\n';
669
13.0k
}
670
671
void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
672
13.0k
                                      int FPUTopSavedRegOff) {
673
13.0k
  OS << "\t.fmask\t";
674
13.0k
  printHex32(FPUBitmask, OS);
675
13.0k
  OS << "," << FPUTopSavedRegOff << '\n';
676
13.0k
}
677
678
16
void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
679
16
  OS << "\t.cpload\t$"
680
16
     << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
681
16
  forbidModuleDirective();
682
16
}
683
684
4
void MipsTargetAsmStreamer::emitDirectiveCpLocal(unsigned RegNo) {
685
4
  OS << "\t.cplocal\t$"
686
4
     << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
687
4
  MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
688
4
}
689
690
bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
691
    int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
692
15
    const MCSubtargetInfo *STI) {
693
15
  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
694
15
  OS << "\t.cprestore\t" << Offset << "\n";
695
15
  return true;
696
15
}
697
698
void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
699
                                                 int RegOrOffset,
700
                                                 const MCSymbol &Sym,
701
19
                                                 bool IsReg) {
702
19
  OS << "\t.cpsetup\t$"
703
19
     << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
704
19
705
19
  if (IsReg)
706
6
    OS << "$"
707
6
       << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
708
13
  else
709
13
    OS << RegOrOffset;
710
19
711
19
  OS << ", ";
712
19
713
19
  OS << Sym.getName();
714
19
  forbidModuleDirective();
715
19
}
716
717
void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
718
12
                                                  bool SaveLocationIsRegister) {
719
12
  OS << "\t.cpreturn";
720
12
  forbidModuleDirective();
721
12
}
722
723
485
void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
724
485
  MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
725
485
  if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
726
71
    OS << "\t.module\tsoftfloat\n";
727
414
  else
728
414
    OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
729
485
}
730
731
void MipsTargetAsmStreamer::emitDirectiveSetFp(
732
6
    MipsABIFlagsSection::FpABIKind Value) {
733
6
  MipsTargetStreamer::emitDirectiveSetFp(Value);
734
6
735
6
  OS << "\t.set\tfp=";
736
6
  OS << ABIFlagsSection.getFpABIString(Value) << "\n";
737
6
}
738
739
29
void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
740
29
  MipsTargetStreamer::emitDirectiveModuleOddSPReg();
741
29
742
29
  OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? 
""16
:
"no"13
) << "oddspreg\n";
743
29
}
744
745
3
void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
746
3
  MipsTargetStreamer::emitDirectiveSetOddSPReg();
747
3
  OS << "\t.set\toddspreg\n";
748
3
}
749
750
2
void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
751
2
  MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
752
2
  OS << "\t.set\tnooddspreg\n";
753
2
}
754
755
2
void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
756
2
  OS << "\t.module\tsoftfloat\n";
757
2
}
758
759
1
void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
760
1
  OS << "\t.module\thardfloat\n";
761
1
}
762
763
1
void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
764
1
  OS << "\t.module\tmt\n";
765
1
}
766
767
1
void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
768
1
  OS << "\t.module\tcrc\n";
769
1
}
770
771
1
void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
772
1
  OS << "\t.module\tnocrc\n";
773
1
}
774
775
1
void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
776
1
  OS << "\t.module\tvirt\n";
777
1
}
778
779
1
void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
780
1
  OS << "\t.module\tnovirt\n";
781
1
}
782
783
1
void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
784
1
  OS << "\t.module\tginv\n";
785
1
}
786
787
1
void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
788
1
  OS << "\t.module\tnoginv\n";
789
1
}
790
791
// This part is for ELF object output.
792
MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
793
                                             const MCSubtargetInfo &STI)
794
546
    : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
795
546
  MCAssembler &MCA = getStreamer().getAssembler();
796
546
797
546
  // It's possible that MCObjectFileInfo isn't fully initialized at this point
798
546
  // due to an initialization order problem where LLVMTargetMachine creates the
799
546
  // target streamer before TargetLoweringObjectFile calls
800
546
  // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
801
546
  // covers all cases so this statement covers most cases and direct object
802
546
  // emission must call setPic() once MCObjectFileInfo has been initialized. The
803
546
  // cases we don't handle here are covered by MipsAsmPrinter.
804
546
  Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
805
546
806
546
  const FeatureBitset &Features = STI.getFeatureBits();
807
546
808
546
  // Set the header flags that we can in the constructor.
809
546
  // FIXME: This is a fairly terrible hack. We set the rest
810
546
  // of these in the destructor. The problem here is two-fold:
811
546
  //
812
546
  // a: Some of the eflags can be set/reset by directives.
813
546
  // b: There aren't any usage paths that initialize the ABI
814
546
  //    pointer until after we initialize either an assembler
815
546
  //    or the target machine.
816
546
  // We can fix this by making the target streamer construct
817
546
  // the ABI, but this is fraught with wide ranging dependency
818
546
  // issues as well.
819
546
  unsigned EFlags = MCA.getELFHeaderEFlags();
820
546
821
546
  // FIXME: Fix a dependency issue by instantiating the ABI object to some
822
546
  // default based off the triple. The triple doesn't describe the target
823
546
  // fully, but any external user of the API that uses the MCTargetStreamer
824
546
  // would otherwise crash on assertion failure.
825
546
826
546
  ABI = MipsABIInfo(
827
546
      STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
828
546
              
STI.getTargetTriple().getArch() == Triple::ArchType::mips424
829
546
          ? 
MipsABIInfo::O32()362
830
546
          : 
MipsABIInfo::N64()184
);
831
546
832
546
  // Architecture
833
546
  if (Features[Mips::FeatureMips64r6])
834
18
    EFlags |= ELF::EF_MIPS_ARCH_64R6;
835
528
  else if (Features[Mips::FeatureMips64r2] ||
836
528
           
Features[Mips::FeatureMips64r3]461
||
837
528
           
Features[Mips::FeatureMips64r5]461
)
838
67
    EFlags |= ELF::EF_MIPS_ARCH_64R2;
839
461
  else if (Features[Mips::FeatureMips64])
840
113
    EFlags |= ELF::EF_MIPS_ARCH_64;
841
348
  else if (Features[Mips::FeatureMips5])
842
8
    EFlags |= ELF::EF_MIPS_ARCH_5;
843
340
  else if (Features[Mips::FeatureMips4])
844
8
    EFlags |= ELF::EF_MIPS_ARCH_4;
845
332
  else if (Features[Mips::FeatureMips3])
846
12
    EFlags |= ELF::EF_MIPS_ARCH_3;
847
320
  else if (Features[Mips::FeatureMips32r6])
848
47
    EFlags |= ELF::EF_MIPS_ARCH_32R6;
849
273
  else if (Features[Mips::FeatureMips32r2] ||
850
273
           
Features[Mips::FeatureMips32r3]216
||
851
273
           
Features[Mips::FeatureMips32r5]216
)
852
57
    EFlags |= ELF::EF_MIPS_ARCH_32R2;
853
216
  else if (Features[Mips::FeatureMips32])
854
208
    EFlags |= ELF::EF_MIPS_ARCH_32;
855
8
  else if (Features[Mips::FeatureMips2])
856
3
    EFlags |= ELF::EF_MIPS_ARCH_2;
857
5
  else
858
5
    EFlags |= ELF::EF_MIPS_ARCH_1;
859
546
860
546
  // Machine
861
546
  if (Features[Mips::FeatureCnMips])
862
7
    EFlags |= ELF::EF_MIPS_MACH_OCTEON;
863
546
864
546
  // Other options.
865
546
  if (Features[Mips::FeatureNaN2008])
866
109
    EFlags |= ELF::EF_MIPS_NAN2008;
867
546
868
546
  MCA.setELFHeaderEFlags(EFlags);
869
546
}
870
871
12.1k
void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
872
12.1k
  auto *Symbol = cast<MCSymbolELF>(S);
873
12.1k
  getStreamer().getAssembler().registerSymbol(*Symbol);
874
12.1k
  uint8_t Type = Symbol->getType();
875
12.1k
  if (Type != ELF::STT_FUNC)
876
11.8k
    return;
877
288
878
288
  if (isMicroMipsEnabled())
879
43
    Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
880
288
}
881
882
542
void MipsTargetELFStreamer::finish() {
883
542
  MCAssembler &MCA = getStreamer().getAssembler();
884
542
  const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
885
542
886
542
  // .bss, .text and .data are always at least 16-byte aligned.
887
542
  MCSection &TextSection = *OFI.getTextSection();
888
542
  MCA.registerSection(TextSection);
889
542
  MCSection &DataSection = *OFI.getDataSection();
890
542
  MCA.registerSection(DataSection);
891
542
  MCSection &BSSSection = *OFI.getBSSSection();
892
542
  MCA.registerSection(BSSSection);
893
542
894
542
  TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
895
542
  DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
896
542
  BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
897
542
898
542
  if (RoundSectionSizes) {
899
1
    // Make sections sizes a multiple of the alignment. This is useful for
900
1
    // verifying the output of IAS against the output of other assemblers but
901
1
    // it's not necessary to produce a correct object and increases section
902
1
    // size.
903
1
    MCStreamer &OS = getStreamer();
904
16
    for (MCSection &S : MCA) {
905
16
      MCSectionELF &Section = static_cast<MCSectionELF &>(S);
906
16
907
16
      unsigned Alignment = Section.getAlignment();
908
16
      if (Alignment) {
909
16
        OS.SwitchSection(&Section);
910
16
        if (Section.UseCodeAlign())
911
5
          OS.EmitCodeAlignment(Alignment, Alignment);
912
11
        else
913
11
          OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
914
16
      }
915
16
    }
916
1
  }
917
542
918
542
  const FeatureBitset &Features = STI.getFeatureBits();
919
542
920
542
  // Update e_header flags. See the FIXME and comment above in
921
542
  // the constructor for a full rundown on this.
922
542
  unsigned EFlags = MCA.getELFHeaderEFlags();
923
542
924
542
  // ABI
925
542
  // N64 does not require any ABI bits.
926
542
  if (getABI().IsO32())
927
326
    EFlags |= ELF::EF_MIPS_ABI_O32;
928
216
  else if (getABI().IsN32())
929
54
    EFlags |= ELF::EF_MIPS_ABI2;
930
542
931
542
  if (Features[Mips::FeatureGP64Bit]) {
932
223
    if (getABI().IsO32())
933
8
      EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
934
319
  } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
935
0
    EFlags |= ELF::EF_MIPS_32BITMODE;
936
542
937
542
  // -mplt is not implemented but we should act as if it was
938
542
  // given.
939
542
  if (!Features[Mips::FeatureNoABICalls])
940
542
    EFlags |= ELF::EF_MIPS_CPIC;
941
542
942
542
  if (Pic)
943
108
    EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
944
542
945
542
  MCA.setELFHeaderEFlags(EFlags);
946
542
947
542
  // Emit all the option records.
948
542
  // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
949
542
  // .reginfo.
950
542
  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
951
542
  MEF.EmitMipsOptionRecords();
952
542
953
542
  emitMipsAbiFlags();
954
542
}
955
956
27
void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
957
27
  auto *Symbol = cast<MCSymbolELF>(S);
958
27
  // If on rhs is micromips symbol then mark Symbol as microMips.
959
27
  if (Value->getKind() != MCExpr::SymbolRef)
960
14
    return;
961
13
  const auto &RhsSym = cast<MCSymbolELF>(
962
13
      static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
963
13
964
13
  if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
965
11
    return;
966
2
967
2
  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
968
2
}
969
970
15.5k
MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
971
15.5k
  return static_cast<MCELFStreamer &>(Streamer);
972
15.5k
}
973
974
69
void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
975
69
  MicroMipsEnabled = true;
976
69
  forbidModuleDirective();
977
69
}
978
979
118
void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
980
118
  MicroMipsEnabled = false;
981
118
  forbidModuleDirective();
982
118
}
983
984
196
void MipsTargetELFStreamer::setUsesMicroMips() {
985
196
  MCAssembler &MCA = getStreamer().getAssembler();
986
196
  unsigned Flags = MCA.getELFHeaderEFlags();
987
196
  Flags |= ELF::EF_MIPS_MICROMIPS;
988
196
  MCA.setELFHeaderEFlags(Flags);
989
196
}
990
991
1
void MipsTargetELFStreamer::emitDirectiveSetMips16() {
992
1
  MCAssembler &MCA = getStreamer().getAssembler();
993
1
  unsigned Flags = MCA.getELFHeaderEFlags();
994
1
  Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
995
1
  MCA.setELFHeaderEFlags(Flags);
996
1
  forbidModuleDirective();
997
1
}
998
999
245
void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
1000
245
  MCAssembler &MCA = getStreamer().getAssembler();
1001
245
  unsigned Flags = MCA.getELFHeaderEFlags();
1002
245
  Flags |= ELF::EF_MIPS_NOREORDER;
1003
245
  MCA.setELFHeaderEFlags(Flags);
1004
245
  forbidModuleDirective();
1005
245
}
1006
1007
157
void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
1008
157
  MCAssembler &MCA = getStreamer().getAssembler();
1009
157
  MCContext &Context = MCA.getContext();
1010
157
  MCStreamer &OS = getStreamer();
1011
157
1012
157
  MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1013
157
1014
157
  MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1015
157
  const MCSymbolRefExpr *ExprRef =
1016
157
      MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
1017
157
1018
157
  MCA.registerSection(*Sec);
1019
157
  Sec->setAlignment(4);
1020
157
1021
157
  OS.PushSection();
1022
157
1023
157
  OS.SwitchSection(Sec);
1024
157
1025
157
  OS.EmitValueImpl(ExprRef, 4);
1026
157
1027
157
  OS.EmitIntValue(GPRInfoSet ? 
GPRBitMask129
:
028
, 4); // reg_mask
1028
157
  OS.EmitIntValue(GPRInfoSet ? 
GPROffset129
:
028
, 4); // reg_offset
1029
157
1030
157
  OS.EmitIntValue(FPRInfoSet ? 
FPRBitMask129
:
028
, 4); // fpreg_mask
1031
157
  OS.EmitIntValue(FPRInfoSet ? 
FPROffset129
:
028
, 4); // fpreg_offset
1032
157
1033
157
  OS.EmitIntValue(FrameInfoSet ? 
FrameOffset147
:
010
, 4); // frame_offset
1034
157
  OS.EmitIntValue(FrameInfoSet ? 
FrameReg147
:
010
, 4); // frame_reg
1035
157
  OS.EmitIntValue(FrameInfoSet ? 
ReturnReg147
:
010
, 4); // return_reg
1036
157
1037
157
  // The .end directive marks the end of a procedure. Invalidate
1038
157
  // the information gathered up until this point.
1039
157
  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1040
157
1041
157
  OS.PopSection();
1042
157
1043
157
  // .end also implicitly sets the size.
1044
157
  MCSymbol *CurPCSym = Context.createTempSymbol();
1045
157
  OS.EmitLabel(CurPCSym);
1046
157
  const MCExpr *Size = MCBinaryExpr::createSub(
1047
157
      MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
1048
157
      ExprRef, Context);
1049
157
1050
157
  // The ELFObjectWriter can determine the absolute size as it has access to
1051
157
  // the layout information of the assembly file, so a size expression rather
1052
157
  // than an absolute value is ok here.
1053
157
  static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1054
157
}
1055
1056
160
void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1057
160
  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1058
160
1059
160
  // .ent also acts like an implicit '.type symbol, STT_FUNC'
1060
160
  static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1061
160
}
1062
1063
72
void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1064
72
  MCAssembler &MCA = getStreamer().getAssembler();
1065
72
  unsigned Flags = MCA.getELFHeaderEFlags();
1066
72
  Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1067
72
  MCA.setELFHeaderEFlags(Flags);
1068
72
}
1069
1070
19
void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1071
19
  MCAssembler &MCA = getStreamer().getAssembler();
1072
19
  unsigned Flags = MCA.getELFHeaderEFlags();
1073
19
  Flags |= ELF::EF_MIPS_NAN2008;
1074
19
  MCA.setELFHeaderEFlags(Flags);
1075
19
}
1076
1077
58
void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1078
58
  MCAssembler &MCA = getStreamer().getAssembler();
1079
58
  unsigned Flags = MCA.getELFHeaderEFlags();
1080
58
  Flags &= ~ELF::EF_MIPS_NAN2008;
1081
58
  MCA.setELFHeaderEFlags(Flags);
1082
58
}
1083
1084
53
void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1085
53
  MCAssembler &MCA = getStreamer().getAssembler();
1086
53
  unsigned Flags = MCA.getELFHeaderEFlags();
1087
53
  // This option overrides other PIC options like -KPIC.
1088
53
  Pic = false;
1089
53
  Flags &= ~ELF::EF_MIPS_PIC;
1090
53
  MCA.setELFHeaderEFlags(Flags);
1091
53
}
1092
1093
59
void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1094
59
  MCAssembler &MCA = getStreamer().getAssembler();
1095
59
  unsigned Flags = MCA.getELFHeaderEFlags();
1096
59
  Pic = true;
1097
59
  // NOTE: We are following the GAS behaviour here which means the directive
1098
59
  // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1099
59
  // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1100
59
  // EF_MIPS_CPIC to be mutually exclusive.
1101
59
  Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1102
59
  MCA.setELFHeaderEFlags(Flags);
1103
59
}
1104
1105
16
void MipsTargetELFStreamer::emitDirectiveInsn() {
1106
16
  MipsTargetStreamer::emitDirectiveInsn();
1107
16
  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1108
16
  MEF.createPendingLabelRelocs();
1109
16
}
1110
1111
void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1112
147
                                      unsigned ReturnReg_) {
1113
147
  MCContext &Context = getStreamer().getAssembler().getContext();
1114
147
  const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1115
147
1116
147
  FrameInfoSet = true;
1117
147
  FrameReg = RegInfo->getEncodingValue(StackReg);
1118
147
  FrameOffset = StackSize;
1119
147
  ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1120
147
}
1121
1122
void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1123
129
                                     int CPUTopSavedRegOff) {
1124
129
  GPRInfoSet = true;
1125
129
  GPRBitMask = CPUBitmask;
1126
129
  GPROffset = CPUTopSavedRegOff;
1127
129
}
1128
1129
void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1130
129
                                      int FPUTopSavedRegOff) {
1131
129
  FPRInfoSet = true;
1132
129
  FPRBitMask = FPUBitmask;
1133
129
  FPROffset = FPUTopSavedRegOff;
1134
129
}
1135
1136
15
void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1137
15
  // .cpload $reg
1138
15
  // This directive expands to:
1139
15
  // lui   $gp, %hi(_gp_disp)
1140
15
  // addui $gp, $gp, %lo(_gp_disp)
1141
15
  // addu  $gp, $gp, $reg
1142
15
  // when support for position independent code is enabled.
1143
15
  if (!Pic || 
(7
getABI().IsN32()7
||
getABI().IsN64()6
))
1144
10
    return;
1145
5
1146
5
  // There's a GNU extension controlled by -mno-shared that allows
1147
5
  // locally-binding symbols to be accessed using absolute addresses.
1148
5
  // This is currently not supported. When supported -mno-shared makes
1149
5
  // .cpload expand to:
1150
5
  //   lui     $gp, %hi(__gnu_local_gp)
1151
5
  //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1152
5
1153
5
  StringRef SymName("_gp_disp");
1154
5
  MCAssembler &MCA = getStreamer().getAssembler();
1155
5
  MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1156
5
  MCA.registerSymbol(*GP_Disp);
1157
5
1158
5
  MCInst TmpInst;
1159
5
  TmpInst.setOpcode(Mips::LUi);
1160
5
  TmpInst.addOperand(MCOperand::createReg(GPReg));
1161
5
  const MCExpr *HiSym = MipsMCExpr::create(
1162
5
      MipsMCExpr::MEK_HI,
1163
5
      MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1164
5
                              MCA.getContext()),
1165
5
      MCA.getContext());
1166
5
  TmpInst.addOperand(MCOperand::createExpr(HiSym));
1167
5
  getStreamer().EmitInstruction(TmpInst, STI);
1168
5
1169
5
  TmpInst.clear();
1170
5
1171
5
  TmpInst.setOpcode(Mips::ADDiu);
1172
5
  TmpInst.addOperand(MCOperand::createReg(GPReg));
1173
5
  TmpInst.addOperand(MCOperand::createReg(GPReg));
1174
5
  const MCExpr *LoSym = MipsMCExpr::create(
1175
5
      MipsMCExpr::MEK_LO,
1176
5
      MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1177
5
                              MCA.getContext()),
1178
5
      MCA.getContext());
1179
5
  TmpInst.addOperand(MCOperand::createExpr(LoSym));
1180
5
  getStreamer().EmitInstruction(TmpInst, STI);
1181
5
1182
5
  TmpInst.clear();
1183
5
1184
5
  TmpInst.setOpcode(Mips::ADDu);
1185
5
  TmpInst.addOperand(MCOperand::createReg(GPReg));
1186
5
  TmpInst.addOperand(MCOperand::createReg(GPReg));
1187
5
  TmpInst.addOperand(MCOperand::createReg(RegNo));
1188
5
  getStreamer().EmitInstruction(TmpInst, STI);
1189
5
1190
5
  forbidModuleDirective();
1191
5
}
1192
1193
2
void MipsTargetELFStreamer::emitDirectiveCpLocal(unsigned RegNo) {
1194
2
  if (Pic)
1195
2
    MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
1196
2
}
1197
1198
bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1199
    int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1200
14
    const MCSubtargetInfo *STI) {
1201
14
  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1202
14
  // .cprestore offset
1203
14
  // When PIC mode is enabled and the O32 ABI is used, this directive expands
1204
14
  // to:
1205
14
  //    sw $gp, offset($sp)
1206
14
  // and adds a corresponding LW after every JAL.
1207
14
1208
14
  // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1209
14
  // is used in non-PIC mode.
1210
14
  if (!Pic || 
(6
getABI().IsN32()6
||
getABI().IsN64()6
))
1211
8
    return true;
1212
6
1213
6
  // Store the $gp on the stack.
1214
6
  emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1215
6
                         STI);
1216
6
  return true;
1217
6
}
1218
1219
void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1220
                                                 int RegOrOffset,
1221
                                                 const MCSymbol &Sym,
1222
18
                                                 bool IsReg) {
1223
18
  // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1224
18
  if (!Pic || 
!(15
getABI().IsN32()15
||
getABI().IsN64()10
))
1225
8
    return;
1226
10
1227
10
  forbidModuleDirective();
1228
10
1229
10
  MCAssembler &MCA = getStreamer().getAssembler();
1230
10
  MCInst Inst;
1231
10
1232
10
  // Either store the old $gp in a register or on the stack
1233
10
  if (IsReg) {
1234
4
    // move $save, $gpreg
1235
4
    emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1236
6
  } else {
1237
6
    // sd $gpreg, offset($sp)
1238
6
    emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1239
6
  }
1240
10
1241
10
  if (getABI().IsN32()) {
1242
5
    MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1243
5
    const MipsMCExpr *HiExpr = MipsMCExpr::create(
1244
5
        MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1245
5
        MCA.getContext());
1246
5
    const MipsMCExpr *LoExpr = MipsMCExpr::create(
1247
5
        MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1248
5
        MCA.getContext());
1249
5
1250
5
    // lui $gp, %hi(__gnu_local_gp)
1251
5
    emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1252
5
1253
5
    // addiu  $gp, $gp, %lo(__gnu_local_gp)
1254
5
    emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1255
5
            &STI);
1256
5
1257
5
    return;
1258
5
  }
1259
5
1260
5
  const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1261
5
      MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1262
5
      MCA.getContext());
1263
5
  const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1264
5
      MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1265
5
      MCA.getContext());
1266
5
1267
5
  // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1268
5
  emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1269
5
1270
5
  // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1271
5
  emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1272
5
          &STI);
1273
5
1274
5
  // daddu  $gp, $gp, $funcreg
1275
5
  emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1276
5
}
1277
1278
void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1279
12
                                                  bool SaveLocationIsRegister) {
1280
12
  // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1281
12
  if (!Pic || 
!(9
getABI().IsN32()9
||
getABI().IsN64()6
))
1282
6
    return;
1283
6
1284
6
  MCInst Inst;
1285
6
  // Either restore the old $gp from a register or on the stack
1286
6
  if (SaveLocationIsRegister) {
1287
2
    Inst.setOpcode(Mips::OR);
1288
2
    Inst.addOperand(MCOperand::createReg(GPReg));
1289
2
    Inst.addOperand(MCOperand::createReg(SaveLocation));
1290
2
    Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1291
4
  } else {
1292
4
    Inst.setOpcode(Mips::LD);
1293
4
    Inst.addOperand(MCOperand::createReg(GPReg));
1294
4
    Inst.addOperand(MCOperand::createReg(Mips::SP));
1295
4
    Inst.addOperand(MCOperand::createImm(SaveLocation));
1296
4
  }
1297
6
  getStreamer().EmitInstruction(Inst, STI);
1298
6
1299
6
  forbidModuleDirective();
1300
6
}
1301
1302
542
void MipsTargetELFStreamer::emitMipsAbiFlags() {
1303
542
  MCAssembler &MCA = getStreamer().getAssembler();
1304
542
  MCContext &Context = MCA.getContext();
1305
542
  MCStreamer &OS = getStreamer();
1306
542
  MCSectionELF *Sec = Context.getELFSection(
1307
542
      ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1308
542
  MCA.registerSection(*Sec);
1309
542
  Sec->setAlignment(8);
1310
542
  OS.SwitchSection(Sec);
1311
542
1312
542
  OS << ABIFlagsSection;
1313
542
}