Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
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//=== MicroMipsSizeReduction.cpp - MicroMips size reduction pass --------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
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//===----------------------------------------------------------------------===//
8
///\file
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/// This pass is used to reduce the size of instructions where applicable.
10
///
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/// TODO: Implement microMIPS64 support.
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//===----------------------------------------------------------------------===//
13
#include "Mips.h"
14
#include "MipsInstrInfo.h"
15
#include "MipsSubtarget.h"
16
#include "llvm/ADT/Statistic.h"
17
#include "llvm/CodeGen/MachineFunctionPass.h"
18
#include "llvm/Support/Debug.h"
19
20
using namespace llvm;
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22
#define DEBUG_TYPE "micromips-reduce-size"
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#define MICROMIPS_SIZE_REDUCE_NAME "MicroMips instruction size reduce pass"
24
25
STATISTIC(NumReduced, "Number of instructions reduced (32-bit to 16-bit ones, "
26
                      "or two instructions into one");
27
28
namespace {
29
30
/// Order of operands to transfer
31
// TODO: Will be extended when additional optimizations are added
32
enum OperandTransfer {
33
  OT_NA,            ///< Not applicable
34
  OT_OperandsAll,   ///< Transfer all operands
35
  OT_Operands02,    ///< Transfer operands 0 and 2
36
  OT_Operand2,      ///< Transfer just operand 2
37
  OT_OperandsXOR,   ///< Transfer operands for XOR16
38
  OT_OperandsLwp,   ///< Transfer operands for LWP
39
  OT_OperandsSwp,   ///< Transfer operands for SWP
40
  OT_OperandsMovep, ///< Transfer operands for MOVEP
41
};
42
43
/// Reduction type
44
// TODO: Will be extended when additional optimizations are added
45
enum ReduceType {
46
  RT_TwoInstr, ///< Reduce two instructions into one instruction
47
  RT_OneInstr  ///< Reduce one instruction into a smaller instruction
48
};
49
50
// Information about immediate field restrictions
51
struct ImmField {
52
0
  ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}
53
  ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
54
           int8_t ImmFieldOperand)
55
      : ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),
56
3.18M
        HBound(HBound) {}
57
  int8_t ImmFieldOperand; // Immediate operand, -1 if it does not exist
58
  uint8_t Shift;          // Shift value
59
  int16_t LBound;         // Low bound of the immediate operand
60
  int16_t HBound;         // High bound of the immediate operand
61
};
62
63
/// Information about operands
64
// TODO: Will be extended when additional optimizations are added
65
struct OpInfo {
66
  OpInfo(enum OperandTransfer TransferOperands)
67
3.18M
      : TransferOperands(TransferOperands) {}
68
0
  OpInfo() : TransferOperands(OT_NA) {}
69
70
  enum OperandTransfer
71
      TransferOperands; ///< Operands to transfer to the new instruction
72
};
73
74
// Information about opcodes
75
struct OpCodes {
76
  OpCodes(unsigned WideOpc, unsigned NarrowOpc)
77
3.18M
      : WideOpc(WideOpc), NarrowOpc(NarrowOpc) {}
78
79
  unsigned WideOpc;   ///< Wide opcode
80
  unsigned NarrowOpc; ///< Narrow opcode
81
};
82
83
typedef struct ReduceEntryFunArgs ReduceEntryFunArgs;
84
85
/// ReduceTable - A static table with information on mapping from wide
86
/// opcodes to narrow
87
struct ReduceEntry {
88
89
  enum ReduceType eRType; ///< Reduction type
90
  bool (*ReduceFunction)(
91
      ReduceEntryFunArgs *Arguments); ///< Pointer to reduce function
92
  struct OpCodes Ops;                 ///< All relevant OpCodes
93
  struct OpInfo OpInf;                ///< Characteristics of operands
94
  struct ImmField Imm;                ///< Characteristics of immediate field
95
96
  ReduceEntry(enum ReduceType RType, struct OpCodes Op,
97
              bool (*F)(ReduceEntryFunArgs *Arguments), struct OpInfo OpInf,
98
              struct ImmField Imm)
99
3.18M
      : eRType(RType), ReduceFunction(F), Ops(Op), OpInf(OpInf), Imm(Imm) {}
100
101
456
  unsigned NarrowOpc() const { return Ops.NarrowOpc; }
102
24.2k
  unsigned WideOpc() const { return Ops.WideOpc; }
103
957
  int16_t LBound() const { return Imm.LBound; }
104
957
  int16_t HBound() const { return Imm.HBound; }
105
957
  uint8_t Shift() const { return Imm.Shift; }
106
1.34k
  int8_t ImmField() const { return Imm.ImmFieldOperand; }
107
456
  enum OperandTransfer TransferOperands() const {
108
456
    return OpInf.TransferOperands;
109
456
  }
110
0
  enum ReduceType RType() const { return eRType; }
111
112
  // operator used by std::equal_range
113
14.1k
  bool operator<(const unsigned int r) const { return (WideOpc() < r); }
114
115
  // operator used by std::equal_range
116
10.1k
  friend bool operator<(const unsigned int r, const struct ReduceEntry &re) {
117
10.1k
    return (r < re.WideOpc());
118
10.1k
  }
119
};
120
121
// Function arguments for ReduceFunction
122
struct ReduceEntryFunArgs {
123
  MachineInstr *MI;         // Instruction
124
  const ReduceEntry &Entry; // Entry field
125
  MachineBasicBlock::instr_iterator
126
      &NextMII; // Iterator to next instruction in block
127
128
  ReduceEntryFunArgs(MachineInstr *argMI, const ReduceEntry &argEntry,
129
                     MachineBasicBlock::instr_iterator &argNextMII)
130
1.61k
      : MI(argMI), Entry(argEntry), NextMII(argNextMII) {}
131
};
132
133
typedef llvm::SmallVector<ReduceEntry, 32> ReduceEntryVector;
134
135
class MicroMipsSizeReduce : public MachineFunctionPass {
136
public:
137
  static char ID;
138
  MicroMipsSizeReduce();
139
140
  static const MipsInstrInfo *MipsII;
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  const MipsSubtarget *Subtarget;
142
143
  bool runOnMachineFunction(MachineFunction &MF) override;
144
145
15.2k
  llvm::StringRef getPassName() const override {
146
15.2k
    return "microMIPS instruction size reduction pass";
147
15.2k
  }
148
149
private:
150
  /// Reduces width of instructions in the specified basic block.
151
  bool ReduceMBB(MachineBasicBlock &MBB);
152
153
  /// Attempts to reduce MI, returns true on success.
154
  bool ReduceMI(const MachineBasicBlock::instr_iterator &MII,
155
                MachineBasicBlock::instr_iterator &NextMII);
156
157
  // Attempts to reduce LW/SW instruction into LWSP/SWSP,
158
  // returns true on success.
159
  static bool ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments);
160
161
  // Attempts to reduce two LW/SW instructions into LWP/SWP instruction,
162
  // returns true on success.
163
  static bool ReduceXWtoXWP(ReduceEntryFunArgs *Arguments);
164
165
  // Attempts to reduce LBU/LHU instruction into LBU16/LHU16,
166
  // returns true on success.
167
  static bool ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments);
168
169
  // Attempts to reduce SB/SH instruction into SB16/SH16,
170
  // returns true on success.
171
  static bool ReduceSXtoSX16(ReduceEntryFunArgs *Arguments);
172
173
  // Attempts to reduce two MOVE instructions into MOVEP instruction,
174
  // returns true on success.
175
  static bool ReduceMoveToMovep(ReduceEntryFunArgs *Arguments);
176
177
  // Attempts to reduce arithmetic instructions, returns true on success.
178
  static bool ReduceArithmeticInstructions(ReduceEntryFunArgs *Arguments);
179
180
  // Attempts to reduce ADDIU into ADDIUSP instruction,
181
  // returns true on success.
182
  static bool ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments);
183
184
  // Attempts to reduce ADDIU into ADDIUR1SP instruction,
185
  // returns true on success.
186
  static bool ReduceADDIUToADDIUR1SP(ReduceEntryFunArgs *Arguments);
187
188
  // Attempts to reduce XOR into XOR16 instruction,
189
  // returns true on success.
190
  static bool ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments);
191
192
  // Changes opcode of an instruction, replaces an instruction with a
193
  // new one, or replaces two instructions with a new instruction
194
  // depending on their order i.e. if these are consecutive forward
195
  // or consecutive backward
196
  static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry,
197
                                 MachineInstr *MI2 = nullptr,
198
                                 bool ConsecutiveForward = true);
199
200
  // Table with transformation rules for each instruction.
201
  static ReduceEntryVector ReduceTable;
202
};
203
204
char MicroMipsSizeReduce::ID = 0;
205
const MipsInstrInfo *MicroMipsSizeReduce::MipsII;
206
207
// This table must be sorted by WideOpc as a main criterion and
208
// ReduceType as a sub-criterion (when wide opcodes are the same).
209
ReduceEntryVector MicroMipsSizeReduce::ReduceTable = {
210
211
    // ReduceType, OpCodes, ReduceFunction,
212
    // OpInfo(TransferOperands),
213
    // ImmField(Shift, LBound, HBound, ImmFieldPosition)
214
    {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
215
     ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
216
    {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
217
     OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
218
    {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
219
     ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
220
    {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
221
     ReduceADDIUToADDIUSP, OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
222
    {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
223
     ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
224
     ImmField(0, 0, 0, -1)},
225
    {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
226
     ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
227
     ImmField(0, 0, 0, -1)},
228
    {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
229
     OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
230
    {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
231
     OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
232
    {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
233
     ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
234
    {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
235
     ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
236
    {RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,
237
     OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
238
    {RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,
239
     OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
240
    {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,
241
     OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
242
    {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
243
     OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
244
    {RT_TwoInstr, OpCodes(Mips::LW16_MM, Mips::LWP_MM), ReduceXWtoXWP,
245
     OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
246
    {RT_TwoInstr, OpCodes(Mips::LW_MM, Mips::LWP_MM), ReduceXWtoXWP,
247
     OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
248
    {RT_OneInstr, OpCodes(Mips::LW_MM, Mips::LWSP_MM), ReduceXWtoXWSP,
249
     OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
250
    {RT_TwoInstr, OpCodes(Mips::MOVE16_MM, Mips::MOVEP_MM), ReduceMoveToMovep,
251
     OpInfo(OT_OperandsMovep), ImmField(0, 0, 0, -1)},
252
    {RT_OneInstr, OpCodes(Mips::SB, Mips::SB16_MM), ReduceSXtoSX16,
253
     OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
254
    {RT_OneInstr, OpCodes(Mips::SB_MM, Mips::SB16_MM), ReduceSXtoSX16,
255
     OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
256
    {RT_OneInstr, OpCodes(Mips::SH, Mips::SH16_MM), ReduceSXtoSX16,
257
     OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
258
    {RT_OneInstr, OpCodes(Mips::SH_MM, Mips::SH16_MM), ReduceSXtoSX16,
259
     OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
260
    {RT_OneInstr, OpCodes(Mips::SUBu, Mips::SUBU16_MM),
261
     ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
262
     ImmField(0, 0, 0, -1)},
263
    {RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),
264
     ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
265
     ImmField(0, 0, 0, -1)},
266
    {RT_TwoInstr, OpCodes(Mips::SW, Mips::SWP_MM), ReduceXWtoXWP,
267
     OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
268
    {RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,
269
     OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
270
    {RT_TwoInstr, OpCodes(Mips::SW16_MM, Mips::SWP_MM), ReduceXWtoXWP,
271
     OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
272
    {RT_TwoInstr, OpCodes(Mips::SW_MM, Mips::SWP_MM), ReduceXWtoXWP,
273
     OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
274
    {RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,
275
     OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
276
    {RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,
277
     OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)},
278
    {RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,
279
     OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)}};
280
} // end anonymous namespace
281
282
INITIALIZE_PASS(MicroMipsSizeReduce, DEBUG_TYPE, MICROMIPS_SIZE_REDUCE_NAME,
283
                false, false)
284
285
// Returns true if the machine operand MO is register SP.
286
558
static bool IsSP(const MachineOperand &MO) {
287
558
  if (MO.isReg() && ((MO.getReg() == Mips::SP)))
288
540
    return true;
289
18
  return false;
290
18
}
291
292
// Returns true if the machine operand MO is register $16, $17, or $2-$7.
293
289
static bool isMMThreeBitGPRegister(const MachineOperand &MO) {
294
289
  if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
295
152
    return true;
296
137
  return false;
297
137
}
298
299
// Returns true if the machine operand MO is register $0, $17, or $2-$7.
300
2
static bool isMMSourceRegister(const MachineOperand &MO) {
301
2
  if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
302
2
    return true;
303
0
  return false;
304
0
}
305
306
// Returns true if the operand Op is an immediate value
307
// and writes the immediate value into variable Imm.
308
1.71k
static bool GetImm(MachineInstr *MI, unsigned Op, int64_t &Imm) {
309
1.71k
310
1.71k
  if (!MI->getOperand(Op).isImm())
311
190
    return false;
312
1.52k
  Imm = MI->getOperand(Op).getImm();
313
1.52k
  return true;
314
1.52k
}
315
316
// Returns true if the value is a valid immediate for ADDIUSP.
317
195
static bool AddiuspImmValue(int64_t Value) {
318
195
  int64_t Value2 = Value >> 2;
319
195
  if (((Value & (int64_t)maskTrailingZeros<uint64_t>(2)) == Value) &&
320
195
      
(181
(181
Value2 >= 2181
&&
Value2 <= 25776
) ||
(106
Value2 >= -258106
&&
Value2 <= -3104
)))
321
155
    return true;
322
40
  return false;
323
40
}
324
325
// Returns true if the variable Value has the number of least-significant zero
326
// bits equal to Shift and if the shifted value is between the bounds.
327
static bool InRange(int64_t Value, unsigned short Shift, int LBound,
328
957
                    int HBound) {
329
957
  int64_t Value2 = Value >> Shift;
330
957
  if (((Value & (int64_t)maskTrailingZeros<uint64_t>(Shift)) == Value) &&
331
957
      
(Value2 >= LBound)943
&&
(Value2 < HBound)838
)
332
778
    return true;
333
179
  return false;
334
179
}
335
336
// Returns true if immediate operand is in range.
337
1.13k
static bool ImmInRange(MachineInstr *MI, const ReduceEntry &Entry) {
338
1.13k
339
1.13k
  int64_t offset;
340
1.13k
341
1.13k
  if (!GetImm(MI, Entry.ImmField(), offset))
342
175
    return false;
343
957
344
957
  if (!InRange(offset, Entry.Shift(), Entry.LBound(), Entry.HBound()))
345
179
    return false;
346
778
347
778
  return true;
348
778
}
349
350
// Returns true if MI can be reduced to lwp/swp instruction
351
static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,
352
834
                          const ReduceEntry &Entry) {
353
834
354
834
  if (ReduceToLwp &&
355
834
      
!(445
MI->getOpcode() == Mips::LW445
||
MI->getOpcode() == Mips::LW_MM291
||
356
445
        
MI->getOpcode() == Mips::LW16_MM123
))
357
99
    return false;
358
735
359
735
  if (!ReduceToLwp &&
360
735
      
!(389
MI->getOpcode() == Mips::SW389
||
MI->getOpcode() == Mips::SW_MM243
||
361
389
        
MI->getOpcode() == Mips::SW16_MM204
))
362
114
    return false;
363
621
364
621
  unsigned reg = MI->getOperand(0).getReg();
365
621
  if (reg == Mips::RA)
366
108
    return false;
367
513
368
513
  if (!ImmInRange(MI, Entry))
369
72
    return false;
370
441
371
441
  if (ReduceToLwp && 
(MI->getOperand(0).getReg() == MI->getOperand(1).getReg())217
)
372
17
    return false;
373
424
374
424
  return true;
375
424
}
376
377
// Returns true if the registers Reg1 and Reg2 are consecutive
378
87
static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
379
87
  static SmallVector<unsigned, 31> Registers = {
380
87
      Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
381
87
      Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6,
382
87
      Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
383
87
      Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP,
384
87
      Mips::SP, Mips::FP, Mips::RA};
385
87
386
1.07k
  for (uint8_t i = 0; i < Registers.size() - 1; 
i++989
) {
387
1.07k
    if (Registers[i] == Reg1) {
388
87
      if (Registers[i + 1] == Reg2)
389
40
        return true;
390
47
      else
391
47
        return false;
392
87
    }
393
1.07k
  }
394
87
  
return false0
;
395
87
}
396
397
// Returns true if registers and offsets are consecutive
398
186
static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) {
399
186
400
186
  int64_t Offset1, Offset2;
401
186
  if (!GetImm(MI1, 2, Offset1))
402
0
    return false;
403
186
  if (!GetImm(MI2, 2, Offset2))
404
0
    return false;
405
186
406
186
  unsigned Reg1 = MI1->getOperand(0).getReg();
407
186
  unsigned Reg2 = MI2->getOperand(0).getReg();
408
186
409
186
  return ((Offset1 == (Offset2 - 4)) && 
(ConsecutiveRegisters(Reg1, Reg2))87
);
410
186
}
411
412
2.09k
MicroMipsSizeReduce::MicroMipsSizeReduce() : MachineFunctionPass(ID) {}
413
414
bool MicroMipsSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII,
415
2.83k
                                   MachineBasicBlock::instr_iterator &NextMII) {
416
2.83k
417
2.83k
  MachineInstr *MI = &*MII;
418
2.83k
  unsigned Opcode = MI->getOpcode();
419
2.83k
420
2.83k
  // Search the table.
421
2.83k
  ReduceEntryVector::const_iterator Start = std::begin(ReduceTable);
422
2.83k
  ReduceEntryVector::const_iterator End = std::end(ReduceTable);
423
2.83k
424
2.83k
  std::pair<ReduceEntryVector::const_iterator,
425
2.83k
            ReduceEntryVector::const_iterator>
426
2.83k
      Range = std::equal_range(Start, End, Opcode);
427
2.83k
428
2.83k
  if (Range.first == Range.second)
429
1.82k
    return false;
430
1.01k
431
1.01k
  for (ReduceEntryVector::const_iterator Entry = Range.first;
432
2.16k
       Entry != Range.second; 
++Entry1.15k
) {
433
1.61k
    ReduceEntryFunArgs Arguments(&(*MII), *Entry, NextMII);
434
1.61k
    if (((*Entry).ReduceFunction)(&Arguments))
435
456
      return true;
436
1.61k
  }
437
1.01k
  
return false554
;
438
1.01k
}
439
440
391
bool MicroMipsSizeReduce::ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments) {
441
391
442
391
  MachineInstr *MI = Arguments->MI;
443
391
  const ReduceEntry &Entry = Arguments->Entry;
444
391
445
391
  if (!ImmInRange(MI, Entry))
446
128
    return false;
447
263
448
263
  if (!IsSP(MI->getOperand(1)))
449
1
    return false;
450
262
451
262
  return ReplaceInstruction(MI, Entry);
452
262
}
453
454
522
bool MicroMipsSizeReduce::ReduceXWtoXWP(ReduceEntryFunArgs *Arguments) {
455
522
456
522
  const ReduceEntry &Entry = Arguments->Entry;
457
522
  MachineBasicBlock::instr_iterator &NextMII = Arguments->NextMII;
458
522
  const MachineBasicBlock::instr_iterator &E =
459
522
      Arguments->MI->getParent()->instr_end();
460
522
461
522
  if (NextMII == E)
462
14
    return false;
463
508
464
508
  MachineInstr *MI1 = Arguments->MI;
465
508
  MachineInstr *MI2 = &*NextMII;
466
508
467
508
  // ReduceToLwp = true/false - reduce to LWP/SWP instruction
468
508
  bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||
469
508
                     
(MI1->getOpcode() == Mips::LW_MM)387
||
470
508
                     
(MI1->getOpcode() == Mips::LW16_MM)240
;
471
508
472
508
  if (!CheckXWPInstr(MI1, ReduceToLwp, Entry))
473
182
    return false;
474
326
475
326
  if (!CheckXWPInstr(MI2, ReduceToLwp, Entry))
476
228
    return false;
477
98
478
98
  unsigned Reg1 = MI1->getOperand(1).getReg();
479
98
  unsigned Reg2 = MI2->getOperand(1).getReg();
480
98
481
98
  if (Reg1 != Reg2)
482
5
    return false;
483
93
484
93
  bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2);
485
93
  bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1);
486
93
487
93
  if (!(ConsecutiveForward || 
ConsecutiveBackward74
))
488
53
    return false;
489
40
490
40
  NextMII = std::next(NextMII);
491
40
  return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);
492
40
}
493
494
bool MicroMipsSizeReduce::ReduceArithmeticInstructions(
495
68
    ReduceEntryFunArgs *Arguments) {
496
68
497
68
  MachineInstr *MI = Arguments->MI;
498
68
  const ReduceEntry &Entry = Arguments->Entry;
499
68
500
68
  if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
501
68
      
!isMMThreeBitGPRegister(MI->getOperand(1))65
||
502
68
      
!isMMThreeBitGPRegister(MI->getOperand(2))65
)
503
62
    return false;
504
6
505
6
  return ReplaceInstruction(MI, Entry);
506
6
}
507
508
bool MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(
509
218
    ReduceEntryFunArgs *Arguments) {
510
218
511
218
  MachineInstr *MI = Arguments->MI;
512
218
  const ReduceEntry &Entry = Arguments->Entry;
513
218
514
218
  if (!ImmInRange(MI, Entry))
515
150
    return false;
516
68
517
68
  if (!isMMThreeBitGPRegister(MI->getOperand(0)) || 
!IsSP(MI->getOperand(1))2
)
518
66
    return false;
519
2
520
2
  return ReplaceInstruction(MI, Entry);
521
2
}
522
523
210
bool MicroMipsSizeReduce::ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments) {
524
210
525
210
  MachineInstr *MI = Arguments->MI;
526
210
  const ReduceEntry &Entry = Arguments->Entry;
527
210
528
210
  int64_t ImmValue;
529
210
  if (!GetImm(MI, Entry.ImmField(), ImmValue))
530
15
    return false;
531
195
532
195
  if (!AddiuspImmValue(ImmValue))
533
40
    return false;
534
155
535
155
  if (!IsSP(MI->getOperand(0)) || 
!IsSP(MI->getOperand(1))138
)
536
17
    return false;
537
138
538
138
  return ReplaceInstruction(MI, Entry);
539
138
}
540
541
6
bool MicroMipsSizeReduce::ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments) {
542
6
543
6
  MachineInstr *MI = Arguments->MI;
544
6
  const ReduceEntry &Entry = Arguments->Entry;
545
6
546
6
  if (!ImmInRange(MI, Entry))
547
2
    return false;
548
4
549
4
  if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
550
4
      !isMMThreeBitGPRegister(MI->getOperand(1)))
551
2
    return false;
552
2
553
2
  return ReplaceInstruction(MI, Entry);
554
2
}
555
556
4
bool MicroMipsSizeReduce::ReduceSXtoSX16(ReduceEntryFunArgs *Arguments) {
557
4
558
4
  MachineInstr *MI = Arguments->MI;
559
4
  const ReduceEntry &Entry = Arguments->Entry;
560
4
561
4
  if (!ImmInRange(MI, Entry))
562
2
    return false;
563
2
564
2
  if (!isMMSourceRegister(MI->getOperand(0)) ||
565
2
      !isMMThreeBitGPRegister(MI->getOperand(1)))
566
0
    return false;
567
2
568
2
  return ReplaceInstruction(MI, Entry);
569
2
}
570
571
// Returns true if Reg can be a source register
572
// of MOVEP instruction
573
188
static bool IsMovepSrcRegister(unsigned Reg) {
574
188
575
188
  if (Reg == Mips::ZERO || Reg == Mips::V0 || 
Reg == Mips::V1171
||
576
188
      
Reg == Mips::S0165
||
Reg == Mips::S1149
||
Reg == Mips::S2145
||
577
188
      
Reg == Mips::S3145
||
Reg == Mips::S4145
)
578
43
    return true;
579
145
580
145
  return false;
581
145
}
582
583
// Returns true if Reg can be a destination register
584
// of MOVEP instruction
585
38
static bool IsMovepDestinationReg(unsigned Reg) {
586
38
587
38
  if (Reg == Mips::A0 || 
Reg == Mips::A129
||
Reg == Mips::A227
||
588
38
      
Reg == Mips::A327
||
Reg == Mips::S527
||
Reg == Mips::S627
)
589
11
    return true;
590
27
591
27
  return false;
592
27
}
593
594
// Returns true if the registers can be a pair of destination
595
// registers in MOVEP instruction
596
8
static bool IsMovepDestinationRegPair(unsigned R0, unsigned R1) {
597
8
598
8
  if ((R0 == Mips::A0 && 
R1 == Mips::S55
) ||
599
8
      (R0 == Mips::A0 && 
R1 == Mips::S65
) ||
600
8
      (R0 == Mips::A0 && 
R1 == Mips::A15
) ||
601
8
      
(5
R0 == Mips::A05
&&
R1 == Mips::A22
) ||
602
8
      
(5
R0 == Mips::A05
&&
R1 == Mips::A32
) ||
603
8
      
(5
R0 == Mips::A15
&&
R1 == Mips::A21
) ||
604
8
      
(5
R0 == Mips::A15
&&
R1 == Mips::A31
) ||
605
8
      
(5
R0 == Mips::A25
&&
R1 == Mips::A30
))
606
3
    return true;
607
5
608
5
  return false;
609
5
}
610
611
183
bool MicroMipsSizeReduce::ReduceMoveToMovep(ReduceEntryFunArgs *Arguments) {
612
183
613
183
  const ReduceEntry &Entry = Arguments->Entry;
614
183
  MachineBasicBlock::instr_iterator &NextMII = Arguments->NextMII;
615
183
  const MachineBasicBlock::instr_iterator &E =
616
183
      Arguments->MI->getParent()->instr_end();
617
183
618
183
  if (NextMII == E)
619
0
    return false;
620
183
621
183
  MachineInstr *MI1 = Arguments->MI;
622
183
  MachineInstr *MI2 = &*NextMII;
623
183
624
183
  unsigned RegDstMI1 = MI1->getOperand(0).getReg();
625
183
  unsigned RegSrcMI1 = MI1->getOperand(1).getReg();
626
183
627
183
  if (!IsMovepSrcRegister(RegSrcMI1))
628
145
    return false;
629
38
630
38
  if (!IsMovepDestinationReg(RegDstMI1))
631
27
    return false;
632
11
633
11
  if (MI2->getOpcode() != Entry.WideOpc())
634
6
    return false;
635
5
636
5
  unsigned RegDstMI2 = MI2->getOperand(0).getReg();
637
5
  unsigned RegSrcMI2 = MI2->getOperand(1).getReg();
638
5
639
5
  if (!IsMovepSrcRegister(RegSrcMI2))
640
0
    return false;
641
5
642
5
  bool ConsecutiveForward;
643
5
  if (IsMovepDestinationRegPair(RegDstMI1, RegDstMI2)) {
644
2
    ConsecutiveForward = true;
645
3
  } else if (IsMovepDestinationRegPair(RegDstMI2, RegDstMI1)) {
646
1
    ConsecutiveForward = false;
647
1
  } else
648
2
    return false;
649
3
650
3
  NextMII = std::next(NextMII);
651
3
  return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);
652
3
}
653
654
9
bool MicroMipsSizeReduce::ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments) {
655
9
656
9
  MachineInstr *MI = Arguments->MI;
657
9
  const ReduceEntry &Entry = Arguments->Entry;
658
9
659
9
  if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
660
9
      
!isMMThreeBitGPRegister(MI->getOperand(1))2
||
661
9
      
!isMMThreeBitGPRegister(MI->getOperand(2))2
)
662
7
    return false;
663
2
664
2
  if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
665
2
      
!(MI->getOperand(0).getReg() == MI->getOperand(1).getReg())1
)
666
1
    return false;
667
1
668
1
  return ReplaceInstruction(MI, Entry);
669
1
}
670
671
520
bool MicroMipsSizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
672
520
  bool Modified = false;
673
520
  MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
674
520
                                    E = MBB.instr_end();
675
520
  MachineBasicBlock::instr_iterator NextMII;
676
520
677
520
  // Iterate through the instructions in the basic block
678
3.54k
  for (; MII != E; 
MII = NextMII3.02k
) {
679
3.02k
    NextMII = std::next(MII);
680
3.02k
    MachineInstr *MI = &*MII;
681
3.02k
682
3.02k
    // Don't reduce bundled instructions or pseudo operations
683
3.02k
    if (MI->isBundle() || MI->isTransient())
684
192
      continue;
685
2.83k
686
2.83k
    // Try to reduce 32-bit instruction into 16-bit instruction
687
2.83k
    Modified |= ReduceMI(MII, NextMII);
688
2.83k
  }
689
520
690
520
  return Modified;
691
520
}
692
693
bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
694
                                             const ReduceEntry &Entry,
695
                                             MachineInstr *MI2,
696
456
                                             bool ConsecutiveForward) {
697
456
698
456
  enum OperandTransfer OpTransfer = Entry.TransferOperands();
699
456
700
456
  LLVM_DEBUG(dbgs() << "Converting 32-bit: " << *MI);
701
456
  ++NumReduced;
702
456
703
456
  if (OpTransfer == OT_OperandsAll) {
704
272
    MI->setDesc(MipsII->get(Entry.NarrowOpc()));
705
272
    LLVM_DEBUG(dbgs() << "       to 16-bit: " << *MI);
706
272
    return true;
707
272
  } else {
708
184
    MachineBasicBlock &MBB = *MI->getParent();
709
184
    const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc());
710
184
    DebugLoc dl = MI->getDebugLoc();
711
184
    MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
712
184
    switch (OpTransfer) {
713
184
    case OT_Operand2:
714
138
      MIB.add(MI->getOperand(2));
715
138
      break;
716
184
    case OT_Operands02: {
717
2
      MIB.add(MI->getOperand(0));
718
2
      MIB.add(MI->getOperand(2));
719
2
      break;
720
184
    }
721
184
    case OT_OperandsXOR: {
722
1
      if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
723
1
        MIB.add(MI->getOperand(0));
724
1
        MIB.add(MI->getOperand(1));
725
1
        MIB.add(MI->getOperand(2));
726
1
      } else {
727
0
        MIB.add(MI->getOperand(0));
728
0
        MIB.add(MI->getOperand(2));
729
0
        MIB.add(MI->getOperand(1));
730
0
      }
731
1
      break;
732
184
    }
733
184
    case OT_OperandsMovep:
734
43
    case OT_OperandsLwp:
735
43
    case OT_OperandsSwp: {
736
43
      if (ConsecutiveForward) {
737
21
        MIB.add(MI->getOperand(0));
738
21
        MIB.add(MI2->getOperand(0));
739
21
        MIB.add(MI->getOperand(1));
740
21
        if (OpTransfer == OT_OperandsMovep)
741
2
          MIB.add(MI2->getOperand(1));
742
19
        else
743
19
          MIB.add(MI->getOperand(2));
744
22
      } else { // consecutive backward
745
22
        MIB.add(MI2->getOperand(0));
746
22
        MIB.add(MI->getOperand(0));
747
22
        MIB.add(MI2->getOperand(1));
748
22
        if (OpTransfer == OT_OperandsMovep)
749
1
          MIB.add(MI->getOperand(1));
750
21
        else
751
21
          MIB.add(MI2->getOperand(2));
752
22
      }
753
43
754
43
      LLVM_DEBUG(dbgs() << "and converting 32-bit: " << *MI2
755
43
                        << "       to: " << *MIB);
756
43
757
43
      MBB.erase_instr(MI);
758
43
      MBB.erase_instr(MI2);
759
43
      return true;
760
43
    }
761
43
    default:
762
0
      llvm_unreachable("Unknown operand transfer!");
763
141
    }
764
141
765
141
    // Transfer MI flags.
766
141
    MIB.setMIFlags(MI->getFlags());
767
141
768
141
    LLVM_DEBUG(dbgs() << "       to 16-bit: " << *MIB);
769
141
    MBB.erase_instr(MI);
770
141
    return true;
771
141
  }
772
0
  return false;
773
0
}
774
775
13.2k
bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
776
13.2k
777
13.2k
  Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
778
13.2k
779
13.2k
  // TODO: Add support for the subtarget microMIPS32R6.
780
13.2k
  if (!Subtarget->inMicroMipsMode() || 
!Subtarget->hasMips32r2()900
||
781
13.2k
      
Subtarget->hasMips32r6()812
)
782
12.7k
    return false;
783
434
784
434
  MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
785
434
786
434
  bool Modified = false;
787
434
  MachineFunction::iterator I = MF.begin(), E = MF.end();
788
434
789
954
  for (; I != E; 
++I520
)
790
520
    Modified |= ReduceMBB(*I);
791
434
  return Modified;
792
434
}
793
794
/// Returns an instance of the MicroMips size reduction pass.
795
2.09k
FunctionPass *llvm::createMicroMipsSizeReducePass() {
796
2.09k
  return new MicroMipsSizeReduce();
797
2.09k
}