Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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Source (jump to first uncovered line)
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//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// Subclass of MipsTargetLowering specialized for mips16.
10
//
11
//===----------------------------------------------------------------------===//
12
#include "Mips16ISelLowering.h"
13
#include "MCTargetDesc/MipsBaseInfo.h"
14
#include "Mips16HardFloatInfo.h"
15
#include "MipsMachineFunction.h"
16
#include "MipsRegisterInfo.h"
17
#include "MipsTargetMachine.h"
18
#include "llvm/CodeGen/MachineInstrBuilder.h"
19
#include "llvm/CodeGen/TargetInstrInfo.h"
20
#include "llvm/Support/CommandLine.h"
21
22
using namespace llvm;
23
24
#define DEBUG_TYPE "mips-lower"
25
26
static cl::opt<bool> DontExpandCondPseudos16(
27
  "mips16-dont-expand-cond-pseudo",
28
  cl::init(false),
29
  cl::desc("Don't expand conditional move related "
30
           "pseudos for Mips 16"),
31
  cl::Hidden);
32
33
namespace {
34
struct Mips16Libcall {
35
  RTLIB::Libcall Libcall;
36
  const char *Name;
37
38
5.52k
  bool operator<(const Mips16Libcall &RHS) const {
39
5.52k
    return std::strcmp(Name, RHS.Name) < 0;
40
5.52k
  }
41
};
42
43
struct Mips16IntrinsicHelperType{
44
  const char* Name;
45
  const char* Helper;
46
47
948
  bool operator<(const Mips16IntrinsicHelperType &RHS) const {
48
948
    return std::strcmp(Name, RHS.Name) < 0;
49
948
  }
50
190
  bool operator==(const Mips16IntrinsicHelperType &RHS) const {
51
190
    return std::strcmp(Name, RHS.Name) == 0;
52
190
  }
53
};
54
}
55
56
// Libcalls for which no helper is generated. Sorted by name for binary search.
57
static const Mips16Libcall HardFloatLibCalls[] = {
58
  { RTLIB::ADD_F64, "__mips16_adddf3" },
59
  { RTLIB::ADD_F32, "__mips16_addsf3" },
60
  { RTLIB::DIV_F64, "__mips16_divdf3" },
61
  { RTLIB::DIV_F32, "__mips16_divsf3" },
62
  { RTLIB::OEQ_F64, "__mips16_eqdf2" },
63
  { RTLIB::OEQ_F32, "__mips16_eqsf2" },
64
  { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
65
  { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
66
  { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
67
  { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
68
  { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
69
  { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
70
  { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
71
  { RTLIB::OGE_F64, "__mips16_gedf2" },
72
  { RTLIB::OGE_F32, "__mips16_gesf2" },
73
  { RTLIB::OGT_F64, "__mips16_gtdf2" },
74
  { RTLIB::OGT_F32, "__mips16_gtsf2" },
75
  { RTLIB::OLE_F64, "__mips16_ledf2" },
76
  { RTLIB::OLE_F32, "__mips16_lesf2" },
77
  { RTLIB::OLT_F64, "__mips16_ltdf2" },
78
  { RTLIB::OLT_F32, "__mips16_ltsf2" },
79
  { RTLIB::MUL_F64, "__mips16_muldf3" },
80
  { RTLIB::MUL_F32, "__mips16_mulsf3" },
81
  { RTLIB::UNE_F64, "__mips16_nedf2" },
82
  { RTLIB::UNE_F32, "__mips16_nesf2" },
83
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
84
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
85
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
86
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
87
  { RTLIB::SUB_F64, "__mips16_subdf3" },
88
  { RTLIB::SUB_F32, "__mips16_subsf3" },
89
  { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
90
  { RTLIB::UO_F64, "__mips16_unorddf2" },
91
  { RTLIB::UO_F32, "__mips16_unordsf2" }
92
};
93
94
static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
95
  {"__fixunsdfsi", "__mips16_call_stub_2" },
96
  {"ceil",  "__mips16_call_stub_df_2"},
97
  {"ceilf", "__mips16_call_stub_sf_1"},
98
  {"copysign",  "__mips16_call_stub_df_10"},
99
  {"copysignf", "__mips16_call_stub_sf_5"},
100
  {"cos",  "__mips16_call_stub_df_2"},
101
  {"cosf", "__mips16_call_stub_sf_1"},
102
  {"exp2",  "__mips16_call_stub_df_2"},
103
  {"exp2f", "__mips16_call_stub_sf_1"},
104
  {"floor",  "__mips16_call_stub_df_2"},
105
  {"floorf", "__mips16_call_stub_sf_1"},
106
  {"log2",  "__mips16_call_stub_df_2"},
107
  {"log2f", "__mips16_call_stub_sf_1"},
108
  {"nearbyint",  "__mips16_call_stub_df_2"},
109
  {"nearbyintf", "__mips16_call_stub_sf_1"},
110
  {"rint",  "__mips16_call_stub_df_2"},
111
  {"rintf", "__mips16_call_stub_sf_1"},
112
  {"sin",  "__mips16_call_stub_df_2"},
113
  {"sinf", "__mips16_call_stub_sf_1"},
114
  {"sqrt",  "__mips16_call_stub_df_2"},
115
  {"sqrtf", "__mips16_call_stub_sf_1"},
116
  {"trunc",  "__mips16_call_stub_df_2"},
117
  {"truncf", "__mips16_call_stub_sf_1"},
118
};
119
120
Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
121
                                           const MipsSubtarget &STI)
122
2.91k
    : MipsTargetLowering(TM, STI) {
123
2.91k
124
2.91k
  // Set up the register classes
125
2.91k
  addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
126
2.91k
127
2.91k
  if (!Subtarget.useSoftFloat())
128
2.73k
    setMips16HardFloatLibCalls();
129
2.91k
130
2.91k
  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);
131
2.91k
  setOperationAction(ISD::ATOMIC_CMP_SWAP,    MVT::i32,   Expand);
132
2.91k
  setOperationAction(ISD::ATOMIC_SWAP,        MVT::i32,   Expand);
133
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_ADD,    MVT::i32,   Expand);
134
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_SUB,    MVT::i32,   Expand);
135
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_AND,    MVT::i32,   Expand);
136
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_OR,     MVT::i32,   Expand);
137
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_XOR,    MVT::i32,   Expand);
138
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_NAND,   MVT::i32,   Expand);
139
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_MIN,    MVT::i32,   Expand);
140
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_MAX,    MVT::i32,   Expand);
141
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_UMIN,   MVT::i32,   Expand);
142
2.91k
  setOperationAction(ISD::ATOMIC_LOAD_UMAX,   MVT::i32,   Expand);
143
2.91k
144
2.91k
  setOperationAction(ISD::ROTR, MVT::i32,  Expand);
145
2.91k
  setOperationAction(ISD::ROTR, MVT::i64,  Expand);
146
2.91k
  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
147
2.91k
  setOperationAction(ISD::BSWAP, MVT::i64, Expand);
148
2.91k
149
2.91k
  computeRegisterProperties(STI.getRegisterInfo());
150
2.91k
}
151
152
const MipsTargetLowering *
153
llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
154
2.91k
                                 const MipsSubtarget &STI) {
155
2.91k
  return new Mips16TargetLowering(TM, STI);
156
2.91k
}
157
158
bool Mips16TargetLowering::allowsMisalignedMemoryAccesses(
159
39
    EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
160
39
  return false;
161
39
}
162
163
MachineBasicBlock *
164
Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
165
182
                                                  MachineBasicBlock *BB) const {
166
182
  switch (MI.getOpcode()) {
167
182
  default:
168
0
    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
169
182
  case Mips::SelBeqZ:
170
4
    return emitSel16(Mips::BeqzRxImm16, MI, BB);
171
182
  case Mips::SelBneZ:
172
6
    return emitSel16(Mips::BnezRxImm16, MI, BB);
173
182
  case Mips::SelTBteqZCmpi:
174
5
    return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
175
182
  case Mips::SelTBteqZSlti:
176
0
    return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
177
182
  case Mips::SelTBteqZSltiu:
178
0
    return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
179
182
  case Mips::SelTBtneZCmpi:
180
5
    return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
181
182
  case Mips::SelTBtneZSlti:
182
3
    return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
183
182
  case Mips::SelTBtneZSltiu:
184
0
    return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
185
182
  case Mips::SelTBteqZCmp:
186
3
    return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
187
182
  case Mips::SelTBteqZSlt:
188
8
    return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
189
182
  case Mips::SelTBteqZSltu:
190
8
    return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
191
182
  case Mips::SelTBtneZCmp:
192
3
    return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
193
182
  case Mips::SelTBtneZSlt:
194
6
    return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
195
182
  case Mips::SelTBtneZSltu:
196
4
    return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
197
182
  case Mips::BteqzT8CmpX16:
198
5
    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
199
182
  case Mips::BteqzT8SltX16:
200
12
    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
201
182
  case Mips::BteqzT8SltuX16:
202
0
    // TBD: figure out a way to get this or remove the instruction
203
0
    // altogether.
204
0
    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
205
182
  case Mips::BtnezT8CmpX16:
206
9
    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
207
182
  case Mips::BtnezT8SltX16:
208
13
    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
209
182
  case Mips::BtnezT8SltuX16:
210
0
    // TBD: figure out a way to get this or remove the instruction
211
0
    // altogether.
212
0
    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
213
182
  case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
214
5
    Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
215
182
  case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
216
0
    Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
217
182
  case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
218
0
    Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
219
182
  case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
220
6
    Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
221
182
  case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
222
7
    Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
223
182
  case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
224
0
    Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
225
182
    
break0
;
226
182
  case Mips::SltCCRxRy16:
227
11
    return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
228
182
    
break0
;
229
182
  case Mips::SltiCCRxImmX16:
230
10
    return emitFEXT_CCRXI16_ins
231
10
      (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
232
182
  case Mips::SltiuCCRxImmX16:
233
30
    return emitFEXT_CCRXI16_ins
234
30
      (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
235
182
  case Mips::SltuCCRxRy16:
236
19
    return emitFEXT_CCRX16_ins
237
19
      (Mips::SltuRxRy16, MI, BB);
238
182
  }
239
182
}
240
241
bool Mips16TargetLowering::isEligibleForTailCallOptimization(
242
    const CCState &CCInfo, unsigned NextStackOffset,
243
14
    const MipsFunctionInfo &FI) const {
244
14
  // No tail call optimization for mips16.
245
14
  return false;
246
14
}
247
248
2.73k
void Mips16TargetLowering::setMips16HardFloatLibCalls() {
249
95.8k
  for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); 
++I93.0k
) {
250
93.0k
    assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
251
93.0k
           "Array not sorted!");
252
93.0k
    if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
253
82.1k
      setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
254
93.0k
  }
255
2.73k
256
2.73k
  setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
257
2.73k
  setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
258
2.73k
}
259
260
//
261
// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
262
// cleaner way to do all of this but it will have to wait until the traditional
263
// gcc mechanism is completed.
264
//
265
// For Pic, in order for Mips16 code to call Mips32 code which according the abi
266
// have either arguments or returned values placed in floating point registers,
267
// we use a set of helper functions. (This includes functions which return type
268
//  complex which on Mips are returned in a pair of floating point registers).
269
//
270
// This is an encoding that we inherited from gcc.
271
// In Mips traditional O32, N32 ABI, floating point numbers are passed in
272
// floating point argument registers 1,2 only when the first and optionally
273
// the second arguments are float (sf) or double (df).
274
// For Mips16 we are only concerned with the situations where floating point
275
// arguments are being passed in floating point registers by the ABI, because
276
// Mips16 mode code cannot execute floating point instructions to load those
277
// values and hence helper functions are needed.
278
// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
279
// the helper function suffixs for these are:
280
//                        0,  1,    5,        9,         2,   6,        10
281
// this suffix can then be calculated as follows:
282
// for a given argument Arg:
283
//     Arg1x, Arg2x = 1 :  Arg is sf
284
//                    2 :  Arg is df
285
//                    0:   Arg is neither sf or df
286
// So this stub is the string for number Arg1x + Arg2x*4.
287
// However not all numbers between 0 and 10 are possible, we check anyway and
288
// assert if the impossible exists.
289
//
290
291
unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
292
794
  (ArgListTy &Args) const {
293
794
  unsigned int resultNum = 0;
294
794
  if (Args.size() >= 1) {
295
363
    Type *t = Args[0].Ty;
296
363
    if (t->isFloatTy()) {
297
66
      resultNum = 1;
298
66
    }
299
297
    else if (t->isDoubleTy()) {
300
64
      resultNum = 2;
301
64
    }
302
363
  }
303
794
  if (resultNum) {
304
130
    if (Args.size() >=2) {
305
42
      Type *t = Args[1].Ty;
306
42
      if (t->isFloatTy()) {
307
26
        resultNum += 4;
308
26
      }
309
16
      else if (t->isDoubleTy()) {
310
16
        resultNum += 8;
311
16
      }
312
42
    }
313
130
  }
314
794
  return resultNum;
315
794
}
316
317
//
318
// Prefixes are attached to stub numbers depending on the return type.
319
// return type: float  sf_
320
//              double df_
321
//              single complex sc_
322
//              double complext dc_
323
//              others  NO PREFIX
324
//
325
//
326
// The full name of a helper function is__mips16_call_stub +
327
//    return type dependent prefix + stub number
328
//
329
// FIXME: This is something that probably should be in a different source file
330
// and perhaps done differently but my main purpose is to not waste runtime
331
// on something that we can enumerate in the source. Another possibility is
332
// to have a python script to generate these mapping tables. This will do
333
// for now. There are a whole series of helper function mapping arrays, one
334
// for each return type class as outlined above. There there are 11 possible
335
// entries. Ones with 0 are ones which should never be selected.
336
//
337
// All the arrays are similar except for ones which return neither
338
// sf, df, sc, dc, in which we only care about ones which have sf or df as a
339
// first parameter.
340
//
341
#define P_ "__mips16_call_stub_"
342
#define MAX_STUB_NUMBER 10
343
#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
344
#define T P "0" , T1
345
#define P P_
346
static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
347
  {nullptr, T1 };
348
#undef P
349
#define P P_ "sf_"
350
static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
351
  { T };
352
#undef P
353
#define P P_ "df_"
354
static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
355
  { T };
356
#undef P
357
#define P P_ "sc_"
358
static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
359
  { T };
360
#undef P
361
#define P P_ "dc_"
362
static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
363
  { T };
364
#undef P
365
#undef P_
366
367
368
const char* Mips16TargetLowering::
369
  getMips16HelperFunction
370
794
    (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
371
794
  const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
372
#ifndef NDEBUG
373
  const unsigned int maxStubNum = 10;
374
  assert(stubNum <= maxStubNum);
375
  const bool validStubNum[maxStubNum+1] =
376
    {true, true, true, false, false, true, true, false, false, true, true};
377
  assert(validStubNum[stubNum]);
378
#endif
379
  const char *result;
380
794
  if (RetTy->isFloatTy()) {
381
38
    result = sfMips16Helper[stubNum];
382
38
  }
383
756
  else if (RetTy ->isDoubleTy()) {
384
27
    result = dfMips16Helper[stubNum];
385
729
  } else if (StructType *SRetTy = dyn_cast<StructType>(RetTy)) {
386
30
    // check if it's complex
387
30
    if (SRetTy->getNumElements() == 2) {
388
30
      if ((SRetTy->getElementType(0)->isFloatTy()) &&
389
30
          
(SRetTy->getElementType(1)->isFloatTy())15
) {
390
15
        result = scMips16Helper[stubNum];
391
15
      } else if ((SRetTy->getElementType(0)->isDoubleTy()) &&
392
15
                 (SRetTy->getElementType(1)->isDoubleTy())) {
393
15
        result = dcMips16Helper[stubNum];
394
15
      } else {
395
0
        llvm_unreachable("Uncovered condition");
396
0
      }
397
0
    } else {
398
0
      llvm_unreachable("Uncovered condition");
399
0
    }
400
699
  } else {
401
699
    if (stubNum == 0) {
402
641
      needHelper = false;
403
641
      return "";
404
641
    }
405
58
    result = vMips16Helper[stubNum];
406
58
  }
407
794
  needHelper = true;
408
153
  return result;
409
794
}
410
411
void Mips16TargetLowering::
412
getOpndList(SmallVectorImpl<SDValue> &Ops,
413
            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
414
            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
415
            bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
416
1.00k
            SDValue Chain) const {
417
1.00k
  SelectionDAG &DAG = CLI.DAG;
418
1.00k
  MachineFunction &MF = DAG.getMachineFunction();
419
1.00k
  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
420
1.00k
  const char* Mips16HelperFunction = nullptr;
421
1.00k
  bool NeedMips16Helper = false;
422
1.00k
423
1.00k
  if (Subtarget.inMips16HardFloat()) {
424
1.00k
    //
425
1.00k
    // currently we don't have symbols tagged with the mips16 or mips32
426
1.00k
    // qualifier so we will assume that we don't know what kind it is.
427
1.00k
    // and generate the helper
428
1.00k
    //
429
1.00k
    bool LookupHelper = true;
430
1.00k
    if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
431
344
      Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
432
344
433
344
      if (std::binary_search(std::begin(HardFloatLibCalls),
434
344
                             std::end(HardFloatLibCalls), Find))
435
154
        LookupHelper = false;
436
190
      else {
437
190
        const char *Symbol = S->getSymbol();
438
190
        Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
439
190
        const Mips16HardFloatInfo::FuncSignature *Signature =
440
190
            Mips16HardFloatInfo::findFuncSignature(Symbol);
441
190
        if (!IsPICCall && 
(164
Signature164
&& (FuncInfo->StubsNeeded.find(Symbol) ==
442
100
                                         FuncInfo->StubsNeeded.end()))) {
443
100
          FuncInfo->StubsNeeded[Symbol] = Signature;
444
100
          //
445
100
          // S2 is normally saved if the stub is for a function which
446
100
          // returns a float or double value and is not otherwise. This is
447
100
          // because more work is required after the function the stub
448
100
          // is calling completes, and so the stub cannot directly return
449
100
          // and the stub has no stack space to store the return address so
450
100
          // S2 is used for that purpose.
451
100
          // In order to take advantage of not saving S2, we need to also
452
100
          // optimize the call in the stub and this requires some further
453
100
          // functionality in MipsAsmPrinter which we don't have yet.
454
100
          // So for now we always save S2. The optimization will be done
455
100
          // in a follow-on patch.
456
100
          //
457
100
          if (1 || 
(Signature->RetSig != Mips16HardFloatInfo::NoFPRet)0
)
458
100
            FuncInfo->setSaveS2();
459
100
        }
460
190
        // one more look at list of intrinsics
461
190
        const Mips16IntrinsicHelperType *Helper =
462
190
            llvm::lower_bound(Mips16IntrinsicHelper, IntrinsicFind);
463
190
        if (Helper != std::end(Mips16IntrinsicHelper) &&
464
190
            *Helper == IntrinsicFind) {
465
24
          Mips16HelperFunction = Helper->Helper;
466
24
          NeedMips16Helper = true;
467
24
          LookupHelper = false;
468
24
        }
469
190
470
190
      }
471
658
    } else if (GlobalAddressSDNode *G =
472
654
                   dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
473
654
      Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
474
654
                             G->getGlobal()->getName().data() };
475
654
476
654
      if (std::binary_search(std::begin(HardFloatLibCalls),
477
654
                             std::end(HardFloatLibCalls), Find))
478
30
        LookupHelper = false;
479
654
    }
480
1.00k
    if (LookupHelper)
481
794
      Mips16HelperFunction =
482
794
        getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
483
1.00k
  }
484
1.00k
485
1.00k
  SDValue JumpTarget = Callee;
486
1.00k
487
1.00k
  // T9 should contain the address of the callee function if
488
1.00k
  // -relocation-model=pic or it is an indirect call.
489
1.00k
  if (IsPICCall || 
!GlobalOrExternal406
) {
490
598
    unsigned V0Reg = Mips::V0;
491
598
    if (NeedMips16Helper) {
492
91
      RegsToPass.push_front(std::make_pair(V0Reg, Callee));
493
91
      JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
494
91
                                         getPointerTy(DAG.getDataLayout()));
495
91
      ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
496
91
      JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG,
497
91
                                 MipsII::MO_GOT, Chain,
498
91
                                 FuncInfo->callPtrInfo(S->getSymbol()));
499
91
    } else
500
507
      RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
501
598
  }
502
1.00k
503
1.00k
  Ops.push_back(JumpTarget);
504
1.00k
505
1.00k
  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
506
1.00k
                                  InternalLinkage, IsCallReloc, CLI, Callee,
507
1.00k
                                  Chain);
508
1.00k
}
509
510
MachineBasicBlock *
511
Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
512
10
                                MachineBasicBlock *BB) const {
513
10
  if (DontExpandCondPseudos16)
514
0
    return BB;
515
10
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
516
10
  DebugLoc DL = MI.getDebugLoc();
517
10
  // To "insert" a SELECT_CC instruction, we actually have to insert the
518
10
  // diamond control-flow pattern.  The incoming instruction knows the
519
10
  // destination vreg to set, the condition code register to branch on, the
520
10
  // true/false values to select between, and a branch opcode to use.
521
10
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
522
10
  MachineFunction::iterator It = ++BB->getIterator();
523
10
524
10
  //  thisMBB:
525
10
  //  ...
526
10
  //   TrueVal = ...
527
10
  //   setcc r1, r2, r3
528
10
  //   bNE   r1, r0, copy1MBB
529
10
  //   fallthrough --> copy0MBB
530
10
  MachineBasicBlock *thisMBB  = BB;
531
10
  MachineFunction *F = BB->getParent();
532
10
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
533
10
  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
534
10
  F->insert(It, copy0MBB);
535
10
  F->insert(It, sinkMBB);
536
10
537
10
  // Transfer the remainder of BB and its successor edges to sinkMBB.
538
10
  sinkMBB->splice(sinkMBB->begin(), BB,
539
10
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
540
10
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
541
10
542
10
  // Next, add the true and fallthrough blocks as its successors.
543
10
  BB->addSuccessor(copy0MBB);
544
10
  BB->addSuccessor(sinkMBB);
545
10
546
10
  BuildMI(BB, DL, TII->get(Opc))
547
10
      .addReg(MI.getOperand(3).getReg())
548
10
      .addMBB(sinkMBB);
549
10
550
10
  //  copy0MBB:
551
10
  //   %FalseValue = ...
552
10
  //   # fallthrough to sinkMBB
553
10
  BB = copy0MBB;
554
10
555
10
  // Update machine-CFG edges
556
10
  BB->addSuccessor(sinkMBB);
557
10
558
10
  //  sinkMBB:
559
10
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
560
10
  //  ...
561
10
  BB = sinkMBB;
562
10
563
10
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
564
10
      .addReg(MI.getOperand(1).getReg())
565
10
      .addMBB(thisMBB)
566
10
      .addReg(MI.getOperand(2).getReg())
567
10
      .addMBB(copy0MBB);
568
10
569
10
  MI.eraseFromParent(); // The pseudo instruction is gone now.
570
10
  return BB;
571
10
}
572
573
MachineBasicBlock *
574
Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
575
32
                                 MachineBasicBlock *BB) const {
576
32
  if (DontExpandCondPseudos16)
577
0
    return BB;
578
32
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
579
32
  DebugLoc DL = MI.getDebugLoc();
580
32
  // To "insert" a SELECT_CC instruction, we actually have to insert the
581
32
  // diamond control-flow pattern.  The incoming instruction knows the
582
32
  // destination vreg to set, the condition code register to branch on, the
583
32
  // true/false values to select between, and a branch opcode to use.
584
32
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
585
32
  MachineFunction::iterator It = ++BB->getIterator();
586
32
587
32
  //  thisMBB:
588
32
  //  ...
589
32
  //   TrueVal = ...
590
32
  //   setcc r1, r2, r3
591
32
  //   bNE   r1, r0, copy1MBB
592
32
  //   fallthrough --> copy0MBB
593
32
  MachineBasicBlock *thisMBB  = BB;
594
32
  MachineFunction *F = BB->getParent();
595
32
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
596
32
  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
597
32
  F->insert(It, copy0MBB);
598
32
  F->insert(It, sinkMBB);
599
32
600
32
  // Transfer the remainder of BB and its successor edges to sinkMBB.
601
32
  sinkMBB->splice(sinkMBB->begin(), BB,
602
32
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
603
32
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
604
32
605
32
  // Next, add the true and fallthrough blocks as its successors.
606
32
  BB->addSuccessor(copy0MBB);
607
32
  BB->addSuccessor(sinkMBB);
608
32
609
32
  BuildMI(BB, DL, TII->get(Opc2))
610
32
      .addReg(MI.getOperand(3).getReg())
611
32
      .addReg(MI.getOperand(4).getReg());
612
32
  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
613
32
614
32
  //  copy0MBB:
615
32
  //   %FalseValue = ...
616
32
  //   # fallthrough to sinkMBB
617
32
  BB = copy0MBB;
618
32
619
32
  // Update machine-CFG edges
620
32
  BB->addSuccessor(sinkMBB);
621
32
622
32
  //  sinkMBB:
623
32
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
624
32
  //  ...
625
32
  BB = sinkMBB;
626
32
627
32
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
628
32
      .addReg(MI.getOperand(1).getReg())
629
32
      .addMBB(thisMBB)
630
32
      .addReg(MI.getOperand(2).getReg())
631
32
      .addMBB(copy0MBB);
632
32
633
32
  MI.eraseFromParent(); // The pseudo instruction is gone now.
634
32
  return BB;
635
32
636
32
}
637
638
MachineBasicBlock *
639
Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
640
                                  MachineInstr &MI,
641
13
                                  MachineBasicBlock *BB) const {
642
13
  if (DontExpandCondPseudos16)
643
0
    return BB;
644
13
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
645
13
  DebugLoc DL = MI.getDebugLoc();
646
13
  // To "insert" a SELECT_CC instruction, we actually have to insert the
647
13
  // diamond control-flow pattern.  The incoming instruction knows the
648
13
  // destination vreg to set, the condition code register to branch on, the
649
13
  // true/false values to select between, and a branch opcode to use.
650
13
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
651
13
  MachineFunction::iterator It = ++BB->getIterator();
652
13
653
13
  //  thisMBB:
654
13
  //  ...
655
13
  //   TrueVal = ...
656
13
  //   setcc r1, r2, r3
657
13
  //   bNE   r1, r0, copy1MBB
658
13
  //   fallthrough --> copy0MBB
659
13
  MachineBasicBlock *thisMBB  = BB;
660
13
  MachineFunction *F = BB->getParent();
661
13
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
662
13
  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
663
13
  F->insert(It, copy0MBB);
664
13
  F->insert(It, sinkMBB);
665
13
666
13
  // Transfer the remainder of BB and its successor edges to sinkMBB.
667
13
  sinkMBB->splice(sinkMBB->begin(), BB,
668
13
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
669
13
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
670
13
671
13
  // Next, add the true and fallthrough blocks as its successors.
672
13
  BB->addSuccessor(copy0MBB);
673
13
  BB->addSuccessor(sinkMBB);
674
13
675
13
  BuildMI(BB, DL, TII->get(Opc2))
676
13
      .addReg(MI.getOperand(3).getReg())
677
13
      .addImm(MI.getOperand(4).getImm());
678
13
  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
679
13
680
13
  //  copy0MBB:
681
13
  //   %FalseValue = ...
682
13
  //   # fallthrough to sinkMBB
683
13
  BB = copy0MBB;
684
13
685
13
  // Update machine-CFG edges
686
13
  BB->addSuccessor(sinkMBB);
687
13
688
13
  //  sinkMBB:
689
13
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
690
13
  //  ...
691
13
  BB = sinkMBB;
692
13
693
13
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
694
13
      .addReg(MI.getOperand(1).getReg())
695
13
      .addMBB(thisMBB)
696
13
      .addReg(MI.getOperand(2).getReg())
697
13
      .addMBB(copy0MBB);
698
13
699
13
  MI.eraseFromParent(); // The pseudo instruction is gone now.
700
13
  return BB;
701
13
702
13
}
703
704
MachineBasicBlock *
705
Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
706
                                          MachineInstr &MI,
707
39
                                          MachineBasicBlock *BB) const {
708
39
  if (DontExpandCondPseudos16)
709
0
    return BB;
710
39
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
711
39
  unsigned regX = MI.getOperand(0).getReg();
712
39
  unsigned regY = MI.getOperand(1).getReg();
713
39
  MachineBasicBlock *target = MI.getOperand(2).getMBB();
714
39
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
715
39
      .addReg(regX)
716
39
      .addReg(regY);
717
39
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
718
39
  MI.eraseFromParent(); // The pseudo instruction is gone now.
719
39
  return BB;
720
39
}
721
722
MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
723
    unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
724
18
    MachineInstr &MI, MachineBasicBlock *BB) const {
725
18
  if (DontExpandCondPseudos16)
726
0
    return BB;
727
18
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
728
18
  unsigned regX = MI.getOperand(0).getReg();
729
18
  int64_t imm = MI.getOperand(1).getImm();
730
18
  MachineBasicBlock *target = MI.getOperand(2).getMBB();
731
18
  unsigned CmpOpc;
732
18
  if (isUInt<8>(imm))
733
12
    CmpOpc = CmpiOpc;
734
6
  else if ((!ImmSigned && 
isUInt<16>(imm)4
) ||
735
6
           
(2
ImmSigned2
&&
isInt<16>(imm)2
))
736
6
    CmpOpc = CmpiXOpc;
737
6
  else
738
6
    
llvm_unreachable0
("immediate field not usable");
739
18
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
740
18
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
741
18
  MI.eraseFromParent(); // The pseudo instruction is gone now.
742
18
  return BB;
743
18
}
744
745
static unsigned Mips16WhichOp8uOr16simm
746
40
  (unsigned shortOp, unsigned longOp, int64_t Imm) {
747
40
  if (isUInt<8>(Imm))
748
39
    return shortOp;
749
1
  else if (isInt<16>(Imm))
750
1
    return longOp;
751
1
  else
752
1
    llvm_unreachable("immediate field not usable");
753
40
}
754
755
MachineBasicBlock *
756
Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
757
30
                                          MachineBasicBlock *BB) const {
758
30
  if (DontExpandCondPseudos16)
759
0
    return BB;
760
30
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
761
30
  unsigned CC = MI.getOperand(0).getReg();
762
30
  unsigned regX = MI.getOperand(1).getReg();
763
30
  unsigned regY = MI.getOperand(2).getReg();
764
30
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
765
30
      .addReg(regX)
766
30
      .addReg(regY);
767
30
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
768
30
      .addReg(Mips::T8);
769
30
  MI.eraseFromParent(); // The pseudo instruction is gone now.
770
30
  return BB;
771
30
}
772
773
MachineBasicBlock *
774
Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
775
                                           MachineInstr &MI,
776
40
                                           MachineBasicBlock *BB) const {
777
40
  if (DontExpandCondPseudos16)
778
0
    return BB;
779
40
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
780
40
  unsigned CC = MI.getOperand(0).getReg();
781
40
  unsigned regX = MI.getOperand(1).getReg();
782
40
  int64_t Imm = MI.getOperand(2).getImm();
783
40
  unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
784
40
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
785
40
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
786
40
      .addReg(Mips::T8);
787
40
  MI.eraseFromParent(); // The pseudo instruction is gone now.
788
40
  return BB;
789
40
790
40
}