Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
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Source (jump to first uncovered line)
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//===- Mips16InstrInfo.cpp - Mips16 Instruction Information ---------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the Mips16 implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "Mips16InstrInfo.h"
14
#include "llvm/ADT/BitVector.h"
15
#include "llvm/CodeGen/MachineBasicBlock.h"
16
#include "llvm/CodeGen/MachineFrameInfo.h"
17
#include "llvm/CodeGen/MachineFunction.h"
18
#include "llvm/CodeGen/MachineInstr.h"
19
#include "llvm/CodeGen/MachineInstrBuilder.h"
20
#include "llvm/CodeGen/MachineMemOperand.h"
21
#include "llvm/CodeGen/MachineOperand.h"
22
#include "llvm/CodeGen/RegisterScavenging.h"
23
#include "llvm/CodeGen/TargetRegisterInfo.h"
24
#include "llvm/IR/DebugLoc.h"
25
#include "llvm/MC/MCAsmInfo.h"
26
#include "llvm/Support/Debug.h"
27
#include "llvm/Support/ErrorHandling.h"
28
#include "llvm/Support/MathExtras.h"
29
#include "llvm/Support/raw_ostream.h"
30
#include <cassert>
31
#include <cctype>
32
#include <cstdint>
33
#include <cstdlib>
34
#include <cstring>
35
#include <iterator>
36
#include <vector>
37
38
using namespace llvm;
39
40
#define DEBUG_TYPE "mips16-instrinfo"
41
42
Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
43
2.91k
    : MipsInstrInfo(STI, Mips::Bimm16) {}
44
45
104k
const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
46
104k
  return RI;
47
104k
}
48
49
/// isLoadFromStackSlot - If the specified machine instruction is a direct
50
/// load from a stack slot, return the virtual or physical register number of
51
/// the destination along with the FrameIndex of the loaded stack slot.  If
52
/// not, return 0.  This predicate must return 0 if the instruction has
53
/// any side effects other than loading from the stack slot.
54
unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
55
5.56k
                                              int &FrameIndex) const {
56
5.56k
  return 0;
57
5.56k
}
58
59
/// isStoreToStackSlot - If the specified machine instruction is a direct
60
/// store to a stack slot, return the virtual or physical register number of
61
/// the source reg along with the FrameIndex of the loaded stack slot.  If
62
/// not, return 0.  This predicate must return 0 if the instruction has
63
/// any side effects other than storing to the stack slot.
64
unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
65
2.83k
                                             int &FrameIndex) const {
66
2.83k
  return 0;
67
2.83k
}
68
69
void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
70
                                  MachineBasicBlock::iterator I,
71
                                  const DebugLoc &DL, unsigned DestReg,
72
1.53k
                                  unsigned SrcReg, bool KillSrc) const {
73
1.53k
  unsigned Opc = 0;
74
1.53k
75
1.53k
  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
76
1.53k
      
Mips::GPR32RegClass.contains(SrcReg)426
)
77
418
    Opc = Mips::MoveR3216;
78
1.11k
  else if (Mips::GPR32RegClass.contains(DestReg) &&
79
1.11k
           Mips::CPU16RegsRegClass.contains(SrcReg))
80
1.10k
    Opc = Mips::Move32R16;
81
8
  else if ((SrcReg == Mips::HI0) &&
82
8
           
(Mips::CPU16RegsRegClass.contains(DestReg))4
)
83
4
    Opc = Mips::Mfhi16, SrcReg = 0;
84
4
  else if ((SrcReg == Mips::LO0) &&
85
4
           (Mips::CPU16RegsRegClass.contains(DestReg)))
86
4
    Opc = Mips::Mflo16, SrcReg = 0;
87
1.53k
88
1.53k
  assert(Opc && "Cannot copy registers");
89
1.53k
90
1.53k
  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
91
1.53k
92
1.53k
  if (DestReg)
93
1.53k
    MIB.addReg(DestReg, RegState::Define);
94
1.53k
95
1.53k
  if (SrcReg)
96
1.52k
    MIB.addReg(SrcReg, getKillRegState(KillSrc));
97
1.53k
}
98
99
bool Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
100
                                      const MachineOperand *&Src,
101
0
                                      const MachineOperand *&Dest) const {
102
0
  if (MI.isMoveReg()) {
103
0
    Dest = &MI.getOperand(0);
104
0
    Src = &MI.getOperand(1);
105
0
    return true;
106
0
  }
107
0
  return false;
108
0
}
109
110
void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
111
                                      MachineBasicBlock::iterator I,
112
                                      unsigned SrcReg, bool isKill, int FI,
113
                                      const TargetRegisterClass *RC,
114
                                      const TargetRegisterInfo *TRI,
115
469
                                      int64_t Offset) const {
116
469
  DebugLoc DL;
117
469
  if (I != MBB.end()) 
DL = I->getDebugLoc()467
;
118
469
  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
119
469
  unsigned Opc = 0;
120
469
  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
121
469
    Opc = Mips::SwRxSpImmX16;
122
469
  assert(Opc && "Register class not handled!");
123
469
  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
124
469
      addFrameIndex(FI).addImm(Offset)
125
469
      .addMemOperand(MMO);
126
469
}
127
128
void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
129
                                       MachineBasicBlock::iterator I,
130
                                       unsigned DestReg, int FI,
131
                                       const TargetRegisterClass *RC,
132
                                       const TargetRegisterInfo *TRI,
133
637
                                       int64_t Offset) const {
134
637
  DebugLoc DL;
135
637
  if (I != MBB.end()) DL = I->getDebugLoc();
136
637
  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
137
637
  unsigned Opc = 0;
138
637
139
637
  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
140
637
    Opc = Mips::LwRxSpImmX16;
141
637
  assert(Opc && "Register class not handled!");
142
637
  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
143
637
    .addMemOperand(MMO);
144
637
}
145
146
2.87k
bool Mips16InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
147
2.87k
  MachineBasicBlock &MBB = *MI.getParent();
148
2.87k
  switch (MI.getDesc().getOpcode()) {
149
2.87k
  default:
150
2.48k
    return false;
151
2.87k
  case Mips::RetRA16:
152
383
    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
153
383
    break;
154
383
  }
155
383
156
383
  MBB.erase(MI.getIterator());
157
383
  return true;
158
383
}
159
160
/// GetOppositeBranchOpc - Return the inverse of the specified
161
/// opcode, e.g. turning BEQ to BNE.
162
49
unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
163
49
  switch (Opc) {
164
49
  
case Mips::BeqzRxImmX16: return Mips::BnezRxImmX160
;
165
49
  
case Mips::BnezRxImmX16: return Mips::BeqzRxImmX160
;
166
49
  
case Mips::BeqzRxImm16: return Mips::BnezRxImm165
;
167
49
  
case Mips::BnezRxImm16: return Mips::BeqzRxImm1611
;
168
49
  
case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX160
;
169
49
  
case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX160
;
170
49
  
case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX160
;
171
49
  
case Mips::Btnez16: return Mips::Bteqz1615
;
172
49
  
case Mips::BtnezX16: return Mips::BteqzX160
;
173
49
  
case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX160
;
174
49
  
case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX160
;
175
49
  
case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX160
;
176
49
  
case Mips::Bteqz16: return Mips::Btnez1618
;
177
49
  
case Mips::BteqzX16: return Mips::BtnezX160
;
178
49
  
case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX160
;
179
49
  
case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX160
;
180
49
  
case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX160
;
181
49
  
case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX160
;
182
49
  
case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX160
;
183
49
  
case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX160
;
184
0
  }
185
0
  llvm_unreachable("Illegal opcode!");
186
0
}
187
188
static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
189
                               const std::vector<CalleeSavedInfo> &CSI,
190
492
                               unsigned Flags = 0) {
191
1.52k
  for (unsigned i = 0, e = CSI.size(); i != e; 
++i1.03k
) {
192
1.03k
    // Add the callee-saved register as live-in. Do not add if the register is
193
1.03k
    // RA and return address is taken, because it has already been added in
194
1.03k
    // method MipsTargetLowering::lowerRETURNADDR.
195
1.03k
    // It's killed at the spill, unless the register is RA and return address
196
1.03k
    // is taken.
197
1.03k
    unsigned Reg = CSI[e-i-1].getReg();
198
1.03k
    switch (Reg) {
199
1.03k
    case Mips::RA:
200
896
    case Mips::S0:
201
896
    case Mips::S1:
202
896
      MIB.addReg(Reg, Flags);
203
896
      break;
204
896
    case Mips::S2:
205
138
      break;
206
896
    default:
207
0
      llvm_unreachable("unexpected mips16 callee saved register");
208
1.03k
209
1.03k
    }
210
1.03k
  }
211
492
}
212
213
// Adjust SP by FrameSize bytes. Save RA, S0, S1
214
void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
215
                                MachineBasicBlock &MBB,
216
247
                                MachineBasicBlock::iterator I) const {
217
247
  DebugLoc DL;
218
247
  MachineFunction &MF = *MBB.getParent();
219
247
  MachineFrameInfo &MFI    = MF.getFrameInfo();
220
247
  const BitVector Reserved = RI.getReservedRegs(MF);
221
247
  bool SaveS2 = Reserved[Mips::S2];
222
247
  MachineInstrBuilder MIB;
223
247
  unsigned Opc = ((FrameSize <= 128) && 
!SaveS2243
)?
Mips::Save16175
:
Mips::SaveX1672
;
224
247
  MIB = BuildMI(MBB, I, DL, get(Opc));
225
247
  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
226
247
  addSaveRestoreRegs(MIB, CSI);
227
247
  if (SaveS2)
228
69
    MIB.addReg(Mips::S2);
229
247
  if (isUInt<11>(FrameSize))
230
246
    MIB.addImm(FrameSize);
231
1
  else {
232
1
    int Base = 2040; // should create template function like isUInt that
233
1
                     // returns largest possible n bit unsigned integer
234
1
    int64_t Remainder = FrameSize - Base;
235
1
    MIB.addImm(Base);
236
1
    if (isInt<16>(-Remainder))
237
1
      BuildAddiuSpImm(MBB, I, -Remainder);
238
0
    else
239
0
      adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
240
1
  }
241
247
}
242
243
// Adjust SP by FrameSize bytes. Restore RA, S0, S1
244
void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
245
                                   MachineBasicBlock &MBB,
246
245
                                   MachineBasicBlock::iterator I) const {
247
245
  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : 
DebugLoc()0
;
248
245
  MachineFunction *MF = MBB.getParent();
249
245
  MachineFrameInfo &MFI    = MF->getFrameInfo();
250
245
  const BitVector Reserved = RI.getReservedRegs(*MF);
251
245
  bool SaveS2 = Reserved[Mips::S2];
252
245
  MachineInstrBuilder MIB;
253
245
  unsigned Opc = ((FrameSize <= 128) && 
!SaveS2241
)?
254
173
    Mips::Restore16:
Mips::RestoreX1672
;
255
245
256
245
  if (!isUInt<11>(FrameSize)) {
257
1
    unsigned Base = 2040;
258
1
    int64_t Remainder = FrameSize - Base;
259
1
    FrameSize = Base; // should create template function like isUInt that
260
1
                     // returns largest possible n bit unsigned integer
261
1
262
1
    if (isInt<16>(Remainder))
263
1
      BuildAddiuSpImm(MBB, I, Remainder);
264
0
    else
265
0
      adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
266
1
  }
267
245
  MIB = BuildMI(MBB, I, DL, get(Opc));
268
245
  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
269
245
  addSaveRestoreRegs(MIB, CSI, RegState::Define);
270
245
  if (SaveS2)
271
69
    MIB.addReg(Mips::S2, RegState::Define);
272
245
  MIB.addImm(FrameSize);
273
245
}
274
275
// Adjust SP by Amount bytes where bytes can be up to 32bit number.
276
// This can only be called at times that we know that there is at least one free
277
// register.
278
// This is clearly safe at prologue and epilogue.
279
void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
280
                                        MachineBasicBlock &MBB,
281
                                        MachineBasicBlock::iterator I,
282
0
                                        unsigned Reg1, unsigned Reg2) const {
283
0
  DebugLoc DL;
284
0
  //
285
0
  // li reg1, constant
286
0
  // move reg2, sp
287
0
  // add reg1, reg1, reg2
288
0
  // move sp, reg1
289
0
  //
290
0
  //
291
0
  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
292
0
  MIB1.addImm(Amount).addImm(-1);
293
0
  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
294
0
  MIB2.addReg(Mips::SP, RegState::Kill);
295
0
  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
296
0
  MIB3.addReg(Reg1);
297
0
  MIB3.addReg(Reg2, RegState::Kill);
298
0
  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
299
0
                                                     Mips::SP);
300
0
  MIB4.addReg(Reg1, RegState::Kill);
301
0
}
302
303
void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
304
    unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
305
0
    MachineBasicBlock::iterator I) const {
306
0
   llvm_unreachable("adjust stack pointer amount exceeded");
307
0
}
308
309
/// Adjust SP by Amount bytes.
310
void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
311
                                     MachineBasicBlock &MBB,
312
8
                                     MachineBasicBlock::iterator I) const {
313
8
  if (Amount == 0)
314
4
    return;
315
4
316
4
  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
317
4
    BuildAddiuSpImm(MBB, I, Amount);
318
0
  else
319
0
    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
320
4
}
321
322
/// This function generates the sequence of instructions needed to get the
323
/// result of adding register REG and immediate IMM.
324
unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
325
                                        MachineBasicBlock &MBB,
326
                                        MachineBasicBlock::iterator II,
327
                                        const DebugLoc &DL,
328
0
                                        unsigned &NewImm) const {
329
0
  //
330
0
  // given original instruction is:
331
0
  // Instr rx, T[offset] where offset is too big.
332
0
  //
333
0
  // lo = offset & 0xFFFF
334
0
  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
335
0
  //
336
0
  // let T = temporary register
337
0
  // li T, hi
338
0
  // shl T, 16
339
0
  // add T, Rx, T
340
0
  //
341
0
  RegScavenger rs;
342
0
  int32_t lo = Imm & 0xFFFF;
343
0
  NewImm = lo;
344
0
  int Reg =0;
345
0
  int SpReg = 0;
346
0
347
0
  rs.enterBasicBlock(MBB);
348
0
  rs.forward(II);
349
0
  //
350
0
  // We need to know which registers can be used, in the case where there
351
0
  // are not enough free registers. We exclude all registers that
352
0
  // are used in the instruction that we are helping.
353
0
  //  // Consider all allocatable registers in the register class initially
354
0
  BitVector Candidates =
355
0
      RI.getAllocatableSet
356
0
      (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
357
0
  // Exclude all the registers being used by the instruction.
358
0
  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
359
0
    MachineOperand &MO = II->getOperand(i);
360
0
    if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
361
0
        !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
362
0
      Candidates.reset(MO.getReg());
363
0
  }
364
0
365
0
  // If the same register was used and defined in an instruction, then
366
0
  // it will not be in the list of candidates.
367
0
  //
368
0
  // we need to analyze the instruction that we are helping.
369
0
  // we need to know if it defines register x but register x is not
370
0
  // present as an operand of the instruction. this tells
371
0
  // whether the register is live before the instruction. if it's not
372
0
  // then we don't need to save it in case there are no free registers.
373
0
  int DefReg = 0;
374
0
  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
375
0
    MachineOperand &MO = II->getOperand(i);
376
0
    if (MO.isReg() && MO.isDef()) {
377
0
      DefReg = MO.getReg();
378
0
      break;
379
0
    }
380
0
  }
381
0
382
0
  BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
383
0
  Available &= Candidates;
384
0
  //
385
0
  // we use T0 for the first register, if we need to save something away.
386
0
  // we use T1 for the second register, if we need to save something away.
387
0
  //
388
0
  unsigned FirstRegSaved =0, SecondRegSaved=0;
389
0
  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
390
0
391
0
  Reg = Available.find_first();
392
0
393
0
  if (Reg == -1) {
394
0
    Reg = Candidates.find_first();
395
0
    Candidates.reset(Reg);
396
0
    if (DefReg != Reg) {
397
0
      FirstRegSaved = Reg;
398
0
      FirstRegSavedTo = Mips::T0;
399
0
      copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
400
0
    }
401
0
  }
402
0
  else
403
0
    Available.reset(Reg);
404
0
  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
405
0
  NewImm = 0;
406
0
  if (FrameReg == Mips::SP) {
407
0
    SpReg = Available.find_first();
408
0
    if (SpReg == -1) {
409
0
      SpReg = Candidates.find_first();
410
0
      // Candidates.reset(SpReg); // not really needed
411
0
      if (DefReg!= SpReg) {
412
0
        SecondRegSaved = SpReg;
413
0
        SecondRegSavedTo = Mips::T1;
414
0
      }
415
0
      if (SecondRegSaved)
416
0
        copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
417
0
    }
418
0
   else
419
0
     Available.reset(SpReg);
420
0
    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
421
0
    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
422
0
      .addReg(Reg);
423
0
  }
424
0
  else
425
0
    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
426
0
      .addReg(Reg, RegState::Kill);
427
0
  if (FirstRegSaved || SecondRegSaved) {
428
0
    II = std::next(II);
429
0
    if (FirstRegSaved)
430
0
      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
431
0
    if (SecondRegSaved)
432
0
      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
433
0
  }
434
0
  return Reg;
435
0
}
436
437
9.78k
unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
438
9.78k
  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
439
9.78k
          
Opc == Mips::Bimm169.78k
||
440
9.78k
          
Opc == Mips::Bteqz168.44k
||
Opc == Mips::Btnez167.69k
||
441
9.78k
          
Opc == Mips::BeqzRxImm166.77k
||
Opc == Mips::BnezRxImm166.62k
||
442
9.78k
          
Opc == Mips::BnezRxImmX165.95k
||
Opc == Mips::BteqzX165.95k
||
443
9.78k
          
Opc == Mips::BteqzT8CmpX165.95k
||
Opc == Mips::BteqzT8CmpiX165.95k
||
444
9.78k
          
Opc == Mips::BteqzT8SltX165.95k
||
Opc == Mips::BteqzT8SltuX165.95k
||
445
9.78k
          
Opc == Mips::BteqzT8SltiX165.95k
||
Opc == Mips::BteqzT8SltiuX165.95k
||
446
9.78k
          
Opc == Mips::BtnezX165.95k
||
Opc == Mips::BtnezT8CmpX165.95k
||
447
9.78k
          
Opc == Mips::BtnezT8CmpiX165.95k
||
Opc == Mips::BtnezT8SltX165.95k
||
448
9.78k
          
Opc == Mips::BtnezT8SltuX165.95k
||
Opc == Mips::BtnezT8SltiX165.95k
||
449
9.78k
          
Opc == Mips::BtnezT8SltiuX165.95k
) ?
Opc3.82k
:
05.95k
;
450
9.78k
}
451
452
void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
453
                                  MachineBasicBlock::iterator I,
454
383
                                  unsigned Opc) const {
455
383
  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
456
383
}
457
458
6
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
459
6
  if (validSpImm8(Imm))
460
6
    return get(Mips::AddiuSpImm16);
461
0
  else
462
0
    return get(Mips::AddiuSpImmX16);
463
6
}
464
465
void Mips16InstrInfo::BuildAddiuSpImm
466
6
  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
467
6
  DebugLoc DL;
468
6
  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
469
6
}
470
471
2.91k
const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {
472
2.91k
  return new Mips16InstrInfo(STI);
473
2.91k
}
474
475
bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
476
1.11k
                                     int64_t Amount) {
477
1.11k
  switch (Opcode) {
478
1.11k
  case Mips::LbRxRyOffMemX16:
479
1.10k
  case Mips::LbuRxRyOffMemX16:
480
1.10k
  case Mips::LhRxRyOffMemX16:
481
1.10k
  case Mips::LhuRxRyOffMemX16:
482
1.10k
  case Mips::SbRxRyOffMemX16:
483
1.10k
  case Mips::ShRxRyOffMemX16:
484
1.10k
  case Mips::LwRxRyOffMemX16:
485
1.10k
  case Mips::SwRxRyOffMemX16:
486
1.10k
  case Mips::SwRxSpImmX16:
487
1.10k
  case Mips::LwRxSpImmX16:
488
1.10k
    return isInt<16>(Amount);
489
1.10k
  case Mips::AddiuRxRyOffMemX16:
490
11
    if ((Reg == Mips::PC) || (Reg == Mips::SP))
491
7
      return isInt<16>(Amount);
492
4
    return isInt<15>(Amount);
493
0
  }
494
0
  llvm_unreachable("unexpected Opcode in validImmediate");
495
0
}