/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
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1 | | //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file contains a printer that converts from our internal representation |
10 | | // of machine-dependent LLVM code to GAS-format MIPS assembly language. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "MipsAsmPrinter.h" |
15 | | #include "MCTargetDesc/MipsABIInfo.h" |
16 | | #include "MCTargetDesc/MipsBaseInfo.h" |
17 | | #include "MCTargetDesc/MipsInstPrinter.h" |
18 | | #include "MCTargetDesc/MipsMCNaCl.h" |
19 | | #include "MCTargetDesc/MipsMCTargetDesc.h" |
20 | | #include "Mips.h" |
21 | | #include "MipsMCInstLower.h" |
22 | | #include "MipsMachineFunction.h" |
23 | | #include "MipsSubtarget.h" |
24 | | #include "MipsTargetMachine.h" |
25 | | #include "MipsTargetStreamer.h" |
26 | | #include "TargetInfo/MipsTargetInfo.h" |
27 | | #include "llvm/ADT/SmallString.h" |
28 | | #include "llvm/ADT/StringRef.h" |
29 | | #include "llvm/ADT/Triple.h" |
30 | | #include "llvm/ADT/Twine.h" |
31 | | #include "llvm/BinaryFormat/ELF.h" |
32 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
33 | | #include "llvm/CodeGen/MachineConstantPool.h" |
34 | | #include "llvm/CodeGen/MachineFrameInfo.h" |
35 | | #include "llvm/CodeGen/MachineFunction.h" |
36 | | #include "llvm/CodeGen/MachineInstr.h" |
37 | | #include "llvm/CodeGen/MachineJumpTableInfo.h" |
38 | | #include "llvm/CodeGen/MachineOperand.h" |
39 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
40 | | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
41 | | #include "llvm/IR/Attributes.h" |
42 | | #include "llvm/IR/BasicBlock.h" |
43 | | #include "llvm/IR/DataLayout.h" |
44 | | #include "llvm/IR/Function.h" |
45 | | #include "llvm/IR/InlineAsm.h" |
46 | | #include "llvm/IR/Instructions.h" |
47 | | #include "llvm/MC/MCContext.h" |
48 | | #include "llvm/MC/MCExpr.h" |
49 | | #include "llvm/MC/MCInst.h" |
50 | | #include "llvm/MC/MCInstBuilder.h" |
51 | | #include "llvm/MC/MCObjectFileInfo.h" |
52 | | #include "llvm/MC/MCSectionELF.h" |
53 | | #include "llvm/MC/MCSymbol.h" |
54 | | #include "llvm/MC/MCSymbolELF.h" |
55 | | #include "llvm/Support/Casting.h" |
56 | | #include "llvm/Support/ErrorHandling.h" |
57 | | #include "llvm/Support/TargetRegistry.h" |
58 | | #include "llvm/Support/raw_ostream.h" |
59 | | #include "llvm/Target/TargetMachine.h" |
60 | | #include <cassert> |
61 | | #include <cstdint> |
62 | | #include <map> |
63 | | #include <memory> |
64 | | #include <string> |
65 | | #include <vector> |
66 | | |
67 | | using namespace llvm; |
68 | | |
69 | | #define DEBUG_TYPE "mips-asm-printer" |
70 | | |
71 | | extern cl::opt<bool> EmitJalrReloc; |
72 | | |
73 | 199k | MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const { |
74 | 199k | return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer()); |
75 | 199k | } |
76 | | |
77 | 13.2k | bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { |
78 | 13.2k | Subtarget = &MF.getSubtarget<MipsSubtarget>(); |
79 | 13.2k | |
80 | 13.2k | MipsFI = MF.getInfo<MipsFunctionInfo>(); |
81 | 13.2k | if (Subtarget->inMips16Mode()) |
82 | 380 | for (std::map< |
83 | 380 | const char *, |
84 | 380 | const Mips16HardFloatInfo::FuncSignature *>::const_iterator |
85 | 380 | it = MipsFI->StubsNeeded.begin(); |
86 | 480 | it != MipsFI->StubsNeeded.end(); ++it100 ) { |
87 | 100 | const char *Symbol = it->first; |
88 | 100 | const Mips16HardFloatInfo::FuncSignature *Signature = it->second; |
89 | 100 | if (StubsNeeded.find(Symbol) == StubsNeeded.end()) |
90 | 100 | StubsNeeded[Symbol] = Signature; |
91 | 100 | } |
92 | 13.2k | MCP = MF.getConstantPool(); |
93 | 13.2k | |
94 | 13.2k | // In NaCl, all indirect jump targets must be aligned to bundle size. |
95 | 13.2k | if (Subtarget->isTargetNaCl()) |
96 | 25 | NaClAlignIndirectJumpTargets(MF); |
97 | 13.2k | |
98 | 13.2k | AsmPrinter::runOnMachineFunction(MF); |
99 | 13.2k | |
100 | 13.2k | emitXRayTable(); |
101 | 13.2k | |
102 | 13.2k | return true; |
103 | 13.2k | } |
104 | | |
105 | 14.3k | bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { |
106 | 14.3k | MCOp = MCInstLowering.LowerOperand(MO); |
107 | 14.3k | return MCOp.isValid(); |
108 | 14.3k | } |
109 | | |
110 | | #include "MipsGenMCPseudoLowering.inc" |
111 | | |
112 | | // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM, |
113 | | // JALR, or JALR64 as appropriate for the target. |
114 | | void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer, |
115 | 11.7k | const MachineInstr *MI) { |
116 | 11.7k | bool HasLinkReg = false; |
117 | 11.7k | bool InMicroMipsMode = Subtarget->inMicroMipsMode(); |
118 | 11.7k | MCInst TmpInst0; |
119 | 11.7k | |
120 | 11.7k | if (Subtarget->hasMips64r6()) { |
121 | 515 | // MIPS64r6 should use (JALR64 ZERO_64, $rs) |
122 | 515 | TmpInst0.setOpcode(Mips::JALR64); |
123 | 515 | HasLinkReg = true; |
124 | 11.1k | } else if (Subtarget->hasMips32r6()) { |
125 | 513 | // MIPS32r6 should use (JALR ZERO, $rs) |
126 | 513 | if (InMicroMipsMode) |
127 | 0 | TmpInst0.setOpcode(Mips::JRC16_MMR6); |
128 | 513 | else { |
129 | 513 | TmpInst0.setOpcode(Mips::JALR); |
130 | 513 | HasLinkReg = true; |
131 | 513 | } |
132 | 10.6k | } else if (Subtarget->inMicroMipsMode()) |
133 | 241 | // microMIPS should use (JR_MM $rs) |
134 | 241 | TmpInst0.setOpcode(Mips::JR_MM); |
135 | 10.4k | else { |
136 | 10.4k | // Everything else should use (JR $rs) |
137 | 10.4k | TmpInst0.setOpcode(Mips::JR); |
138 | 10.4k | } |
139 | 11.7k | |
140 | 11.7k | MCOperand MCOp; |
141 | 11.7k | |
142 | 11.7k | if (HasLinkReg) { |
143 | 1.02k | unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64515 : Mips::ZERO513 ; |
144 | 1.02k | TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); |
145 | 1.02k | } |
146 | 11.7k | |
147 | 11.7k | lowerOperand(MI->getOperand(0), MCOp); |
148 | 11.7k | TmpInst0.addOperand(MCOp); |
149 | 11.7k | |
150 | 11.7k | EmitToStreamer(OutStreamer, TmpInst0); |
151 | 11.7k | } |
152 | | |
153 | | // If there is an MO_JALR operand, insert: |
154 | | // |
155 | | // .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol |
156 | | // tmplabel: |
157 | | // |
158 | | // This is an optimization hint for the linker which may then replace |
159 | | // an indirect call with a direct branch. |
160 | | static void emitDirectiveRelocJalr(const MachineInstr &MI, |
161 | | MCContext &OutContext, |
162 | | TargetMachine &TM, |
163 | | MCStreamer &OutStreamer, |
164 | 15.3k | const MipsSubtarget &Subtarget) { |
165 | 15.3k | for (unsigned int I = MI.getDesc().getNumOperands(), E = MI.getNumOperands(); |
166 | 36.5k | I < E; ++I21.1k ) { |
167 | 22.1k | MachineOperand MO = MI.getOperand(I); |
168 | 22.1k | if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR)939 ) { |
169 | 939 | MCSymbol *Callee = MO.getMCSymbol(); |
170 | 939 | if (Callee && !Callee->getName().empty()) { |
171 | 939 | MCSymbol *OffsetLabel = OutContext.createTempSymbol(); |
172 | 939 | const MCExpr *OffsetExpr = |
173 | 939 | MCSymbolRefExpr::create(OffsetLabel, OutContext); |
174 | 939 | const MCExpr *CaleeExpr = |
175 | 939 | MCSymbolRefExpr::create(Callee, OutContext); |
176 | 939 | OutStreamer.EmitRelocDirective |
177 | 939 | (*OffsetExpr, |
178 | 939 | Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR"71 : "R_MIPS_JALR"868 , |
179 | 939 | CaleeExpr, SMLoc(), *TM.getMCSubtargetInfo()); |
180 | 939 | OutStreamer.EmitLabel(OffsetLabel); |
181 | 939 | return; |
182 | 939 | } |
183 | 939 | } |
184 | 22.1k | } |
185 | 15.3k | } |
186 | | |
187 | 113k | void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { |
188 | 113k | MipsTargetStreamer &TS = getTargetStreamer(); |
189 | 113k | unsigned Opc = MI->getOpcode(); |
190 | 113k | TS.forbidModuleDirective(); |
191 | 113k | |
192 | 113k | if (MI->isDebugValue()) { |
193 | 0 | SmallString<128> Str; |
194 | 0 | raw_svector_ostream OS(Str); |
195 | 0 |
|
196 | 0 | PrintDebugValueComment(MI, OS); |
197 | 0 | return; |
198 | 0 | } |
199 | 113k | if (MI->isDebugLabel()) |
200 | 0 | return; |
201 | 113k | |
202 | 113k | // If we just ended a constant pool, mark it as such. |
203 | 113k | if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY17 ) { |
204 | 3 | OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); |
205 | 3 | InConstantPool = false; |
206 | 3 | } |
207 | 113k | if (Opc == Mips::CONSTPOOL_ENTRY) { |
208 | 34 | // CONSTPOOL_ENTRY - This instruction represents a floating |
209 | 34 | // constant pool in the function. The first operand is the ID# |
210 | 34 | // for this instruction, the second is the index into the |
211 | 34 | // MachineConstantPool that this is, the third is the size in |
212 | 34 | // bytes of this constant pool entry. |
213 | 34 | // The required alignment is specified on the basic block holding this MI. |
214 | 34 | // |
215 | 34 | unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); |
216 | 34 | unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); |
217 | 34 | |
218 | 34 | // If this is the first entry of the pool, mark it. |
219 | 34 | if (!InConstantPool) { |
220 | 20 | OutStreamer->EmitDataRegion(MCDR_DataRegion); |
221 | 20 | InConstantPool = true; |
222 | 20 | } |
223 | 34 | |
224 | 34 | OutStreamer->EmitLabel(GetCPISymbol(LabelId)); |
225 | 34 | |
226 | 34 | const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; |
227 | 34 | if (MCPE.isMachineConstantPoolEntry()) |
228 | 0 | EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); |
229 | 34 | else |
230 | 34 | EmitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); |
231 | 34 | return; |
232 | 34 | } |
233 | 113k | |
234 | 113k | switch (Opc) { |
235 | 113k | case Mips::PATCHABLE_FUNCTION_ENTER: |
236 | 24 | LowerPATCHABLE_FUNCTION_ENTER(*MI); |
237 | 24 | return; |
238 | 113k | case Mips::PATCHABLE_FUNCTION_EXIT: |
239 | 28 | LowerPATCHABLE_FUNCTION_EXIT(*MI); |
240 | 28 | return; |
241 | 113k | case Mips::PATCHABLE_TAIL_CALL: |
242 | 0 | LowerPATCHABLE_TAIL_CALL(*MI); |
243 | 0 | return; |
244 | 113k | } |
245 | 113k | |
246 | 113k | if (EmitJalrReloc && |
247 | 113k | (103k MI->isReturn()103k || MI->isCall()91.7k || MI->isIndirectBranch()88.9k )) { |
248 | 15.3k | emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget); |
249 | 15.3k | } |
250 | 113k | |
251 | 113k | MachineBasicBlock::const_instr_iterator I = MI->getIterator(); |
252 | 113k | MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); |
253 | 113k | |
254 | 128k | do { |
255 | 128k | // Do any auto-generated pseudo lowerings. |
256 | 128k | if (emitPseudoExpansionLowering(*OutStreamer, &*I)) |
257 | 6.04k | continue; |
258 | 122k | |
259 | 122k | if (I->getOpcode() == Mips::PseudoReturn || |
260 | 122k | I->getOpcode() == Mips::PseudoReturn64115k || |
261 | 122k | I->getOpcode() == Mips::PseudoIndirectBranch110k || |
262 | 122k | I->getOpcode() == Mips::PseudoIndirectBranch64110k || |
263 | 122k | I->getOpcode() == Mips::TAILCALLREG110k || |
264 | 122k | I->getOpcode() == Mips::TAILCALLREG64110k ) { |
265 | 11.7k | emitPseudoIndirectBranch(*OutStreamer, &*I); |
266 | 11.7k | continue; |
267 | 11.7k | } |
268 | 110k | |
269 | 110k | // The inMips16Mode() test is not permanent. |
270 | 110k | // Some instructions are marked as pseudo right now which |
271 | 110k | // would make the test fail for the wrong reason but |
272 | 110k | // that will be fixed soon. We need this here because we are |
273 | 110k | // removing another test for this situation downstream in the |
274 | 110k | // callchain. |
275 | 110k | // |
276 | 110k | if (I->isPseudo() && !Subtarget->inMips16Mode()176 |
277 | 110k | && !isLongBranchPseudo(I->getOpcode())68 ) |
278 | 110k | llvm_unreachable0 ("Pseudo opcode found in EmitInstruction()"); |
279 | 110k | |
280 | 110k | MCInst TmpInst0; |
281 | 110k | MCInstLowering.Lower(&*I, TmpInst0); |
282 | 110k | EmitToStreamer(*OutStreamer, TmpInst0); |
283 | 128k | } while ((++I != E) && I->isInsideBundle()112k ); // Delay slot check |
284 | 113k | } |
285 | | |
286 | | //===----------------------------------------------------------------------===// |
287 | | // |
288 | | // Mips Asm Directives |
289 | | // |
290 | | // -- Frame directive "frame Stackpointer, Stacksize, RARegister" |
291 | | // Describe the stack frame. |
292 | | // |
293 | | // -- Mask directives "(f)mask bitmask, offset" |
294 | | // Tells the assembler which registers are saved and where. |
295 | | // bitmask - contain a little endian bitset indicating which registers are |
296 | | // saved on function prologue (e.g. with a 0x80000000 mask, the |
297 | | // assembler knows the register 31 (RA) is saved at prologue. |
298 | | // offset - the position before stack pointer subtraction indicating where |
299 | | // the first saved register on prologue is located. (e.g. with a |
300 | | // |
301 | | // Consider the following function prologue: |
302 | | // |
303 | | // .frame $fp,48,$ra |
304 | | // .mask 0xc0000000,-8 |
305 | | // addiu $sp, $sp, -48 |
306 | | // sw $ra, 40($sp) |
307 | | // sw $fp, 36($sp) |
308 | | // |
309 | | // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and |
310 | | // 30 (FP) are saved at prologue. As the save order on prologue is from |
311 | | // left to right, RA is saved first. A -8 offset means that after the |
312 | | // stack pointer subtration, the first register in the mask (RA) will be |
313 | | // saved at address 48-8=40. |
314 | | // |
315 | | //===----------------------------------------------------------------------===// |
316 | | |
317 | | //===----------------------------------------------------------------------===// |
318 | | // Mask directives |
319 | | //===----------------------------------------------------------------------===// |
320 | | |
321 | | // Create a bitmask with all callee saved registers for CPU or Floating Point |
322 | | // registers. For CPU registers consider RA, GP and FP for saving if necessary. |
323 | 13.1k | void MipsAsmPrinter::printSavedRegsBitmask() { |
324 | 13.1k | // CPU and FPU Saved Registers Bitmasks |
325 | 13.1k | unsigned CPUBitmask = 0, FPUBitmask = 0; |
326 | 13.1k | int CPUTopSavedRegOff, FPUTopSavedRegOff; |
327 | 13.1k | |
328 | 13.1k | // Set the CPU and FPU Bitmasks |
329 | 13.1k | const MachineFrameInfo &MFI = MF->getFrameInfo(); |
330 | 13.1k | const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); |
331 | 13.1k | const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); |
332 | 13.1k | // size of stack area to which FP callee-saved regs are saved. |
333 | 13.1k | unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; |
334 | 13.1k | unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; |
335 | 13.1k | unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; |
336 | 13.1k | bool HasAFGR64Reg = false; |
337 | 13.1k | unsigned CSFPRegsSize = 0; |
338 | 13.1k | |
339 | 13.1k | for (const auto &I : CSI) { |
340 | 4.29k | unsigned Reg = I.getReg(); |
341 | 4.29k | unsigned RegNum = TRI->getEncodingValue(Reg); |
342 | 4.29k | |
343 | 4.29k | // If it's a floating point register, set the FPU Bitmask. |
344 | 4.29k | // If it's a general purpose register, set the CPU Bitmask. |
345 | 4.29k | if (Mips::FGR32RegClass.contains(Reg)) { |
346 | 0 | FPUBitmask |= (1 << RegNum); |
347 | 0 | CSFPRegsSize += FGR32RegSize; |
348 | 4.29k | } else if (Mips::AFGR64RegClass.contains(Reg)) { |
349 | 107 | FPUBitmask |= (3 << RegNum); |
350 | 107 | CSFPRegsSize += AFGR64RegSize; |
351 | 107 | HasAFGR64Reg = true; |
352 | 4.19k | } else if (Mips::GPR32RegClass.contains(Reg)) |
353 | 2.29k | CPUBitmask |= (1 << RegNum); |
354 | 4.29k | } |
355 | 13.1k | |
356 | 13.1k | // FP Regs are saved right below where the virtual frame pointer points to. |
357 | 13.1k | FPUTopSavedRegOff = FPUBitmask ? |
358 | 13.1k | (HasAFGR64Reg 35 ? -AFGR64RegSize35 : -FGR32RegSize0 ) : 0; |
359 | 13.1k | |
360 | 13.1k | // CPU Regs are saved below FP Regs. |
361 | 13.1k | CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize1.42k : 011.7k ; |
362 | 13.1k | |
363 | 13.1k | MipsTargetStreamer &TS = getTargetStreamer(); |
364 | 13.1k | // Print CPUBitmask |
365 | 13.1k | TS.emitMask(CPUBitmask, CPUTopSavedRegOff); |
366 | 13.1k | |
367 | 13.1k | // Print FPUBitmask |
368 | 13.1k | TS.emitFMask(FPUBitmask, FPUTopSavedRegOff); |
369 | 13.1k | } |
370 | | |
371 | | //===----------------------------------------------------------------------===// |
372 | | // Frame and Set directives |
373 | | //===----------------------------------------------------------------------===// |
374 | | |
375 | | /// Frame Directive |
376 | 13.1k | void MipsAsmPrinter::emitFrameDirective() { |
377 | 13.1k | const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo(); |
378 | 13.1k | |
379 | 13.1k | unsigned stackReg = RI.getFrameRegister(*MF); |
380 | 13.1k | unsigned returnReg = RI.getRARegister(); |
381 | 13.1k | unsigned stackSize = MF->getFrameInfo().getStackSize(); |
382 | 13.1k | |
383 | 13.1k | getTargetStreamer().emitFrame(stackReg, stackSize, returnReg); |
384 | 13.1k | } |
385 | | |
386 | | /// Emit Set directives. |
387 | 2.01k | const char *MipsAsmPrinter::getCurrentABIString() const { |
388 | 2.01k | switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) { |
389 | 2.01k | case MipsABIInfo::ABI::O32: return "abi32"1.34k ; |
390 | 2.01k | case MipsABIInfo::ABI::N32: return "abiN32"89 ; |
391 | 2.01k | case MipsABIInfo::ABI::N64: return "abi64"585 ; |
392 | 2.01k | default: 0 llvm_unreachable0 ("Unknown Mips ABI"); |
393 | 2.01k | } |
394 | 2.01k | } |
395 | | |
396 | 13.2k | void MipsAsmPrinter::EmitFunctionEntryLabel() { |
397 | 13.2k | MipsTargetStreamer &TS = getTargetStreamer(); |
398 | 13.2k | |
399 | 13.2k | // NaCl sandboxing requires that indirect call instructions are masked. |
400 | 13.2k | // This means that function entry points should be bundle-aligned. |
401 | 13.2k | if (Subtarget->isTargetNaCl()) |
402 | 25 | EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN)); |
403 | 13.2k | |
404 | 13.2k | if (Subtarget->inMicroMipsMode()) { |
405 | 891 | TS.emitDirectiveSetMicroMips(); |
406 | 891 | TS.setUsesMicroMips(); |
407 | 891 | TS.updateABIInfo(*Subtarget); |
408 | 891 | } else |
409 | 12.3k | TS.emitDirectiveSetNoMicroMips(); |
410 | 13.2k | |
411 | 13.2k | if (Subtarget->inMips16Mode()) |
412 | 380 | TS.emitDirectiveSetMips16(); |
413 | 12.8k | else |
414 | 12.8k | TS.emitDirectiveSetNoMips16(); |
415 | 13.2k | |
416 | 13.2k | TS.emitDirectiveEnt(*CurrentFnSym); |
417 | 13.2k | OutStreamer->EmitLabel(CurrentFnSym); |
418 | 13.2k | } |
419 | | |
420 | | /// EmitFunctionBodyStart - Targets can override this to emit stuff before |
421 | | /// the first basic block in the function. |
422 | 13.2k | void MipsAsmPrinter::EmitFunctionBodyStart() { |
423 | 13.2k | MipsTargetStreamer &TS = getTargetStreamer(); |
424 | 13.2k | |
425 | 13.2k | MCInstLowering.Initialize(&MF->getContext()); |
426 | 13.2k | |
427 | 13.2k | bool IsNakedFunction = MF->getFunction().hasFnAttribute(Attribute::Naked); |
428 | 13.2k | if (!IsNakedFunction) |
429 | 13.1k | emitFrameDirective(); |
430 | 13.2k | |
431 | 13.2k | if (!IsNakedFunction) |
432 | 13.1k | printSavedRegsBitmask(); |
433 | 13.2k | |
434 | 13.2k | if (!Subtarget->inMips16Mode()) { |
435 | 12.8k | TS.emitDirectiveSetNoReorder(); |
436 | 12.8k | TS.emitDirectiveSetNoMacro(); |
437 | 12.8k | TS.emitDirectiveSetNoAt(); |
438 | 12.8k | } |
439 | 13.2k | } |
440 | | |
441 | | /// EmitFunctionBodyEnd - Targets can override this to emit stuff after |
442 | | /// the last basic block in the function. |
443 | 13.2k | void MipsAsmPrinter::EmitFunctionBodyEnd() { |
444 | 13.2k | MipsTargetStreamer &TS = getTargetStreamer(); |
445 | 13.2k | |
446 | 13.2k | // There are instruction for this macros, but they must |
447 | 13.2k | // always be at the function end, and we can't emit and |
448 | 13.2k | // break with BB logic. |
449 | 13.2k | if (!Subtarget->inMips16Mode()) { |
450 | 12.8k | TS.emitDirectiveSetAt(); |
451 | 12.8k | TS.emitDirectiveSetMacro(); |
452 | 12.8k | TS.emitDirectiveSetReorder(); |
453 | 12.8k | } |
454 | 13.2k | TS.emitDirectiveEnd(CurrentFnSym->getName()); |
455 | 13.2k | // Make sure to terminate any constant pools that were at the end |
456 | 13.2k | // of the function. |
457 | 13.2k | if (!InConstantPool) |
458 | 13.2k | return; |
459 | 17 | InConstantPool = false; |
460 | 17 | OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); |
461 | 17 | } |
462 | | |
463 | 16.4k | void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) { |
464 | 16.4k | AsmPrinter::EmitBasicBlockEnd(MBB); |
465 | 16.4k | MipsTargetStreamer &TS = getTargetStreamer(); |
466 | 16.4k | if (MBB.empty()) |
467 | 42 | TS.emitDirectiveInsn(); |
468 | 16.4k | } |
469 | | |
470 | | /// isBlockOnlyReachableByFallthough - Return true if the basic block has |
471 | | /// exactly one predecessor and the control transfer mechanism between |
472 | | /// the predecessor and this block is a fall-through. |
473 | | bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock* |
474 | 9.73k | MBB) const { |
475 | 9.73k | // The predecessor has to be immediately before this block. |
476 | 9.73k | const MachineBasicBlock *Pred = *MBB->pred_begin(); |
477 | 9.73k | |
478 | 9.73k | // If the predecessor is a switch statement, assume a jump table |
479 | 9.73k | // implementation, so it is not a fall through. |
480 | 9.73k | if (const BasicBlock *bb = Pred->getBasicBlock()) |
481 | 9.70k | if (isa<SwitchInst>(bb->getTerminator())) |
482 | 576 | return false; |
483 | 9.16k | |
484 | 9.16k | // If this is a landing pad, it isn't a fall through. If it has no preds, |
485 | 9.16k | // then nothing falls through to it. |
486 | 9.16k | if (MBB->isEHPad() || MBB->pred_empty()9.10k ) |
487 | 57 | return false; |
488 | 9.10k | |
489 | 9.10k | // If there isn't exactly one predecessor, it can't be a fall through. |
490 | 9.10k | MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI; |
491 | 9.10k | ++PI2; |
492 | 9.10k | |
493 | 9.10k | if (PI2 != MBB->pred_end()) |
494 | 3.65k | return false; |
495 | 5.45k | |
496 | 5.45k | // The predecessor has to be immediately before this block. |
497 | 5.45k | if (!Pred->isLayoutSuccessor(MBB)) |
498 | 1.23k | return false; |
499 | 4.22k | |
500 | 4.22k | // If the block is completely empty, then it definitely does fall through. |
501 | 4.22k | if (Pred->empty()) |
502 | 6 | return true; |
503 | 4.21k | |
504 | 4.21k | // Otherwise, check the last instruction. |
505 | 4.21k | // Check if the last terminator is an unconditional branch. |
506 | 4.21k | MachineBasicBlock::const_iterator I = Pred->end(); |
507 | 6.35k | while (I != Pred->begin() && !(--I)->isTerminator()5.84k ) ;2.13k |
508 | 4.21k | |
509 | 4.21k | return !I->isBarrier(); |
510 | 4.21k | } |
511 | | |
512 | | // Print out an operand for an inline asm expression. |
513 | | bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, |
514 | 343 | const char *ExtraCode, raw_ostream &O) { |
515 | 343 | // Does this asm operand have a single letter operand modifier? |
516 | 343 | if (ExtraCode && ExtraCode[0]68 ) { |
517 | 68 | if (ExtraCode[1] != 0) return true0 ; // Unknown modifier. |
518 | 68 | |
519 | 68 | const MachineOperand &MO = MI->getOperand(OpNum); |
520 | 68 | switch (ExtraCode[0]) { |
521 | 68 | default: |
522 | 6 | // See if this is a generic print operand |
523 | 6 | return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O); |
524 | 68 | case 'X': // hex const int |
525 | 4 | if ((MO.getType()) != MachineOperand::MO_Immediate) |
526 | 0 | return true; |
527 | 4 | O << "0x" << Twine::utohexstr(MO.getImm()); |
528 | 4 | return false; |
529 | 4 | case 'x': // hex const int (low 16 bits) |
530 | 4 | if ((MO.getType()) != MachineOperand::MO_Immediate) |
531 | 0 | return true; |
532 | 4 | O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff); |
533 | 4 | return false; |
534 | 4 | case 'd': // decimal const int |
535 | 4 | if ((MO.getType()) != MachineOperand::MO_Immediate) |
536 | 0 | return true; |
537 | 4 | O << MO.getImm(); |
538 | 4 | return false; |
539 | 4 | case 'm': // decimal const int minus 1 |
540 | 4 | if ((MO.getType()) != MachineOperand::MO_Immediate) |
541 | 0 | return true; |
542 | 4 | O << MO.getImm() - 1; |
543 | 4 | return false; |
544 | 5 | case 'y': // exact log2 |
545 | 5 | if ((MO.getType()) != MachineOperand::MO_Immediate) |
546 | 0 | return true; |
547 | 5 | if (!isPowerOf2_64(MO.getImm())) |
548 | 1 | return true; |
549 | 4 | O << Log2_64(MO.getImm()); |
550 | 4 | return false; |
551 | 24 | case 'z': |
552 | 24 | // $0 if zero, regular printing otherwise |
553 | 24 | if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 012 ) { |
554 | 8 | O << "$0"; |
555 | 8 | return false; |
556 | 8 | } |
557 | 16 | // If not, call printOperand as normal. |
558 | 16 | break; |
559 | 16 | case 'D': // Second part of a double word register operand |
560 | 12 | case 'L': // Low order register of a double word register operand |
561 | 12 | case 'M': // High order register of a double word register operand |
562 | 12 | { |
563 | 12 | if (OpNum == 0) |
564 | 0 | return true; |
565 | 12 | const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); |
566 | 12 | if (!FlagsOP.isImm()) |
567 | 0 | return true; |
568 | 12 | unsigned Flags = FlagsOP.getImm(); |
569 | 12 | unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); |
570 | 12 | // Number of registers represented by this operand. We are looking |
571 | 12 | // for 2 for 32 bit mode and 1 for 64 bit mode. |
572 | 12 | if (NumVals != 2) { |
573 | 0 | if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { |
574 | 0 | unsigned Reg = MO.getReg(); |
575 | 0 | O << '$' << MipsInstPrinter::getRegisterName(Reg); |
576 | 0 | return false; |
577 | 0 | } |
578 | 0 | return true; |
579 | 0 | } |
580 | 12 | |
581 | 12 | unsigned RegOp = OpNum; |
582 | 12 | if (!Subtarget->isGP64bit()){ |
583 | 12 | // Endianness reverses which register holds the high or low value |
584 | 12 | // between M and L. |
585 | 12 | switch(ExtraCode[0]) { |
586 | 12 | case 'M': |
587 | 4 | RegOp = (Subtarget->isLittle()) ? OpNum + 12 : OpNum2 ; |
588 | 4 | break; |
589 | 12 | case 'L': |
590 | 4 | RegOp = (Subtarget->isLittle()) ? OpNum2 : OpNum + 12 ; |
591 | 4 | break; |
592 | 12 | case 'D': // Always the second part |
593 | 4 | RegOp = OpNum + 1; |
594 | 12 | } |
595 | 12 | if (RegOp >= MI->getNumOperands()) |
596 | 0 | return true; |
597 | 12 | const MachineOperand &MO = MI->getOperand(RegOp); |
598 | 12 | if (!MO.isReg()) |
599 | 0 | return true; |
600 | 12 | unsigned Reg = MO.getReg(); |
601 | 12 | O << '$' << MipsInstPrinter::getRegisterName(Reg); |
602 | 12 | return false; |
603 | 12 | } |
604 | 0 | break; |
605 | 0 | } |
606 | 5 | case 'w': |
607 | 5 | // Print MSA registers for the 'f' constraint |
608 | 5 | // In LLVM, the 'w' modifier doesn't need to do anything. |
609 | 5 | // We can just call printOperand as normal. |
610 | 5 | break; |
611 | 296 | } |
612 | 296 | } |
613 | 296 | |
614 | 296 | printOperand(MI, OpNum, O); |
615 | 296 | return false; |
616 | 296 | } |
617 | | |
618 | | bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, |
619 | | unsigned OpNum, |
620 | | const char *ExtraCode, |
621 | 59 | raw_ostream &O) { |
622 | 59 | assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands"); |
623 | 59 | const MachineOperand &BaseMO = MI->getOperand(OpNum); |
624 | 59 | const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1); |
625 | 59 | assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand."); |
626 | 59 | assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand."); |
627 | 59 | int Offset = OffsetMO.getImm(); |
628 | 59 | |
629 | 59 | // Currently we are expecting either no ExtraCode or 'D','M','L'. |
630 | 59 | if (ExtraCode) { |
631 | 6 | switch (ExtraCode[0]) { |
632 | 6 | case 'D': |
633 | 2 | Offset += 4; |
634 | 2 | break; |
635 | 6 | case 'M': |
636 | 2 | if (Subtarget->isLittle()) |
637 | 1 | Offset += 4; |
638 | 2 | break; |
639 | 6 | case 'L': |
640 | 2 | if (!Subtarget->isLittle()) |
641 | 1 | Offset += 4; |
642 | 2 | break; |
643 | 6 | default: |
644 | 0 | return true; // Unknown modifier. |
645 | 59 | } |
646 | 59 | } |
647 | 59 | |
648 | 59 | O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) |
649 | 59 | << ")"; |
650 | 59 | |
651 | 59 | return false; |
652 | 59 | } |
653 | | |
654 | | void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, |
655 | 296 | raw_ostream &O) { |
656 | 296 | const MachineOperand &MO = MI->getOperand(opNum); |
657 | 296 | bool closeP = false; |
658 | 296 | |
659 | 296 | if (MO.getTargetFlags()) |
660 | 0 | closeP = true; |
661 | 296 | |
662 | 296 | switch(MO.getTargetFlags()) { |
663 | 296 | case MipsII::MO_GPREL: O << "%gp_rel("; break0 ; |
664 | 296 | case MipsII::MO_GOT_CALL: O << "%call16("; break0 ; |
665 | 296 | case MipsII::MO_GOT: O << "%got("; break0 ; |
666 | 296 | case MipsII::MO_ABS_HI: O << "%hi("; break0 ; |
667 | 296 | case MipsII::MO_ABS_LO: O << "%lo("; break0 ; |
668 | 296 | case MipsII::MO_HIGHER: O << "%higher("; break0 ; |
669 | 296 | case MipsII::MO_HIGHEST: O << "%highest(("; break0 ; |
670 | 296 | case MipsII::MO_TLSGD: O << "%tlsgd("; break0 ; |
671 | 296 | case MipsII::MO_GOTTPREL: O << "%gottprel("; break0 ; |
672 | 296 | case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break0 ; |
673 | 296 | case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break0 ; |
674 | 296 | case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break0 ; |
675 | 296 | case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break0 ; |
676 | 296 | case MipsII::MO_GOT_DISP: O << "%got_disp("; break0 ; |
677 | 296 | case MipsII::MO_GOT_PAGE: O << "%got_page("; break0 ; |
678 | 296 | case MipsII::MO_GOT_OFST: O << "%got_ofst("; break0 ; |
679 | 296 | } |
680 | 296 | |
681 | 296 | switch (MO.getType()) { |
682 | 296 | case MachineOperand::MO_Register: |
683 | 257 | O << '$' |
684 | 257 | << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower(); |
685 | 257 | break; |
686 | 296 | |
687 | 296 | case MachineOperand::MO_Immediate: |
688 | 39 | O << MO.getImm(); |
689 | 39 | break; |
690 | 296 | |
691 | 296 | case MachineOperand::MO_MachineBasicBlock: |
692 | 0 | MO.getMBB()->getSymbol()->print(O, MAI); |
693 | 0 | return; |
694 | 296 | |
695 | 296 | case MachineOperand::MO_GlobalAddress: |
696 | 0 | PrintSymbolOperand(MO, O); |
697 | 0 | break; |
698 | 296 | |
699 | 296 | case MachineOperand::MO_BlockAddress: { |
700 | 0 | MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress()); |
701 | 0 | O << BA->getName(); |
702 | 0 | break; |
703 | 296 | } |
704 | 296 | |
705 | 296 | case MachineOperand::MO_ConstantPoolIndex: |
706 | 0 | O << getDataLayout().getPrivateGlobalPrefix() << "CPI" |
707 | 0 | << getFunctionNumber() << "_" << MO.getIndex(); |
708 | 0 | if (MO.getOffset()) |
709 | 0 | O << "+" << MO.getOffset(); |
710 | 0 | break; |
711 | 296 | |
712 | 296 | default: |
713 | 0 | llvm_unreachable("<unknown operand type>"); |
714 | 296 | } |
715 | 296 | |
716 | 296 | if (closeP) O << ")"0 ; |
717 | 296 | } |
718 | | |
719 | | void MipsAsmPrinter:: |
720 | 0 | printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { |
721 | 0 | // Load/Store memory operands -- imm($reg) |
722 | 0 | // If PIC target the target is loaded as the |
723 | 0 | // pattern lw $25,%call16($28) |
724 | 0 |
|
725 | 0 | // opNum can be invalid if instruction has reglist as operand. |
726 | 0 | // MemOperand is always last operand of instruction (base + offset). |
727 | 0 | switch (MI->getOpcode()) { |
728 | 0 | default: |
729 | 0 | break; |
730 | 0 | case Mips::SWM32_MM: |
731 | 0 | case Mips::LWM32_MM: |
732 | 0 | opNum = MI->getNumOperands() - 2; |
733 | 0 | break; |
734 | 0 | } |
735 | 0 | |
736 | 0 | printOperand(MI, opNum+1, O); |
737 | 0 | O << "("; |
738 | 0 | printOperand(MI, opNum, O); |
739 | 0 | O << ")"; |
740 | 0 | } |
741 | | |
742 | | void MipsAsmPrinter:: |
743 | 0 | printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) { |
744 | 0 | // when using stack locations for not load/store instructions |
745 | 0 | // print the same way as all normal 3 operand instructions. |
746 | 0 | printOperand(MI, opNum, O); |
747 | 0 | O << ", "; |
748 | 0 | printOperand(MI, opNum+1, O); |
749 | 0 | } |
750 | | |
751 | | void MipsAsmPrinter:: |
752 | | printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, |
753 | 0 | const char *Modifier) { |
754 | 0 | const MachineOperand &MO = MI->getOperand(opNum); |
755 | 0 | O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); |
756 | 0 | } |
757 | | |
758 | | void MipsAsmPrinter:: |
759 | 0 | printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) { |
760 | 0 | for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) { |
761 | 0 | if (i != opNum) O << ", "; |
762 | 0 | printOperand(MI, i, O); |
763 | 0 | } |
764 | 0 | } |
765 | | |
766 | 2.01k | void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { |
767 | 2.01k | MipsTargetStreamer &TS = getTargetStreamer(); |
768 | 2.01k | |
769 | 2.01k | // MipsTargetStreamer has an initialization order problem when emitting an |
770 | 2.01k | // object file directly (see MipsTargetELFStreamer for full details). Work |
771 | 2.01k | // around it by re-initializing the PIC state here. |
772 | 2.01k | TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent()); |
773 | 2.01k | |
774 | 2.01k | // Compute MIPS architecture attributes based on the default subtarget |
775 | 2.01k | // that we'd have constructed. Module level directives aren't LTO |
776 | 2.01k | // clean anyhow. |
777 | 2.01k | // FIXME: For ifunc related functions we could iterate over and look |
778 | 2.01k | // for a feature string that doesn't match the default one. |
779 | 2.01k | const Triple &TT = TM.getTargetTriple(); |
780 | 2.01k | StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU()); |
781 | 2.01k | StringRef FS = TM.getTargetFeatureString(); |
782 | 2.01k | const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM); |
783 | 2.01k | const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, 0); |
784 | 2.01k | |
785 | 2.01k | bool IsABICalls = STI.isABICalls(); |
786 | 2.01k | const MipsABIInfo &ABI = MTM.getABI(); |
787 | 2.01k | if (IsABICalls) { |
788 | 1.63k | TS.emitDirectiveAbiCalls(); |
789 | 1.63k | // FIXME: This condition should be a lot more complicated that it is here. |
790 | 1.63k | // Ideally it should test for properties of the ABI and not the ABI |
791 | 1.63k | // itself. |
792 | 1.63k | // For the moment, I'm only correcting enough to make MIPS-IV work. |
793 | 1.63k | if (!isPositionIndependent() && STI.hasSym32()869 ) |
794 | 869 | TS.emitDirectiveOptionPic0(); |
795 | 1.63k | } |
796 | 2.01k | |
797 | 2.01k | // Tell the assembler which ABI we are using |
798 | 2.01k | std::string SectionName = std::string(".mdebug.") + getCurrentABIString(); |
799 | 2.01k | OutStreamer->SwitchSection( |
800 | 2.01k | OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0)); |
801 | 2.01k | |
802 | 2.01k | // NaN: At the moment we only support: |
803 | 2.01k | // 1. .nan legacy (default) |
804 | 2.01k | // 2. .nan 2008 |
805 | 2.01k | STI.isNaN2008() ? TS.emitDirectiveNaN2008()271 |
806 | 2.01k | : TS.emitDirectiveNaNLegacy()1.74k ; |
807 | 2.01k | |
808 | 2.01k | // TODO: handle O64 ABI |
809 | 2.01k | |
810 | 2.01k | TS.updateABIInfo(STI); |
811 | 2.01k | |
812 | 2.01k | // We should always emit a '.module fp=...' but binutils 2.24 does not accept |
813 | 2.01k | // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or |
814 | 2.01k | // -mfp64) and omit it otherwise. |
815 | 2.01k | if ((ABI.IsO32() && (1.34k STI.isABI_FPXX()1.34k || STI.isFP64bit()1.33k )) || |
816 | 2.01k | STI.useSoftFloat()1.63k ) |
817 | 449 | TS.emitDirectiveModuleFP(); |
818 | 2.01k | |
819 | 2.01k | // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not |
820 | 2.01k | // accept it. We therefore emit it when it contradicts the default or an |
821 | 2.01k | // option has changed the default (i.e. FPXX) and omit it otherwise. |
822 | 2.01k | if (ABI.IsO32() && (1.34k !STI.useOddSPReg()1.34k || STI.isABI_FPXX()1.33k )) |
823 | 22 | TS.emitDirectiveModuleOddSPReg(); |
824 | 2.01k | } |
825 | | |
826 | 481 | void MipsAsmPrinter::emitInlineAsmStart() const { |
827 | 481 | MipsTargetStreamer &TS = getTargetStreamer(); |
828 | 481 | |
829 | 481 | // GCC's choice of assembler options for inline assembly code ('at', 'macro' |
830 | 481 | // and 'reorder') is different from LLVM's choice for generated code ('noat', |
831 | 481 | // 'nomacro' and 'noreorder'). |
832 | 481 | // In order to maintain compatibility with inline assembly code which depends |
833 | 481 | // on GCC's assembler options being used, we have to switch to those options |
834 | 481 | // for the duration of the inline assembly block and then switch back. |
835 | 481 | TS.emitDirectiveSetPush(); |
836 | 481 | TS.emitDirectiveSetAt(); |
837 | 481 | TS.emitDirectiveSetMacro(); |
838 | 481 | TS.emitDirectiveSetReorder(); |
839 | 481 | OutStreamer->AddBlankLine(); |
840 | 481 | } |
841 | | |
842 | | void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, |
843 | 481 | const MCSubtargetInfo *EndInfo) const { |
844 | 481 | OutStreamer->AddBlankLine(); |
845 | 481 | getTargetStreamer().emitDirectiveSetPop(); |
846 | 481 | } |
847 | | |
848 | 100 | void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) { |
849 | 100 | MCInst I; |
850 | 100 | I.setOpcode(Mips::JAL); |
851 | 100 | I.addOperand( |
852 | 100 | MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext))); |
853 | 100 | OutStreamer->EmitInstruction(I, STI); |
854 | 100 | } |
855 | | |
856 | | void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, |
857 | 100 | unsigned Reg) { |
858 | 100 | MCInst I; |
859 | 100 | I.setOpcode(Opcode); |
860 | 100 | I.addOperand(MCOperand::createReg(Reg)); |
861 | 100 | OutStreamer->EmitInstruction(I, STI); |
862 | 100 | } |
863 | | |
864 | | void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI, |
865 | | unsigned Opcode, unsigned Reg1, |
866 | 150 | unsigned Reg2) { |
867 | 150 | MCInst I; |
868 | 150 | // |
869 | 150 | // Because of the current td files for Mips32, the operands for MTC1 |
870 | 150 | // appear backwards from their normal assembly order. It's not a trivial |
871 | 150 | // change to fix this in the td file so we adjust for it here. |
872 | 150 | // |
873 | 150 | if (Opcode == Mips::MTC1) { |
874 | 90 | unsigned Temp = Reg1; |
875 | 90 | Reg1 = Reg2; |
876 | 90 | Reg2 = Temp; |
877 | 90 | } |
878 | 150 | I.setOpcode(Opcode); |
879 | 150 | I.addOperand(MCOperand::createReg(Reg1)); |
880 | 150 | I.addOperand(MCOperand::createReg(Reg2)); |
881 | 150 | OutStreamer->EmitInstruction(I, STI); |
882 | 150 | } |
883 | | |
884 | | void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI, |
885 | | unsigned Opcode, unsigned Reg1, |
886 | 100 | unsigned Reg2, unsigned Reg3) { |
887 | 100 | MCInst I; |
888 | 100 | I.setOpcode(Opcode); |
889 | 100 | I.addOperand(MCOperand::createReg(Reg1)); |
890 | 100 | I.addOperand(MCOperand::createReg(Reg2)); |
891 | 100 | I.addOperand(MCOperand::createReg(Reg3)); |
892 | 100 | OutStreamer->EmitInstruction(I, STI); |
893 | 100 | } |
894 | | |
895 | | void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI, |
896 | | unsigned MovOpc, unsigned Reg1, |
897 | | unsigned Reg2, unsigned FPReg1, |
898 | 50 | unsigned FPReg2, bool LE) { |
899 | 50 | if (!LE) { |
900 | 0 | unsigned temp = Reg1; |
901 | 0 | Reg1 = Reg2; |
902 | 0 | Reg2 = temp; |
903 | 0 | } |
904 | 50 | EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); |
905 | 50 | EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); |
906 | 50 | } |
907 | | |
908 | | void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI, |
909 | | Mips16HardFloatInfo::FPParamVariant PV, |
910 | 100 | bool LE, bool ToFP) { |
911 | 100 | using namespace Mips16HardFloatInfo; |
912 | 100 | |
913 | 100 | unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC10 ; |
914 | 100 | switch (PV) { |
915 | 100 | case FSig: |
916 | 30 | EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12); |
917 | 30 | break; |
918 | 100 | case FFSig: |
919 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE); |
920 | 0 | break; |
921 | 100 | case FDSig: |
922 | 0 | EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12); |
923 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); |
924 | 0 | break; |
925 | 100 | case DSig: |
926 | 30 | EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); |
927 | 30 | break; |
928 | 100 | case DDSig: |
929 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); |
930 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); |
931 | 0 | break; |
932 | 100 | case DFSig: |
933 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); |
934 | 0 | EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14); |
935 | 0 | break; |
936 | 100 | case NoSig: |
937 | 40 | return; |
938 | 100 | } |
939 | 100 | } |
940 | | |
941 | | void MipsAsmPrinter::EmitSwapFPIntRetval( |
942 | | const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV, |
943 | 100 | bool LE) { |
944 | 100 | using namespace Mips16HardFloatInfo; |
945 | 100 | |
946 | 100 | unsigned MovOpc = Mips::MFC1; |
947 | 100 | switch (RV) { |
948 | 100 | case FRet: |
949 | 20 | EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0); |
950 | 20 | break; |
951 | 100 | case DRet: |
952 | 20 | EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); |
953 | 20 | break; |
954 | 100 | case CFRet: |
955 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); |
956 | 0 | break; |
957 | 100 | case CDRet: |
958 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); |
959 | 0 | EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE); |
960 | 0 | break; |
961 | 100 | case NoFPRet: |
962 | 60 | break; |
963 | 100 | } |
964 | 100 | } |
965 | | |
966 | | void MipsAsmPrinter::EmitFPCallStub( |
967 | 100 | const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) { |
968 | 100 | using namespace Mips16HardFloatInfo; |
969 | 100 | |
970 | 100 | MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol)); |
971 | 100 | bool LE = getDataLayout().isLittleEndian(); |
972 | 100 | // Construct a local MCSubtargetInfo here. |
973 | 100 | // This is because the MachineFunction won't exist (but have not yet been |
974 | 100 | // freed) and since we're at the global level we can use the default |
975 | 100 | // constructed subtarget. |
976 | 100 | std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo( |
977 | 100 | TM.getTargetTriple().str(), TM.getTargetCPU(), |
978 | 100 | TM.getTargetFeatureString())); |
979 | 100 | |
980 | 100 | // |
981 | 100 | // .global xxxx |
982 | 100 | // |
983 | 100 | OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global); |
984 | 100 | const char *RetType; |
985 | 100 | // |
986 | 100 | // make the comment field identifying the return and parameter |
987 | 100 | // types of the floating point stub |
988 | 100 | // # Stub function to call rettype xxxx (params) |
989 | 100 | // |
990 | 100 | switch (Signature->RetSig) { |
991 | 100 | case FRet: |
992 | 20 | RetType = "float"; |
993 | 20 | break; |
994 | 100 | case DRet: |
995 | 20 | RetType = "double"; |
996 | 20 | break; |
997 | 100 | case CFRet: |
998 | 0 | RetType = "complex"; |
999 | 0 | break; |
1000 | 100 | case CDRet: |
1001 | 0 | RetType = "double complex"; |
1002 | 0 | break; |
1003 | 100 | case NoFPRet: |
1004 | 60 | RetType = ""; |
1005 | 60 | break; |
1006 | 100 | } |
1007 | 100 | const char *Parms; |
1008 | 100 | switch (Signature->ParamSig) { |
1009 | 100 | case FSig: |
1010 | 30 | Parms = "float"; |
1011 | 30 | break; |
1012 | 100 | case FFSig: |
1013 | 0 | Parms = "float, float"; |
1014 | 0 | break; |
1015 | 100 | case FDSig: |
1016 | 0 | Parms = "float, double"; |
1017 | 0 | break; |
1018 | 100 | case DSig: |
1019 | 30 | Parms = "double"; |
1020 | 30 | break; |
1021 | 100 | case DDSig: |
1022 | 0 | Parms = "double, double"; |
1023 | 0 | break; |
1024 | 100 | case DFSig: |
1025 | 0 | Parms = "double, float"; |
1026 | 0 | break; |
1027 | 100 | case NoSig: |
1028 | 40 | Parms = ""; |
1029 | 40 | break; |
1030 | 100 | } |
1031 | 100 | OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " + |
1032 | 100 | Twine(Symbol) + " (" + Twine(Parms) + ")"); |
1033 | 100 | // |
1034 | 100 | // probably not necessary but we save and restore the current section state |
1035 | 100 | // |
1036 | 100 | OutStreamer->PushSection(); |
1037 | 100 | // |
1038 | 100 | // .section mips16.call.fpxxxx,"ax",@progbits |
1039 | 100 | // |
1040 | 100 | MCSectionELF *M = OutContext.getELFSection( |
1041 | 100 | ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS, |
1042 | 100 | ELF::SHF_ALLOC | ELF::SHF_EXECINSTR); |
1043 | 100 | OutStreamer->SwitchSection(M, nullptr); |
1044 | 100 | // |
1045 | 100 | // .align 2 |
1046 | 100 | // |
1047 | 100 | OutStreamer->EmitValueToAlignment(4); |
1048 | 100 | MipsTargetStreamer &TS = getTargetStreamer(); |
1049 | 100 | // |
1050 | 100 | // .set nomips16 |
1051 | 100 | // .set nomicromips |
1052 | 100 | // |
1053 | 100 | TS.emitDirectiveSetNoMips16(); |
1054 | 100 | TS.emitDirectiveSetNoMicroMips(); |
1055 | 100 | // |
1056 | 100 | // .ent __call_stub_fp_xxxx |
1057 | 100 | // .type __call_stub_fp_xxxx,@function |
1058 | 100 | // __call_stub_fp_xxxx: |
1059 | 100 | // |
1060 | 100 | std::string x = "__call_stub_fp_" + std::string(Symbol); |
1061 | 100 | MCSymbolELF *Stub = |
1062 | 100 | cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x))); |
1063 | 100 | TS.emitDirectiveEnt(*Stub); |
1064 | 100 | MCSymbol *MType = |
1065 | 100 | OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol)); |
1066 | 100 | OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction); |
1067 | 100 | OutStreamer->EmitLabel(Stub); |
1068 | 100 | |
1069 | 100 | // Only handle non-pic for now. |
1070 | 100 | assert(!isPositionIndependent() && |
1071 | 100 | "should not be here if we are compiling pic"); |
1072 | 100 | TS.emitDirectiveSetReorder(); |
1073 | 100 | // |
1074 | 100 | // We need to add a MipsMCExpr class to MCTargetDesc to fully implement |
1075 | 100 | // stubs without raw text but this current patch is for compiler generated |
1076 | 100 | // functions and they all return some value. |
1077 | 100 | // The calling sequence for non pic is different in that case and we need |
1078 | 100 | // to implement %lo and %hi in order to handle the case of no return value |
1079 | 100 | // See the corresponding method in Mips16HardFloat for details. |
1080 | 100 | // |
1081 | 100 | // mov the return address to S2. |
1082 | 100 | // we have no stack space to store it and we are about to make another call. |
1083 | 100 | // We need to make sure that the enclosing function knows to save S2 |
1084 | 100 | // This should have already been handled. |
1085 | 100 | // |
1086 | 100 | // Mov $18, $31 |
1087 | 100 | |
1088 | 100 | EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO); |
1089 | 100 | |
1090 | 100 | EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true); |
1091 | 100 | |
1092 | 100 | // Jal xxxx |
1093 | 100 | // |
1094 | 100 | EmitJal(*STI, MSymbol); |
1095 | 100 | |
1096 | 100 | // fix return values |
1097 | 100 | EmitSwapFPIntRetval(*STI, Signature->RetSig, LE); |
1098 | 100 | // |
1099 | 100 | // do the return |
1100 | 100 | // if (Signature->RetSig == NoFPRet) |
1101 | 100 | // llvm_unreachable("should not be any stubs here with no return value"); |
1102 | 100 | // else |
1103 | 100 | EmitInstrReg(*STI, Mips::JR, Mips::S2); |
1104 | 100 | |
1105 | 100 | MCSymbol *Tmp = OutContext.createTempSymbol(); |
1106 | 100 | OutStreamer->EmitLabel(Tmp); |
1107 | 100 | const MCSymbolRefExpr *E = MCSymbolRefExpr::create(Stub, OutContext); |
1108 | 100 | const MCSymbolRefExpr *T = MCSymbolRefExpr::create(Tmp, OutContext); |
1109 | 100 | const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext); |
1110 | 100 | OutStreamer->emitELFSize(Stub, T_min_E); |
1111 | 100 | TS.emitDirectiveEnd(x); |
1112 | 100 | OutStreamer->PopSection(); |
1113 | 100 | } |
1114 | | |
1115 | 2.01k | void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) { |
1116 | 2.01k | // Emit needed stubs |
1117 | 2.01k | // |
1118 | 2.01k | for (std::map< |
1119 | 2.01k | const char *, |
1120 | 2.01k | const Mips16HardFloatInfo::FuncSignature *>::const_iterator |
1121 | 2.01k | it = StubsNeeded.begin(); |
1122 | 2.11k | it != StubsNeeded.end(); ++it100 ) { |
1123 | 100 | const char *Symbol = it->first; |
1124 | 100 | const Mips16HardFloatInfo::FuncSignature *Signature = it->second; |
1125 | 100 | EmitFPCallStub(Symbol, Signature); |
1126 | 100 | } |
1127 | 2.01k | // return to the text section |
1128 | 2.01k | OutStreamer->SwitchSection(OutContext.getObjectFileInfo()->getTextSection()); |
1129 | 2.01k | } |
1130 | | |
1131 | 52 | void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) { |
1132 | 52 | const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 1526 : 1126 ; |
1133 | 52 | // For mips32 we want to emit the following pattern: |
1134 | 52 | // |
1135 | 52 | // .Lxray_sled_N: |
1136 | 52 | // ALIGN |
1137 | 52 | // B .tmpN |
1138 | 52 | // 11 NOP instructions (44 bytes) |
1139 | 52 | // ADDIU T9, T9, 52 |
1140 | 52 | // .tmpN |
1141 | 52 | // |
1142 | 52 | // We need the 44 bytes (11 instructions) because at runtime, we'd |
1143 | 52 | // be patching over the full 48 bytes (12 instructions) with the following |
1144 | 52 | // pattern: |
1145 | 52 | // |
1146 | 52 | // ADDIU SP, SP, -8 |
1147 | 52 | // NOP |
1148 | 52 | // SW RA, 4(SP) |
1149 | 52 | // SW T9, 0(SP) |
1150 | 52 | // LUI T9, %hi(__xray_FunctionEntry/Exit) |
1151 | 52 | // ORI T9, T9, %lo(__xray_FunctionEntry/Exit) |
1152 | 52 | // LUI T0, %hi(function_id) |
1153 | 52 | // JALR T9 |
1154 | 52 | // ORI T0, T0, %lo(function_id) |
1155 | 52 | // LW T9, 0(SP) |
1156 | 52 | // LW RA, 4(SP) |
1157 | 52 | // ADDIU SP, SP, 8 |
1158 | 52 | // |
1159 | 52 | // We add 52 bytes to t9 because we want to adjust the function pointer to |
1160 | 52 | // the actual start of function i.e. the address just after the noop sled. |
1161 | 52 | // We do this because gp displacement relocation is emitted at the start of |
1162 | 52 | // of the function i.e after the nop sled and to correctly calculate the |
1163 | 52 | // global offset table address, t9 must hold the address of the instruction |
1164 | 52 | // containing the gp displacement relocation. |
1165 | 52 | // FIXME: Is this correct for the static relocation model? |
1166 | 52 | // |
1167 | 52 | // For mips64 we want to emit the following pattern: |
1168 | 52 | // |
1169 | 52 | // .Lxray_sled_N: |
1170 | 52 | // ALIGN |
1171 | 52 | // B .tmpN |
1172 | 52 | // 15 NOP instructions (60 bytes) |
1173 | 52 | // .tmpN |
1174 | 52 | // |
1175 | 52 | // We need the 60 bytes (15 instructions) because at runtime, we'd |
1176 | 52 | // be patching over the full 64 bytes (16 instructions) with the following |
1177 | 52 | // pattern: |
1178 | 52 | // |
1179 | 52 | // DADDIU SP, SP, -16 |
1180 | 52 | // NOP |
1181 | 52 | // SD RA, 8(SP) |
1182 | 52 | // SD T9, 0(SP) |
1183 | 52 | // LUI T9, %highest(__xray_FunctionEntry/Exit) |
1184 | 52 | // ORI T9, T9, %higher(__xray_FunctionEntry/Exit) |
1185 | 52 | // DSLL T9, T9, 16 |
1186 | 52 | // ORI T9, T9, %hi(__xray_FunctionEntry/Exit) |
1187 | 52 | // DSLL T9, T9, 16 |
1188 | 52 | // ORI T9, T9, %lo(__xray_FunctionEntry/Exit) |
1189 | 52 | // LUI T0, %hi(function_id) |
1190 | 52 | // JALR T9 |
1191 | 52 | // ADDIU T0, T0, %lo(function_id) |
1192 | 52 | // LD T9, 0(SP) |
1193 | 52 | // LD RA, 8(SP) |
1194 | 52 | // DADDIU SP, SP, 16 |
1195 | 52 | // |
1196 | 52 | OutStreamer->EmitCodeAlignment(4); |
1197 | 52 | auto CurSled = OutContext.createTempSymbol("xray_sled_", true); |
1198 | 52 | OutStreamer->EmitLabel(CurSled); |
1199 | 52 | auto Target = OutContext.createTempSymbol(); |
1200 | 52 | |
1201 | 52 | // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual |
1202 | 52 | // start of function |
1203 | 52 | const MCExpr *TargetExpr = MCSymbolRefExpr::create( |
1204 | 52 | Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext); |
1205 | 52 | EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ) |
1206 | 52 | .addReg(Mips::ZERO) |
1207 | 52 | .addReg(Mips::ZERO) |
1208 | 52 | .addExpr(TargetExpr)); |
1209 | 52 | |
1210 | 728 | for (int8_t I = 0; I < NoopsInSledCount; I++676 ) |
1211 | 676 | EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL) |
1212 | 676 | .addReg(Mips::ZERO) |
1213 | 676 | .addReg(Mips::ZERO) |
1214 | 676 | .addImm(0)); |
1215 | 52 | |
1216 | 52 | OutStreamer->EmitLabel(Target); |
1217 | 52 | |
1218 | 52 | if (!Subtarget->isGP64bit()) { |
1219 | 26 | EmitToStreamer(*OutStreamer, |
1220 | 26 | MCInstBuilder(Mips::ADDiu) |
1221 | 26 | .addReg(Mips::T9) |
1222 | 26 | .addReg(Mips::T9) |
1223 | 26 | .addImm(0x34)); |
1224 | 26 | } |
1225 | 52 | |
1226 | 52 | recordSled(CurSled, MI, Kind); |
1227 | 52 | } |
1228 | | |
1229 | 24 | void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) { |
1230 | 24 | EmitSled(MI, SledKind::FUNCTION_ENTER); |
1231 | 24 | } |
1232 | | |
1233 | 28 | void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) { |
1234 | 28 | EmitSled(MI, SledKind::FUNCTION_EXIT); |
1235 | 28 | } |
1236 | | |
1237 | 0 | void MipsAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) { |
1238 | 0 | EmitSled(MI, SledKind::TAIL_CALL); |
1239 | 0 | } |
1240 | | |
1241 | | void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, |
1242 | 0 | raw_ostream &OS) { |
1243 | 0 | // TODO: implement |
1244 | 0 | } |
1245 | | |
1246 | | // Emit .dtprelword or .dtpreldword directive |
1247 | | // and value for debug thread local expression. |
1248 | 2 | void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const { |
1249 | 2 | if (auto *MipsExpr = dyn_cast<MipsMCExpr>(Value)) { |
1250 | 2 | if (MipsExpr && MipsExpr->getKind() == MipsMCExpr::MEK_DTPREL) { |
1251 | 2 | switch (Size) { |
1252 | 2 | case 4: |
1253 | 1 | OutStreamer->EmitDTPRel32Value(MipsExpr->getSubExpr()); |
1254 | 1 | break; |
1255 | 2 | case 8: |
1256 | 1 | OutStreamer->EmitDTPRel64Value(MipsExpr->getSubExpr()); |
1257 | 1 | break; |
1258 | 2 | default: |
1259 | 0 | llvm_unreachable("Unexpected size of expression value."); |
1260 | 2 | } |
1261 | 2 | return; |
1262 | 2 | } |
1263 | 2 | } |
1264 | 0 | AsmPrinter::EmitDebugValue(Value, Size); |
1265 | 0 | } |
1266 | | |
1267 | | // Align all targets of indirect branches on bundle size. Used only if target |
1268 | | // is NaCl. |
1269 | 25 | void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) { |
1270 | 25 | // Align all blocks that are jumped to through jump table. |
1271 | 25 | if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) { |
1272 | 1 | const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables(); |
1273 | 2 | for (unsigned I = 0; I < JT.size(); ++I1 ) { |
1274 | 1 | const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs; |
1275 | 1 | |
1276 | 5 | for (unsigned J = 0; J < MBBs.size(); ++J4 ) |
1277 | 4 | MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN); |
1278 | 1 | } |
1279 | 1 | } |
1280 | 25 | |
1281 | 25 | // If basic block address is taken, block can be target of indirect branch. |
1282 | 37 | for (auto &MBB : MF) { |
1283 | 37 | if (MBB.hasAddressTaken()) |
1284 | 2 | MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN); |
1285 | 37 | } |
1286 | 25 | } |
1287 | | |
1288 | 68 | bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const { |
1289 | 68 | return (Opcode == Mips::LONG_BRANCH_LUi |
1290 | 68 | || Opcode == Mips::LONG_BRANCH_LUi2Op53 |
1291 | 68 | || Opcode == Mips::LONG_BRANCH_LUi2Op_6449 |
1292 | 68 | || Opcode == Mips::LONG_BRANCH_ADDiu45 |
1293 | 68 | || Opcode == Mips::LONG_BRANCH_ADDiu2Op30 |
1294 | 68 | || Opcode == Mips::LONG_BRANCH_DADDiu26 |
1295 | 68 | || Opcode == Mips::LONG_BRANCH_DADDiu2Op12 ); |
1296 | 68 | } |
1297 | | |
1298 | | // Force static initialization. |
1299 | 78.9k | extern "C" void LLVMInitializeMipsAsmPrinter() { |
1300 | 78.9k | RegisterAsmPrinter<MipsAsmPrinter> X(getTheMipsTarget()); |
1301 | 78.9k | RegisterAsmPrinter<MipsAsmPrinter> Y(getTheMipselTarget()); |
1302 | 78.9k | RegisterAsmPrinter<MipsAsmPrinter> A(getTheMips64Target()); |
1303 | 78.9k | RegisterAsmPrinter<MipsAsmPrinter> B(getTheMips64elTarget()); |
1304 | 78.9k | } |