Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsFastISel.cpp
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Source (jump to first uncovered line)
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//===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
///
9
/// \file
10
/// This file defines the MIPS-specific support for the FastISel class.
11
/// Some of the target-specific code is generated by tablegen in the file
12
/// MipsGenFastISel.inc, which is #included here.
13
///
14
//===----------------------------------------------------------------------===//
15
16
#include "MCTargetDesc/MipsABIInfo.h"
17
#include "MCTargetDesc/MipsBaseInfo.h"
18
#include "MipsCCState.h"
19
#include "MipsISelLowering.h"
20
#include "MipsInstrInfo.h"
21
#include "MipsMachineFunction.h"
22
#include "MipsSubtarget.h"
23
#include "MipsTargetMachine.h"
24
#include "llvm/ADT/APInt.h"
25
#include "llvm/ADT/ArrayRef.h"
26
#include "llvm/ADT/DenseMap.h"
27
#include "llvm/ADT/SmallVector.h"
28
#include "llvm/Analysis/TargetLibraryInfo.h"
29
#include "llvm/CodeGen/CallingConvLower.h"
30
#include "llvm/CodeGen/FastISel.h"
31
#include "llvm/CodeGen/FunctionLoweringInfo.h"
32
#include "llvm/CodeGen/ISDOpcodes.h"
33
#include "llvm/CodeGen/MachineBasicBlock.h"
34
#include "llvm/CodeGen/MachineFrameInfo.h"
35
#include "llvm/CodeGen/MachineInstrBuilder.h"
36
#include "llvm/CodeGen/MachineMemOperand.h"
37
#include "llvm/CodeGen/MachineRegisterInfo.h"
38
#include "llvm/CodeGen/TargetInstrInfo.h"
39
#include "llvm/CodeGen/TargetLowering.h"
40
#include "llvm/CodeGen/ValueTypes.h"
41
#include "llvm/IR/Attributes.h"
42
#include "llvm/IR/CallingConv.h"
43
#include "llvm/IR/Constant.h"
44
#include "llvm/IR/Constants.h"
45
#include "llvm/IR/DataLayout.h"
46
#include "llvm/IR/Function.h"
47
#include "llvm/IR/GetElementPtrTypeIterator.h"
48
#include "llvm/IR/GlobalValue.h"
49
#include "llvm/IR/GlobalVariable.h"
50
#include "llvm/IR/InstrTypes.h"
51
#include "llvm/IR/Instruction.h"
52
#include "llvm/IR/Instructions.h"
53
#include "llvm/IR/IntrinsicInst.h"
54
#include "llvm/IR/Operator.h"
55
#include "llvm/IR/Type.h"
56
#include "llvm/IR/User.h"
57
#include "llvm/IR/Value.h"
58
#include "llvm/MC/MCContext.h"
59
#include "llvm/MC/MCInstrDesc.h"
60
#include "llvm/MC/MCRegisterInfo.h"
61
#include "llvm/MC/MCSymbol.h"
62
#include "llvm/Support/Casting.h"
63
#include "llvm/Support/Compiler.h"
64
#include "llvm/Support/Debug.h"
65
#include "llvm/Support/ErrorHandling.h"
66
#include "llvm/Support/MachineValueType.h"
67
#include "llvm/Support/MathExtras.h"
68
#include "llvm/Support/raw_ostream.h"
69
#include <algorithm>
70
#include <array>
71
#include <cassert>
72
#include <cstdint>
73
74
#define DEBUG_TYPE "mips-fastisel"
75
76
using namespace llvm;
77
78
extern cl::opt<bool> EmitJalrReloc;
79
80
namespace {
81
82
class MipsFastISel final : public FastISel {
83
84
  // All possible address modes.
85
  class Address {
86
  public:
87
    using BaseKind = enum { RegBase, FrameIndexBase };
88
89
  private:
90
    BaseKind Kind = RegBase;
91
    union {
92
      unsigned Reg;
93
      int FI;
94
    } Base;
95
96
    int64_t Offset = 0;
97
98
    const GlobalValue *GV = nullptr;
99
100
  public:
101
    // Innocuous defaults for our address.
102
642
    Address() { Base.Reg = 0; }
103
104
15
    void setKind(BaseKind K) { Kind = K; }
105
0
    BaseKind getKind() const { return Kind; }
106
581
    bool isRegBase() const { return Kind == RegBase; }
107
15
    bool isFIBase() const { return Kind == FrameIndexBase; }
108
109
570
    void setReg(unsigned Reg) {
110
570
      assert(isRegBase() && "Invalid base register access!");
111
570
      Base.Reg = Reg;
112
570
    }
113
114
1.13k
    unsigned getReg() const {
115
1.13k
      assert(isRegBase() && "Invalid base register access!");
116
1.13k
      return Base.Reg;
117
1.13k
    }
118
119
15
    void setFI(unsigned FI) {
120
15
      assert(isFIBase() && "Invalid base frame index access!");
121
15
      Base.FI = FI;
122
15
    }
123
124
15
    unsigned getFI() const {
125
15
      assert(isFIBase() && "Invalid base frame index access!");
126
15
      return Base.FI;
127
15
    }
128
129
14
    void setOffset(int64_t Offset_) { Offset = Offset_; }
130
1.16k
    int64_t getOffset() const { return Offset; }
131
61
    void setGlobalValue(const GlobalValue *G) { GV = G; }
132
170
    const GlobalValue *getGlobalValue() { return GV; }
133
  };
134
135
  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
136
  /// make the right decision when generating code for different targets.
137
  const TargetMachine &TM;
138
  const MipsSubtarget *Subtarget;
139
  const TargetInstrInfo &TII;
140
  const TargetLowering &TLI;
141
  MipsFunctionInfo *MFI;
142
143
  // Convenience variables to avoid some queries.
144
  LLVMContext *Context;
145
146
  bool fastLowerArguments() override;
147
  bool fastLowerCall(CallLoweringInfo &CLI) override;
148
  bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
149
150
  bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
151
  // floating point but not reject doing fast-isel in other
152
  // situations
153
154
private:
155
  // Selection routines.
156
  bool selectLogicalOp(const Instruction *I);
157
  bool selectLoad(const Instruction *I);
158
  bool selectStore(const Instruction *I);
159
  bool selectBranch(const Instruction *I);
160
  bool selectSelect(const Instruction *I);
161
  bool selectCmp(const Instruction *I);
162
  bool selectFPExt(const Instruction *I);
163
  bool selectFPTrunc(const Instruction *I);
164
  bool selectFPToInt(const Instruction *I, bool IsSigned);
165
  bool selectRet(const Instruction *I);
166
  bool selectTrunc(const Instruction *I);
167
  bool selectIntExt(const Instruction *I);
168
  bool selectShift(const Instruction *I);
169
  bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
170
171
  // Utility helper routines.
172
  bool isTypeLegal(Type *Ty, MVT &VT);
173
  bool isTypeSupported(Type *Ty, MVT &VT);
174
  bool isLoadTypeLegal(Type *Ty, MVT &VT);
175
  bool computeAddress(const Value *Obj, Address &Addr);
176
  bool computeCallAddress(const Value *V, Address &Addr);
177
  void simplifyAddress(Address &Addr);
178
179
  // Emit helper routines.
180
  bool emitCmp(unsigned DestReg, const CmpInst *CI);
181
  bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
182
                unsigned Alignment = 0);
183
  bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
184
                 MachineMemOperand *MMO = nullptr);
185
  bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
186
                 unsigned Alignment = 0);
187
  unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188
  bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
189
190
                  bool IsZExt);
191
  bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
192
193
  bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194
  bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
195
                       unsigned DestReg);
196
  bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
197
                       unsigned DestReg);
198
199
  unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
200
201
  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
202
                         const Value *RHS);
203
204
  unsigned materializeFP(const ConstantFP *CFP, MVT VT);
205
  unsigned materializeGV(const GlobalValue *GV, MVT VT);
206
  unsigned materializeInt(const Constant *C, MVT VT);
207
  unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
208
  unsigned materializeExternalCallSym(MCSymbol *Syn);
209
210
744
  MachineInstrBuilder emitInst(unsigned Opc) {
211
744
    return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
212
744
  }
213
214
1.80k
  MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
215
1.80k
    return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
216
1.80k
                   DstReg);
217
1.80k
  }
218
219
  MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
220
249
                                    unsigned MemReg, int64_t MemOffset) {
221
249
    return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
222
249
  }
223
224
  MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
225
317
                                   unsigned MemReg, int64_t MemOffset) {
226
317
    return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
227
317
  }
228
229
  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
230
                           const TargetRegisterClass *RC,
231
                           unsigned Op0, bool Op0IsKill,
232
                           unsigned Op1, bool Op1IsKill);
233
234
  // for some reason, this default is not generated by tablegen
235
  // so we explicitly generate it here.
236
  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
237
                             unsigned Op0, bool Op0IsKill, uint64_t imm1,
238
0
                             uint64_t imm2, unsigned Op3, bool Op3IsKill) {
239
0
    return 0;
240
0
  }
241
242
  // Call handling routines.
243
private:
244
  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
245
  bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
246
                       unsigned &NumBytes);
247
  bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
248
249
326
  const MipsABIInfo &getABI() const {
250
326
    return static_cast<const MipsTargetMachine &>(TM).getABI();
251
326
  }
252
253
public:
254
  // Backend specific FastISel code.
255
  explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
256
                        const TargetLibraryInfo *libInfo)
257
      : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
258
        Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
259
339
        TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
260
339
    MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
261
339
    Context = &funcInfo.Fn->getContext();
262
339
    UnsupportedFPMode = Subtarget->isFP64bit() || 
Subtarget->useSoftFloat()338
;
263
339
  }
264
265
  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
266
  unsigned fastMaterializeConstant(const Constant *C) override;
267
  bool fastSelectInstruction(const Instruction *I) override;
268
269
#include "MipsGenFastISel.inc"
270
};
271
272
} // end anonymous namespace
273
274
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
275
                    CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
276
                    CCState &State) LLVM_ATTRIBUTE_UNUSED;
277
278
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
279
                            CCValAssign::LocInfo LocInfo,
280
0
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
281
0
  llvm_unreachable("should not be called");
282
0
}
283
284
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
285
                            CCValAssign::LocInfo LocInfo,
286
0
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
287
0
  llvm_unreachable("should not be called");
288
0
}
289
290
#include "MipsGenCallingConv.inc"
291
292
61
CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
293
61
  return CC_MipsO32;
294
61
}
295
296
unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
297
42
                                     const Value *LHS, const Value *RHS) {
298
42
  // Canonicalize immediates to the RHS first.
299
42
  if (isa<ConstantInt>(LHS) && 
!isa<ConstantInt>(RHS)2
)
300
2
    std::swap(LHS, RHS);
301
42
302
42
  unsigned Opc;
303
42
  switch (ISDOpc) {
304
42
  case ISD::AND:
305
14
    Opc = Mips::AND;
306
14
    break;
307
42
  case ISD::OR:
308
14
    Opc = Mips::OR;
309
14
    break;
310
42
  case ISD::XOR:
311
14
    Opc = Mips::XOR;
312
14
    break;
313
42
  default:
314
0
    llvm_unreachable("unexpected opcode");
315
42
  }
316
42
317
42
  unsigned LHSReg = getRegForValue(LHS);
318
42
  if (!LHSReg)
319
0
    return 0;
320
42
321
42
  unsigned RHSReg;
322
42
  if (const auto *C = dyn_cast<ConstantInt>(RHS))
323
30
    RHSReg = materializeInt(C, MVT::i32);
324
12
  else
325
12
    RHSReg = getRegForValue(RHS);
326
42
  if (!RHSReg)
327
0
    return 0;
328
42
329
42
  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
330
42
  if (!ResultReg)
331
0
    return 0;
332
42
333
42
  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
334
42
  return ResultReg;
335
42
}
336
337
2
unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
338
2
  assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
339
2
         "Alloca should always return a pointer.");
340
2
341
2
  DenseMap<const AllocaInst *, int>::iterator SI =
342
2
      FuncInfo.StaticAllocaMap.find(AI);
343
2
344
2
  if (SI != FuncInfo.StaticAllocaMap.end()) {
345
2
    unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
346
2
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
347
2
            ResultReg)
348
2
        .addFrameIndex(SI->second)
349
2
        .addImm(0);
350
2
    return ResultReg;
351
2
  }
352
0
353
0
  return 0;
354
0
}
355
356
168
unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
357
168
  if (VT != MVT::i32 && 
VT != MVT::i1645
&&
VT != MVT::i823
&&
VT != MVT::i10
)
358
0
    return 0;
359
168
  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
360
168
  const ConstantInt *CI = cast<ConstantInt>(C);
361
168
  return materialize32BitInt(CI->getZExtValue(), RC);
362
168
}
363
364
unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
365
228
                                           const TargetRegisterClass *RC) {
366
228
  unsigned ResultReg = createResultReg(RC);
367
228
368
228
  if (isInt<16>(Imm)) {
369
146
    unsigned Opc = Mips::ADDiu;
370
146
    emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
371
146
    return ResultReg;
372
146
  } else 
if (82
isUInt<16>(Imm)82
) {
373
8
    emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
374
8
    return ResultReg;
375
8
  }
376
74
  unsigned Lo = Imm & 0xFFFF;
377
74
  unsigned Hi = (Imm >> 16) & 0xFFFF;
378
74
  if (Lo) {
379
70
    // Both Lo and Hi have nonzero bits.
380
70
    unsigned TmpReg = createResultReg(RC);
381
70
    emitInst(Mips::LUi, TmpReg).addImm(Hi);
382
70
    emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
383
70
  } else {
384
4
    emitInst(Mips::LUi, ResultReg).addImm(Hi);
385
4
  }
386
74
  return ResultReg;
387
74
}
388
389
46
unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
390
46
  if (UnsupportedFPMode)
391
0
    return 0;
392
46
  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
393
46
  if (VT == MVT::f32) {
394
36
    const TargetRegisterClass *RC = &Mips::FGR32RegClass;
395
36
    unsigned DestReg = createResultReg(RC);
396
36
    unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
397
36
    emitInst(Mips::MTC1, DestReg).addReg(TempReg);
398
36
    return DestReg;
399
36
  } else 
if (10
VT == MVT::f6410
) {
400
10
    const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
401
10
    unsigned DestReg = createResultReg(RC);
402
10
    unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
403
10
    unsigned TempReg2 =
404
10
        materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
405
10
    emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
406
10
    return DestReg;
407
10
  }
408
0
  return 0;
409
0
}
410
411
587
unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
412
587
  // For now 32-bit only.
413
587
  if (VT != MVT::i32)
414
0
    return 0;
415
587
  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
416
587
  unsigned DestReg = createResultReg(RC);
417
587
  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
418
587
  bool IsThreadLocal = GVar && 
GVar->isThreadLocal()532
;
419
587
  // TLS not supported at this time.
420
587
  if (IsThreadLocal)
421
0
    return 0;
422
587
  emitInst(Mips::LW, DestReg)
423
587
      .addReg(MFI->getGlobalBaseReg())
424
587
      .addGlobalAddress(GV, 0, MipsII::MO_GOT);
425
587
  if ((GV->hasInternalLinkage() ||
426
587
       
(585
GV->hasLocalLinkage()585
&&
!isa<Function>(GV)2
))) {
427
4
    unsigned TempReg = createResultReg(RC);
428
4
    emitInst(Mips::ADDiu, TempReg)
429
4
        .addReg(DestReg)
430
4
        .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
431
4
    DestReg = TempReg;
432
4
  }
433
587
  return DestReg;
434
587
}
435
436
6
unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
437
6
  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
438
6
  unsigned DestReg = createResultReg(RC);
439
6
  emitInst(Mips::LW, DestReg)
440
6
      .addReg(MFI->getGlobalBaseReg())
441
6
      .addSym(Sym, MipsII::MO_GOT);
442
6
  return DestReg;
443
6
}
444
445
// Materialize a constant into a register, and return the register
446
// number (or zero if we failed to handle it).
447
724
unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
448
724
  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
449
724
450
724
  // Only handle simple types.
451
724
  if (!CEVT.isSimple())
452
0
    return 0;
453
724
  MVT VT = CEVT.getSimpleVT();
454
724
455
724
  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
456
46
    return (UnsupportedFPMode) ? 
00
: materializeFP(CFP, VT);
457
678
  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
458
532
    return materializeGV(GV, VT);
459
146
  else if (isa<ConstantInt>(C))
460
138
    return materializeInt(C, VT);
461
8
462
8
  return 0;
463
8
}
464
465
591
bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
466
591
  const User *U = nullptr;
467
591
  unsigned Opcode = Instruction::UserOp1;
468
591
  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
469
28
    // Don't walk into other basic blocks unless the object is an alloca from
470
28
    // another block, otherwise it may not have a virtual register assigned.
471
28
    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
472
28
        
FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB13
) {
473
28
      Opcode = I->getOpcode();
474
28
      U = I;
475
28
    }
476
563
  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
477
2
    Opcode = C->getOpcode();
478
2
    U = C;
479
2
  }
480
591
  switch (Opcode) {
481
591
  default:
482
566
    break;
483
591
  case Instruction::BitCast:
484
0
    // Look through bitcasts.
485
0
    return computeAddress(U->getOperand(0), Addr);
486
591
  case Instruction::GetElementPtr: {
487
10
    Address SavedAddr = Addr;
488
10
    int64_t TmpOffset = Addr.getOffset();
489
10
    // Iterate through the GEP folding the constants into offsets where
490
10
    // we can.
491
10
    gep_type_iterator GTI = gep_type_begin(U);
492
26
    for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
493
16
         ++i, ++GTI) {
494
16
      const Value *Op = *i;
495
16
      if (StructType *STy = GTI.getStructTypeOrNull()) {
496
2
        const StructLayout *SL = DL.getStructLayout(STy);
497
2
        unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
498
2
        TmpOffset += SL->getElementOffset(Idx);
499
14
      } else {
500
14
        uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
501
14
        while (true) {
502
14
          if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
503
14
            // Constant-offset addressing.
504
14
            TmpOffset += CI->getSExtValue() * S;
505
14
            break;
506
14
          }
507
0
          if (canFoldAddIntoGEP(U, Op)) {
508
0
            // A compatible add with a constant operand. Fold the constant.
509
0
            ConstantInt *CI =
510
0
                cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
511
0
            TmpOffset += CI->getSExtValue() * S;
512
0
            // Iterate on the other operand.
513
0
            Op = cast<AddOperator>(Op)->getOperand(0);
514
0
            continue;
515
0
          }
516
0
          // Unsupported
517
0
          goto unsupported_gep;
518
0
        }
519
14
      }
520
16
    }
521
10
    // Try to grab the base operand now.
522
10
    Addr.setOffset(TmpOffset);
523
10
    if (computeAddress(U->getOperand(0), Addr))
524
10
      return true;
525
0
    // We failed, restore everything and try the other options.
526
0
    Addr = SavedAddr;
527
0
  unsupported_gep:
528
0
    break;
529
0
  }
530
15
  case Instruction::Alloca: {
531
15
    const AllocaInst *AI = cast<AllocaInst>(Obj);
532
15
    DenseMap<const AllocaInst *, int>::iterator SI =
533
15
        FuncInfo.StaticAllocaMap.find(AI);
534
15
    if (SI != FuncInfo.StaticAllocaMap.end()) {
535
15
      Addr.setKind(Address::FrameIndexBase);
536
15
      Addr.setFI(SI->second);
537
15
      return true;
538
15
    }
539
0
    break;
540
0
  }
541
566
  }
542
566
  Addr.setReg(getRegForValue(Obj));
543
566
  return Addr.getReg() != 0;
544
566
}
545
546
62
bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
547
62
  const User *U = nullptr;
548
62
  unsigned Opcode = Instruction::UserOp1;
549
62
550
62
  if (const auto *I = dyn_cast<Instruction>(V)) {
551
0
    // Check if the value is defined in the same basic block. This information
552
0
    // is crucial to know whether or not folding an operand is valid.
553
0
    if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
554
0
      Opcode = I->getOpcode();
555
0
      U = I;
556
0
    }
557
62
  } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
558
1
    Opcode = C->getOpcode();
559
1
    U = C;
560
1
  }
561
62
562
62
  switch (Opcode) {
563
62
  default:
564
61
    break;
565
62
  case Instruction::BitCast:
566
1
    // Look past bitcasts if its operand is in the same BB.
567
1
      return computeCallAddress(U->getOperand(0), Addr);
568
62
    
break0
;
569
62
  case Instruction::IntToPtr:
570
0
    // Look past no-op inttoptrs if its operand is in the same BB.
571
0
    if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
572
0
        TLI.getPointerTy(DL))
573
0
      return computeCallAddress(U->getOperand(0), Addr);
574
0
    break;
575
0
  case Instruction::PtrToInt:
576
0
    // Look past no-op ptrtoints if its operand is in the same BB.
577
0
    if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
578
0
      return computeCallAddress(U->getOperand(0), Addr);
579
0
    break;
580
61
  }
581
61
582
61
  if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
583
61
    Addr.setGlobalValue(GV);
584
61
    return true;
585
61
  }
586
0
587
0
  // If all else fails, try to materialize the value in a register.
588
0
  if (!Addr.getGlobalValue()) {
589
0
    Addr.setReg(getRegForValue(V));
590
0
    return Addr.getReg() != 0;
591
0
  }
592
0
593
0
  return false;
594
0
}
595
596
812
bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
597
812
  EVT evt = TLI.getValueType(DL, Ty, true);
598
812
  // Only handle simple types.
599
812
  if (evt == MVT::Other || !evt.isSimple())
600
0
    return false;
601
812
  VT = evt.getSimpleVT();
602
812
603
812
  // Handle all legal types, i.e. a register that will directly hold this
604
812
  // value.
605
812
  return TLI.isTypeLegal(VT);
606
812
}
607
608
66
bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
609
66
  if (Ty->isVectorTy())
610
0
    return false;
611
66
612
66
  if (isTypeLegal(Ty, VT))
613
7
    return true;
614
59
615
59
  // If this is a type than can be sign or zero-extended to a basic operation
616
59
  // go ahead and accept it now.
617
59
  if (VT == MVT::i1 || 
VT == MVT::i858
||
VT == MVT::i1633
)
618
59
    return true;
619
0
620
0
  return false;
621
0
}
622
623
582
bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
624
582
  if (isTypeLegal(Ty, VT))
625
315
    return true;
626
267
  // We will extend this in a later patch:
627
267
  //   If this is a type than can be sign or zero-extended to a basic operation
628
267
  //   go ahead and accept it now.
629
267
  if (VT == MVT::i8 || 
VT == MVT::i16125
)
630
266
    return true;
631
1
  return false;
632
1
}
633
634
// Because of how EmitCmp is called with fast-isel, you can
635
// end up with redundant "andi" instructions after the sequences emitted below.
636
// We should try and solve this issue in the future.
637
//
638
67
bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
639
67
  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
640
67
  bool IsUnsigned = CI->isUnsigned();
641
67
  unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
642
67
  if (LeftReg == 0)
643
11
    return false;
644
56
  unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
645
56
  if (RightReg == 0)
646
0
    return false;
647
56
  CmpInst::Predicate P = CI->getPredicate();
648
56
649
56
  switch (P) {
650
56
  default:
651
0
    return false;
652
56
  case CmpInst::ICMP_EQ: {
653
5
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
654
5
    emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
655
5
    emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
656
5
    break;
657
56
  }
658
56
  case CmpInst::ICMP_NE: {
659
10
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
660
10
    emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
661
10
    emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
662
10
    break;
663
56
  }
664
56
  case CmpInst::ICMP_UGT:
665
2
    emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
666
2
    break;
667
56
  case CmpInst::ICMP_ULT:
668
2
    emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
669
2
    break;
670
56
  case CmpInst::ICMP_UGE: {
671
2
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
672
2
    emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
673
2
    emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
674
2
    break;
675
56
  }
676
56
  case CmpInst::ICMP_ULE: {
677
2
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
678
2
    emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
679
2
    emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
680
2
    break;
681
56
  }
682
56
  case CmpInst::ICMP_SGT:
683
2
    emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
684
2
    break;
685
56
  case CmpInst::ICMP_SLT:
686
3
    emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
687
3
    break;
688
56
  case CmpInst::ICMP_SGE: {
689
2
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
690
2
    emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
691
2
    emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
692
2
    break;
693
56
  }
694
56
  case CmpInst::ICMP_SLE: {
695
2
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
696
2
    emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
697
2
    emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
698
2
    break;
699
56
  }
700
56
  case CmpInst::FCMP_OEQ:
701
24
  case CmpInst::FCMP_UNE:
702
24
  case CmpInst::FCMP_OLT:
703
24
  case CmpInst::FCMP_OLE:
704
24
  case CmpInst::FCMP_OGT:
705
24
  case CmpInst::FCMP_OGE: {
706
24
    if (UnsupportedFPMode)
707
0
      return false;
708
24
    bool IsFloat = Left->getType()->isFloatTy();
709
24
    bool IsDouble = Left->getType()->isDoubleTy();
710
24
    if (!IsFloat && 
!IsDouble12
)
711
0
      return false;
712
24
    unsigned Opc, CondMovOpc;
713
24
    switch (P) {
714
24
    case CmpInst::FCMP_OEQ:
715
4
      Opc = IsFloat ? 
Mips::C_EQ_S2
:
Mips::C_EQ_D322
;
716
4
      CondMovOpc = Mips::MOVT_I;
717
4
      break;
718
24
    case CmpInst::FCMP_UNE:
719
4
      Opc = IsFloat ? 
Mips::C_EQ_S2
:
Mips::C_EQ_D322
;
720
4
      CondMovOpc = Mips::MOVF_I;
721
4
      break;
722
24
    case CmpInst::FCMP_OLT:
723
4
      Opc = IsFloat ? 
Mips::C_OLT_S2
:
Mips::C_OLT_D322
;
724
4
      CondMovOpc = Mips::MOVT_I;
725
4
      break;
726
24
    case CmpInst::FCMP_OLE:
727
4
      Opc = IsFloat ? 
Mips::C_OLE_S2
:
Mips::C_OLE_D322
;
728
4
      CondMovOpc = Mips::MOVT_I;
729
4
      break;
730
24
    case CmpInst::FCMP_OGT:
731
4
      Opc = IsFloat ? 
Mips::C_ULE_S2
:
Mips::C_ULE_D322
;
732
4
      CondMovOpc = Mips::MOVF_I;
733
4
      break;
734
24
    case CmpInst::FCMP_OGE:
735
4
      Opc = IsFloat ? 
Mips::C_ULT_S2
:
Mips::C_ULT_D322
;
736
4
      CondMovOpc = Mips::MOVF_I;
737
4
      break;
738
24
    default:
739
0
      llvm_unreachable("Only switching of a subset of CCs.");
740
24
    }
741
24
    unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
742
24
    unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
743
24
    emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744
24
    emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
745
24
    emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
746
24
                 .addReg(RightReg);
747
24
    emitInst(CondMovOpc, ResultReg)
748
24
        .addReg(RegWithOne)
749
24
        .addReg(Mips::FCC0)
750
24
        .addReg(RegWithZero);
751
24
    break;
752
24
  }
753
56
  }
754
56
  return true;
755
56
}
756
757
bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
758
324
                            unsigned Alignment) {
759
324
  //
760
324
  // more cases will be handled here in following patches.
761
324
  //
762
324
  unsigned Opc;
763
324
  switch (VT.SimpleTy) {
764
324
  case MVT::i32:
765
91
    ResultReg = createResultReg(&Mips::GPR32RegClass);
766
91
    Opc = Mips::LW;
767
91
    break;
768
324
  case MVT::i16:
769
69
    ResultReg = createResultReg(&Mips::GPR32RegClass);
770
69
    Opc = Mips::LHu;
771
69
    break;
772
324
  case MVT::i8:
773
100
    ResultReg = createResultReg(&Mips::GPR32RegClass);
774
100
    Opc = Mips::LBu;
775
100
    break;
776
324
  case MVT::f32:
777
33
    if (UnsupportedFPMode)
778
0
      return false;
779
33
    ResultReg = createResultReg(&Mips::FGR32RegClass);
780
33
    Opc = Mips::LWC1;
781
33
    break;
782
33
  case MVT::f64:
783
31
    if (UnsupportedFPMode)
784
0
      return false;
785
31
    ResultReg = createResultReg(&Mips::AFGR64RegClass);
786
31
    Opc = Mips::LDC1;
787
31
    break;
788
31
  default:
789
0
    return false;
790
324
  }
791
324
  if (Addr.isRegBase()) {
792
317
    simplifyAddress(Addr);
793
317
    emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
794
317
    return true;
795
317
  }
796
7
  if (Addr.isFIBase()) {
797
7
    unsigned FI = Addr.getFI();
798
7
    unsigned Align = 4;
799
7
    int64_t Offset = Addr.getOffset();
800
7
    MachineFrameInfo &MFI = MF->getFrameInfo();
801
7
    MachineMemOperand *MMO = MF->getMachineMemOperand(
802
7
        MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
803
7
        MFI.getObjectSize(FI), Align);
804
7
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
805
7
        .addFrameIndex(FI)
806
7
        .addImm(Offset)
807
7
        .addMemOperand(MMO);
808
7
    return true;
809
7
  }
810
0
  return false;
811
0
}
812
813
bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
814
257
                             unsigned Alignment) {
815
257
  //
816
257
  // more cases will be handled here in following patches.
817
257
  //
818
257
  unsigned Opc;
819
257
  switch (VT.SimpleTy) {
820
257
  case MVT::i8:
821
42
    Opc = Mips::SB;
822
42
    break;
823
257
  case MVT::i16:
824
55
    Opc = Mips::SH;
825
55
    break;
826
257
  case MVT::i32:
827
140
    Opc = Mips::SW;
828
140
    break;
829
257
  case MVT::f32:
830
12
    if (UnsupportedFPMode)
831
0
      return false;
832
12
    Opc = Mips::SWC1;
833
12
    break;
834
12
  case MVT::f64:
835
8
    if (UnsupportedFPMode)
836
0
      return false;
837
8
    Opc = Mips::SDC1;
838
8
    break;
839
8
  default:
840
0
    return false;
841
257
  }
842
257
  if (Addr.isRegBase()) {
843
249
    simplifyAddress(Addr);
844
249
    emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
845
249
    return true;
846
249
  }
847
8
  if (Addr.isFIBase()) {
848
8
    unsigned FI = Addr.getFI();
849
8
    unsigned Align = 4;
850
8
    int64_t Offset = Addr.getOffset();
851
8
    MachineFrameInfo &MFI = MF->getFrameInfo();
852
8
    MachineMemOperand *MMO = MF->getMachineMemOperand(
853
8
        MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
854
8
        MFI.getObjectSize(FI), Align);
855
8
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
856
8
        .addReg(SrcReg)
857
8
        .addFrameIndex(FI)
858
8
        .addImm(Offset)
859
8
        .addMemOperand(MMO);
860
8
    return true;
861
8
  }
862
0
  return false;
863
0
}
864
865
42
bool MipsFastISel::selectLogicalOp(const Instruction *I) {
866
42
  MVT VT;
867
42
  if (!isTypeSupported(I->getType(), VT))
868
0
    return false;
869
42
870
42
  unsigned ResultReg;
871
42
  switch (I->getOpcode()) {
872
42
  default:
873
0
    llvm_unreachable("Unexpected instruction.");
874
42
  case Instruction::And:
875
14
    ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
876
14
    break;
877
42
  case Instruction::Or:
878
14
    ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
879
14
    break;
880
42
  case Instruction::Xor:
881
14
    ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
882
14
    break;
883
42
  }
884
42
885
42
  if (!ResultReg)
886
0
    return false;
887
42
888
42
  updateValueMap(I, ResultReg);
889
42
  return true;
890
42
}
891
892
324
bool MipsFastISel::selectLoad(const Instruction *I) {
893
324
  // Atomic loads need special handling.
894
324
  if (cast<LoadInst>(I)->isAtomic())
895
0
    return false;
896
324
897
324
  // Verify we have a legal type before going any further.
898
324
  MVT VT;
899
324
  if (!isLoadTypeLegal(I->getType(), VT))
900
0
    return false;
901
324
902
324
  // See if we can handle this address.
903
324
  Address Addr;
904
324
  if (!computeAddress(I->getOperand(0), Addr))
905
0
    return false;
906
324
907
324
  unsigned ResultReg;
908
324
  if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
909
0
    return false;
910
324
  updateValueMap(I, ResultReg);
911
324
  return true;
912
324
}
913
914
259
bool MipsFastISel::selectStore(const Instruction *I) {
915
259
  Value *Op0 = I->getOperand(0);
916
259
  unsigned SrcReg = 0;
917
259
918
259
  // Atomic stores need special handling.
919
259
  if (cast<StoreInst>(I)->isAtomic())
920
1
    return false;
921
258
922
258
  // Verify we have a legal type before going any further.
923
258
  MVT VT;
924
258
  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
925
1
    return false;
926
257
927
257
  // Get the value to be stored into a register.
928
257
  SrcReg = getRegForValue(Op0);
929
257
  if (SrcReg == 0)
930
0
    return false;
931
257
932
257
  // See if we can handle this address.
933
257
  Address Addr;
934
257
  if (!computeAddress(I->getOperand(1), Addr))
935
0
    return false;
936
257
937
257
  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
938
0
    return false;
939
257
  return true;
940
257
}
941
942
// This can cause a redundant sltiu to be generated.
943
// FIXME: try and eliminate this in a future patch.
944
16
bool MipsFastISel::selectBranch(const Instruction *I) {
945
16
  const BranchInst *BI = cast<BranchInst>(I);
946
16
  MachineBasicBlock *BrBB = FuncInfo.MBB;
947
16
  //
948
16
  // TBB is the basic block for the case where the comparison is true.
949
16
  // FBB is the basic block for the case where the comparison is false.
950
16
  // if (cond) goto TBB
951
16
  // goto FBB
952
16
  // TBB:
953
16
  //
954
16
  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
955
16
  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
956
16
957
16
  // Fold the common case of a conditional branch with a comparison
958
16
  // in the same block.
959
16
  unsigned ZExtCondReg = 0;
960
16
  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
961
16
    if (CI->hasOneUse() && 
CI->getParent() == I->getParent()15
) {
962
14
      ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
963
14
      if (!emitCmp(ZExtCondReg, CI))
964
10
        return false;
965
6
    }
966
16
  }
967
6
968
6
  // For the general case, we need to mask with 1.
969
6
  if (ZExtCondReg == 0) {
970
2
    unsigned CondReg = getRegForValue(BI->getCondition());
971
2
    if (CondReg == 0)
972
0
      return false;
973
2
974
2
    ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true);
975
2
    if (ZExtCondReg == 0)
976
0
      return false;
977
6
  }
978
6
979
6
  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
980
6
      .addReg(ZExtCondReg)
981
6
      .addMBB(TBB);
982
6
  finishCondBranch(BI->getParent(), TBB, FBB);
983
6
  return true;
984
6
}
985
986
53
bool MipsFastISel::selectCmp(const Instruction *I) {
987
53
  const CmpInst *CI = cast<CmpInst>(I);
988
53
  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
989
53
  if (!emitCmp(ResultReg, CI))
990
1
    return false;
991
52
  updateValueMap(I, ResultReg);
992
52
  return true;
993
52
}
994
995
// Attempt to fast-select a floating-point extend instruction.
996
2
bool MipsFastISel::selectFPExt(const Instruction *I) {
997
2
  if (UnsupportedFPMode)
998
0
    return false;
999
2
  Value *Src = I->getOperand(0);
1000
2
  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1001
2
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1002
2
1003
2
  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1004
0
    return false;
1005
2
1006
2
  unsigned SrcReg =
1007
2
      getRegForValue(Src); // this must be a 32bit floating point register class
1008
2
                           // maybe we should handle this differently
1009
2
  if (!SrcReg)
1010
0
    return false;
1011
2
1012
2
  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
1013
2
  emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1014
2
  updateValueMap(I, DestReg);
1015
2
  return true;
1016
2
}
1017
1018
8
bool MipsFastISel::selectSelect(const Instruction *I) {
1019
8
  assert(isa<SelectInst>(I) && "Expected a select instruction.");
1020
8
1021
8
  LLVM_DEBUG(dbgs() << "selectSelect\n");
1022
8
1023
8
  MVT VT;
1024
8
  if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1025
0
    LLVM_DEBUG(
1026
0
        dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1027
0
    return false;
1028
0
  }
1029
8
1030
8
  unsigned CondMovOpc;
1031
8
  const TargetRegisterClass *RC;
1032
8
1033
8
  if (VT.isInteger() && 
!VT.isVector()4
&&
VT.getSizeInBits() <= 324
) {
1034
4
    CondMovOpc = Mips::MOVN_I_I;
1035
4
    RC = &Mips::GPR32RegClass;
1036
4
  } else if (VT == MVT::f32) {
1037
2
    CondMovOpc = Mips::MOVN_I_S;
1038
2
    RC = &Mips::FGR32RegClass;
1039
2
  } else if (VT == MVT::f64) {
1040
2
    CondMovOpc = Mips::MOVN_I_D32;
1041
2
    RC = &Mips::AFGR64RegClass;
1042
2
  } else
1043
0
    return false;
1044
8
1045
8
  const SelectInst *SI = cast<SelectInst>(I);
1046
8
  const Value *Cond = SI->getCondition();
1047
8
  unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1048
8
  unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1049
8
  unsigned CondReg = getRegForValue(Cond);
1050
8
1051
8
  if (!Src1Reg || !Src2Reg || !CondReg)
1052
0
    return false;
1053
8
1054
8
  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1055
8
  if (!ZExtCondReg)
1056
0
    return false;
1057
8
1058
8
  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1059
0
    return false;
1060
8
1061
8
  unsigned ResultReg = createResultReg(RC);
1062
8
  unsigned TempReg = createResultReg(RC);
1063
8
1064
8
  if (!ResultReg || !TempReg)
1065
0
    return false;
1066
8
1067
8
  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1068
8
  emitInst(CondMovOpc, ResultReg)
1069
8
    .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1070
8
  updateValueMap(I, ResultReg);
1071
8
  return true;
1072
8
}
1073
1074
// Attempt to fast-select a floating-point truncate instruction.
1075
2
bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1076
2
  if (UnsupportedFPMode)
1077
0
    return false;
1078
2
  Value *Src = I->getOperand(0);
1079
2
  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1080
2
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1081
2
1082
2
  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1083
0
    return false;
1084
2
1085
2
  unsigned SrcReg = getRegForValue(Src);
1086
2
  if (!SrcReg)
1087
0
    return false;
1088
2
1089
2
  unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1090
2
  if (!DestReg)
1091
0
    return false;
1092
2
1093
2
  emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1094
2
  updateValueMap(I, DestReg);
1095
2
  return true;
1096
2
}
1097
1098
// Attempt to fast-select a floating-point-to-integer conversion.
1099
4
bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1100
4
  if (UnsupportedFPMode)
1101
0
    return false;
1102
4
  MVT DstVT, SrcVT;
1103
4
  if (!IsSigned)
1104
0
    return false; // We don't handle this case yet. There is no native
1105
4
                  // instruction for this but it can be synthesized.
1106
4
  Type *DstTy = I->getType();
1107
4
  if (!isTypeLegal(DstTy, DstVT))
1108
0
    return false;
1109
4
1110
4
  if (DstVT != MVT::i32)
1111
0
    return false;
1112
4
1113
4
  Value *Src = I->getOperand(0);
1114
4
  Type *SrcTy = Src->getType();
1115
4
  if (!isTypeLegal(SrcTy, SrcVT))
1116
0
    return false;
1117
4
1118
4
  if (SrcVT != MVT::f32 && 
SrcVT != MVT::f642
)
1119
0
    return false;
1120
4
1121
4
  unsigned SrcReg = getRegForValue(Src);
1122
4
  if (SrcReg == 0)
1123
0
    return false;
1124
4
1125
4
  // Determine the opcode for the conversion, which takes place
1126
4
  // entirely within FPRs.
1127
4
  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1128
4
  unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1129
4
  unsigned Opc = (SrcVT == MVT::f32) ? 
Mips::TRUNC_W_S2
:
Mips::TRUNC_W_D322
;
1130
4
1131
4
  // Generate the convert.
1132
4
  emitInst(Opc, TempReg).addReg(SrcReg);
1133
4
  emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1134
4
1135
4
  updateValueMap(I, DestReg);
1136
4
  return true;
1137
4
}
1138
1139
bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1140
                                   SmallVectorImpl<MVT> &OutVTs,
1141
61
                                   unsigned &NumBytes) {
1142
61
  CallingConv::ID CC = CLI.CallConv;
1143
61
  SmallVector<CCValAssign, 16> ArgLocs;
1144
61
  CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1145
61
  CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1146
61
  // Get a count of how many bytes are to be pushed on the stack.
1147
61
  NumBytes = CCInfo.getNextStackOffset();
1148
61
  // This is the minimum argument area used for A0-A3.
1149
61
  if (NumBytes < 16)
1150
43
    NumBytes = 16;
1151
61
1152
61
  emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1153
61
  // Process the args.
1154
61
  MVT firstMVT;
1155
217
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i156
) {
1156
156
    CCValAssign &VA = ArgLocs[i];
1157
156
    const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1158
156
    MVT ArgVT = OutVTs[VA.getValNo()];
1159
156
1160
156
    if (i == 0) {
1161
58
      firstMVT = ArgVT;
1162
58
      if (ArgVT == MVT::f32) {
1163
10
        VA.convertToReg(Mips::F12);
1164
48
      } else if (ArgVT == MVT::f64) {
1165
4
        VA.convertToReg(Mips::D6);
1166
4
      }
1167
98
    } else if (i == 1) {
1168
48
      if ((firstMVT == MVT::f32) || 
(firstMVT == MVT::f64)40
) {
1169
10
        if (ArgVT == MVT::f32) {
1170
2
          VA.convertToReg(Mips::F14);
1171
8
        } else if (ArgVT == MVT::f64) {
1172
2
          VA.convertToReg(Mips::D7);
1173
2
        }
1174
10
      }
1175
48
    }
1176
156
    if (((ArgVT == MVT::i32) || 
(ArgVT == MVT::f32)78
||
(ArgVT == MVT::i16)48
||
1177
156
         
(ArgVT == MVT::i8)28
) &&
1178
156
        
VA.isMemLoc()150
) {
1179
138
      switch (VA.getLocMemOffset()) {
1180
138
      case 0:
1181
44
        VA.convertToReg(Mips::A0);
1182
44
        break;
1183
138
      case 4:
1184
44
        VA.convertToReg(Mips::A1);
1185
44
        break;
1186
138
      case 8:
1187
34
        VA.convertToReg(Mips::A2);
1188
34
        break;
1189
138
      case 12:
1190
16
        VA.convertToReg(Mips::A3);
1191
16
        break;
1192
138
      default:
1193
0
        break;
1194
156
      }
1195
156
    }
1196
156
    unsigned ArgReg = getRegForValue(ArgVal);
1197
156
    if (!ArgReg)
1198
0
      return false;
1199
156
1200
156
    // Handle arg promotion: SExt, ZExt, AExt.
1201
156
    switch (VA.getLocInfo()) {
1202
156
    case CCValAssign::Full:
1203
114
      break;
1204
156
    case CCValAssign::AExt:
1205
42
    case CCValAssign::SExt: {
1206
42
      MVT DestVT = VA.getLocVT();
1207
42
      MVT SrcVT = ArgVT;
1208
42
      ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1209
42
      if (!ArgReg)
1210
0
        return false;
1211
42
      break;
1212
42
    }
1213
42
    case CCValAssign::ZExt: {
1214
0
      MVT DestVT = VA.getLocVT();
1215
0
      MVT SrcVT = ArgVT;
1216
0
      ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1217
0
      if (!ArgReg)
1218
0
        return false;
1219
0
      break;
1220
0
    }
1221
0
    default:
1222
0
      llvm_unreachable("Unknown arg promotion!");
1223
156
    }
1224
156
1225
156
    // Now copy/store arg to correct locations.
1226
156
    if (VA.isRegLoc() && !VA.needsCustom()) {
1227
156
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1228
156
              TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1229
156
      CLI.OutRegs.push_back(VA.getLocReg());
1230
156
    } else 
if (0
VA.needsCustom()0
) {
1231
0
      llvm_unreachable("Mips does not use custom args.");
1232
0
      return false;
1233
0
    } else {
1234
0
      //
1235
0
      // FIXME: This path will currently return false. It was copied
1236
0
      // from the AArch64 port and should be essentially fine for Mips too.
1237
0
      // The work to finish up this path will be done in a follow-on patch.
1238
0
      //
1239
0
      assert(VA.isMemLoc() && "Assuming store on stack.");
1240
0
      // Don't emit stores for undef values.
1241
0
      if (isa<UndefValue>(ArgVal))
1242
0
        continue;
1243
0
1244
0
      // Need to store on the stack.
1245
0
      // FIXME: This alignment is incorrect but this path is disabled
1246
0
      // for now (will return false). We need to determine the right alignment
1247
0
      // based on the normal alignment for the underlying machine type.
1248
0
      //
1249
0
      unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1250
0
1251
0
      unsigned BEAlign = 0;
1252
0
      if (ArgSize < 8 && !Subtarget->isLittle())
1253
0
        BEAlign = 8 - ArgSize;
1254
0
1255
0
      Address Addr;
1256
0
      Addr.setKind(Address::RegBase);
1257
0
      Addr.setReg(Mips::SP);
1258
0
      Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1259
0
1260
0
      unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1261
0
      MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1262
0
          MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1263
0
          MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1264
0
      (void)(MMO);
1265
0
      // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1266
0
      return false; // can't store on the stack yet.
1267
0
    }
1268
156
  }
1269
61
1270
61
  return true;
1271
61
}
1272
1273
bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1274
61
                              unsigned NumBytes) {
1275
61
  CallingConv::ID CC = CLI.CallConv;
1276
61
  emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1277
61
  if (RetVT != MVT::isVoid) {
1278
0
    SmallVector<CCValAssign, 16> RVLocs;
1279
0
    MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1280
0
1281
0
    CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1282
0
                             CLI.Symbol ? CLI.Symbol->getName().data()
1283
0
                                        : nullptr);
1284
0
1285
0
    // Only handle a single return value.
1286
0
    if (RVLocs.size() != 1)
1287
0
      return false;
1288
0
    // Copy all of the result registers out of their specified physreg.
1289
0
    MVT CopyVT = RVLocs[0].getValVT();
1290
0
    // Special handling for extended integers.
1291
0
    if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1292
0
      CopyVT = MVT::i32;
1293
0
1294
0
    unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1295
0
    if (!ResultReg)
1296
0
      return false;
1297
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1298
0
            TII.get(TargetOpcode::COPY),
1299
0
            ResultReg).addReg(RVLocs[0].getLocReg());
1300
0
    CLI.InRegs.push_back(RVLocs[0].getLocReg());
1301
0
1302
0
    CLI.ResultReg = ResultReg;
1303
0
    CLI.NumResultRegs = 1;
1304
0
  }
1305
61
  return true;
1306
61
}
1307
1308
339
bool MipsFastISel::fastLowerArguments() {
1309
339
  LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1310
339
1311
339
  if (!FuncInfo.CanLowerReturn) {
1312
0
    LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1313
0
    return false;
1314
0
  }
1315
339
1316
339
  const Function *F = FuncInfo.Fn;
1317
339
  if (F->isVarArg()) {
1318
0
    LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1319
0
    return false;
1320
0
  }
1321
339
1322
339
  CallingConv::ID CC = F->getCallingConv();
1323
339
  if (CC != CallingConv::C) {
1324
0
    LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1325
0
    return false;
1326
0
  }
1327
339
1328
339
  std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1329
339
                                           Mips::A3}};
1330
339
  std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1331
339
  std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1332
339
  auto NextGPR32 = GPR32ArgRegs.begin();
1333
339
  auto NextFGR32 = FGR32ArgRegs.begin();
1334
339
  auto NextAFGR64 = AFGR64ArgRegs.begin();
1335
339
1336
339
  struct AllocatedReg {
1337
339
    const TargetRegisterClass *RC;
1338
339
    unsigned Reg;
1339
339
    AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1340
339
        : RC(RC), Reg(Reg) 
{}86
1341
339
  };
1342
339
1343
339
  // Only handle simple cases. i.e. All arguments are directly mapped to
1344
339
  // registers of the appropriate type.
1345
339
  SmallVector<AllocatedReg, 4> Allocation;
1346
339
  for (const auto &FormalArg : F->args()) {
1347
99
    if (FormalArg.hasAttribute(Attribute::InReg) ||
1348
99
        FormalArg.hasAttribute(Attribute::StructRet) ||
1349
99
        FormalArg.hasAttribute(Attribute::ByVal)) {
1350
0
      LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1351
0
      return false;
1352
0
    }
1353
99
1354
99
    Type *ArgTy = FormalArg.getType();
1355
99
    if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1356
0
      LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1357
0
      return false;
1358
0
    }
1359
99
1360
99
    EVT ArgVT = TLI.getValueType(DL, ArgTy);
1361
99
    LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1362
99
                      << ArgVT.getEVTString() << "\n");
1363
99
    if (!ArgVT.isSimple()) {
1364
0
      LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1365
0
      return false;
1366
0
    }
1367
99
1368
99
    switch (ArgVT.getSimpleVT().SimpleTy) {
1369
99
    case MVT::i1:
1370
13
    case MVT::i8:
1371
13
    case MVT::i16:
1372
13
      if (!FormalArg.hasAttribute(Attribute::SExt) &&
1373
13
          
!FormalArg.hasAttribute(Attribute::ZExt)4
) {
1374
4
        // It must be any extend, this shouldn't happen for clang-generated IR
1375
4
        // so just fall back on SelectionDAG.
1376
4
        LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1377
4
        return false;
1378
4
      }
1379
9
1380
9
      if (NextGPR32 == GPR32ArgRegs.end()) {
1381
0
        LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1382
0
        return false;
1383
0
      }
1384
9
1385
9
      LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1386
9
      Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1387
9
1388
9
      // Allocating any GPR32 prohibits further use of floating point arguments.
1389
9
      NextFGR32 = FGR32ArgRegs.end();
1390
9
      NextAFGR64 = AFGR64ArgRegs.end();
1391
9
      break;
1392
9
1393
74
    case MVT::i32:
1394
74
      if (FormalArg.hasAttribute(Attribute::ZExt)) {
1395
0
        // The O32 ABI does not permit a zero-extended i32.
1396
0
        LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1397
0
        return false;
1398
0
      }
1399
74
1400
74
      if (NextGPR32 == GPR32ArgRegs.end()) {
1401
3
        LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1402
3
        return false;
1403
3
      }
1404
71
1405
71
      LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1406
71
      Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1407
71
1408
71
      // Allocating any GPR32 prohibits further use of floating point arguments.
1409
71
      NextFGR32 = FGR32ArgRegs.end();
1410
71
      NextAFGR64 = AFGR64ArgRegs.end();
1411
71
      break;
1412
71
1413
71
    case MVT::f32:
1414
3
      if (UnsupportedFPMode) {
1415
0
        LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1416
0
        return false;
1417
0
      }
1418
3
      if (NextFGR32 == FGR32ArgRegs.end()) {
1419
1
        LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1420
1
        return false;
1421
1
      }
1422
2
      LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1423
2
      Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1424
2
      // Allocating an FGR32 also allocates the super-register AFGR64, and
1425
2
      // ABI rules require us to skip the corresponding GPR32.
1426
2
      if (NextGPR32 != GPR32ArgRegs.end())
1427
2
        NextGPR32++;
1428
2
      if (NextAFGR64 != AFGR64ArgRegs.end())
1429
2
        NextAFGR64++;
1430
2
      break;
1431
2
1432
7
    case MVT::f64:
1433
7
      if (UnsupportedFPMode) {
1434
2
        LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1435
2
        return false;
1436
2
      }
1437
5
      if (NextAFGR64 == AFGR64ArgRegs.end()) {
1438
1
        LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1439
1
        return false;
1440
1
      }
1441
4
      LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1442
4
      Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1443
4
      // Allocating an FGR32 also allocates the super-register AFGR64, and
1444
4
      // ABI rules require us to skip the corresponding GPR32 pair.
1445
4
      if (NextGPR32 != GPR32ArgRegs.end())
1446
4
        NextGPR32++;
1447
4
      if (NextGPR32 != GPR32ArgRegs.end())
1448
4
        NextGPR32++;
1449
4
      if (NextFGR32 != FGR32ArgRegs.end())
1450
4
        NextFGR32++;
1451
4
      break;
1452
4
1453
4
    default:
1454
2
      LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1455
2
      return false;
1456
99
    }
1457
99
  }
1458
339
1459
339
  
for (const auto &FormalArg : F->args())326
{
1460
73
    unsigned ArgNo = FormalArg.getArgNo();
1461
73
    unsigned SrcReg = Allocation[ArgNo].Reg;
1462
73
    unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1463
73
    // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1464
73
    // Without this, EmitLiveInCopies may eliminate the livein if its only
1465
73
    // use is a bitcast (which isn't turned into an instruction).
1466
73
    unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1467
73
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1468
73
            TII.get(TargetOpcode::COPY), ResultReg)
1469
73
        .addReg(DstReg, getKillRegState(true));
1470
73
    updateValueMap(&FormalArg, ResultReg);
1471
73
  }
1472
326
1473
326
  // Calculate the size of the incoming arguments area.
1474
326
  // We currently reject all the cases where this would be non-zero.
1475
326
  unsigned IncomingArgSizeInBytes = 0;
1476
326
1477
326
  // Account for the reserved argument area on ABI's that have one (O32).
1478
326
  // It seems strange to do this on the caller side but it's necessary in
1479
326
  // SelectionDAG's implementation.
1480
326
  IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1481
326
                                    IncomingArgSizeInBytes);
1482
326
1483
326
  MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1484
326
                                                    false);
1485
326
1486
326
  return true;
1487
339
}
1488
1489
69
bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1490
69
  CallingConv::ID CC = CLI.CallConv;
1491
69
  bool IsTailCall = CLI.IsTailCall;
1492
69
  bool IsVarArg = CLI.IsVarArg;
1493
69
  const Value *Callee = CLI.Callee;
1494
69
  MCSymbol *Symbol = CLI.Symbol;
1495
69
1496
69
  // Do not handle FastCC.
1497
69
  if (CC == CallingConv::Fast)
1498
1
    return false;
1499
68
1500
68
  // Allow SelectionDAG isel to handle tail calls.
1501
68
  if (IsTailCall)
1502
3
    return false;
1503
65
1504
65
  // Let SDISel handle vararg functions.
1505
65
  if (IsVarArg)
1506
4
    return false;
1507
61
1508
61
  // FIXME: Only handle *simple* calls for now.
1509
61
  MVT RetVT;
1510
61
  if (CLI.RetTy->isVoidTy())
1511
61
    RetVT = MVT::isVoid;
1512
0
  else if (!isTypeSupported(CLI.RetTy, RetVT))
1513
0
    return false;
1514
61
1515
61
  for (auto Flag : CLI.OutFlags)
1516
156
    if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1517
0
      return false;
1518
61
1519
61
  // Set up the argument vectors.
1520
61
  SmallVector<MVT, 16> OutVTs;
1521
61
  OutVTs.reserve(CLI.OutVals.size());
1522
61
1523
156
  for (auto *Val : CLI.OutVals) {
1524
156
    MVT VT;
1525
156
    if (!isTypeLegal(Val->getType(), VT) &&
1526
156
        
!(42
VT == MVT::i142
||
VT == MVT::i842
||
VT == MVT::i1620
))
1527
0
      return false;
1528
156
1529
156
    // We don't handle vector parameters yet.
1530
156
    if (VT.isVector() || VT.getSizeInBits() > 64)
1531
0
      return false;
1532
156
1533
156
    OutVTs.push_back(VT);
1534
156
  }
1535
61
1536
61
  Address Addr;
1537
61
  if (!computeCallAddress(Callee, Addr))
1538
0
    return false;
1539
61
1540
61
  // Handle the arguments now that we've gotten them.
1541
61
  unsigned NumBytes;
1542
61
  if (!processCallArgs(CLI, OutVTs, NumBytes))
1543
0
    return false;
1544
61
1545
61
  if (!Addr.getGlobalValue())
1546
0
    return false;
1547
61
1548
61
  // Issue the call.
1549
61
  unsigned DestAddress;
1550
61
  if (Symbol)
1551
6
    DestAddress = materializeExternalCallSym(Symbol);
1552
55
  else
1553
55
    DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1554
61
  emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1555
61
  MachineInstrBuilder MIB =
1556
61
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1557
61
              Mips::RA).addReg(Mips::T9);
1558
61
1559
61
  // Add implicit physical register uses to the call.
1560
61
  for (auto Reg : CLI.OutRegs)
1561
156
    MIB.addReg(Reg, RegState::Implicit);
1562
61
1563
61
  // Add a register mask with the call-preserved registers.
1564
61
  // Proper defs for return values will be added by setPhysRegsDeadExcept().
1565
61
  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1566
61
1567
61
  CLI.Call = MIB;
1568
61
1569
61
  if (EmitJalrReloc && 
!Subtarget->inMips16Mode()60
) {
1570
60
    // Attach callee address to the instruction, let asm printer emit
1571
60
    // .reloc R_MIPS_JALR.
1572
60
    if (Symbol)
1573
6
      MIB.addSym(Symbol, MipsII::MO_JALR);
1574
54
    else
1575
54
      MIB.addSym(FuncInfo.MF->getContext().getOrCreateSymbol(
1576
54
                     Addr.getGlobalValue()->getName()), MipsII::MO_JALR);
1577
60
  }
1578
61
1579
61
  // Finish off the call including any return values.
1580
61
  return finishCall(CLI, RetVT, NumBytes);
1581
61
}
1582
1583
22
bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1584
22
  switch (II->getIntrinsicID()) {
1585
22
  default:
1586
12
    return false;
1587
22
  case Intrinsic::bswap: {
1588
4
    Type *RetTy = II->getCalledFunction()->getReturnType();
1589
4
1590
4
    MVT VT;
1591
4
    if (!isTypeSupported(RetTy, VT))
1592
0
      return false;
1593
4
1594
4
    unsigned SrcReg = getRegForValue(II->getOperand(0));
1595
4
    if (SrcReg == 0)
1596
0
      return false;
1597
4
    unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1598
4
    if (DestReg == 0)
1599
0
      return false;
1600
4
    if (VT == MVT::i16) {
1601
2
      if (Subtarget->hasMips32r2()) {
1602
1
        emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1603
1
        updateValueMap(II, DestReg);
1604
1
        return true;
1605
1
      } else {
1606
1
        unsigned TempReg[3];
1607
4
        for (int i = 0; i < 3; 
i++3
) {
1608
3
          TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1609
3
          if (TempReg[i] == 0)
1610
0
            return false;
1611
3
        }
1612
1
        emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1613
1
        emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1614
1
        emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1615
1
        emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1616
1
        updateValueMap(II, DestReg);
1617
1
        return true;
1618
2
      }
1619
2
    } else if (VT == MVT::i32) {
1620
2
      if (Subtarget->hasMips32r2()) {
1621
1
        unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1622
1
        emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1623
1
        emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1624
1
        updateValueMap(II, DestReg);
1625
1
        return true;
1626
1
      } else {
1627
1
        unsigned TempReg[8];
1628
9
        for (int i = 0; i < 8; 
i++8
) {
1629
8
          TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1630
8
          if (TempReg[i] == 0)
1631
0
            return false;
1632
8
        }
1633
1
1634
1
        emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1635
1
        emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1636
1
        emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1637
1
        emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1638
1
1639
1
        emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1640
1
        emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1641
1
1642
1
        emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1643
1
        emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1644
1
        emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1645
1
        updateValueMap(II, DestReg);
1646
1
        return true;
1647
0
      }
1648
2
    }
1649
0
    return false;
1650
0
  }
1651
4
  case Intrinsic::memcpy:
1652
4
  case Intrinsic::memmove: {
1653
4
    const auto *MTI = cast<MemTransferInst>(II);
1654
4
    // Don't handle volatile.
1655
4
    if (MTI->isVolatile())
1656
0
      return false;
1657
4
    if (!MTI->getLength()->getType()->isIntegerTy(32))
1658
0
      return false;
1659
4
    const char *IntrMemName = isa<MemCpyInst>(II) ? 
"memcpy"2
:
"memmove"2
;
1660
4
    return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1661
4
  }
1662
4
  case Intrinsic::memset: {
1663
2
    const MemSetInst *MSI = cast<MemSetInst>(II);
1664
2
    // Don't handle volatile.
1665
2
    if (MSI->isVolatile())
1666
0
      return false;
1667
2
    if (!MSI->getLength()->getType()->isIntegerTy(32))
1668
0
      return false;
1669
2
    return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1670
2
  }
1671
0
  }
1672
0
  return false;
1673
0
}
1674
1675
338
bool MipsFastISel::selectRet(const Instruction *I) {
1676
338
  const Function &F = *I->getParent()->getParent();
1677
338
  const ReturnInst *Ret = cast<ReturnInst>(I);
1678
338
1679
338
  LLVM_DEBUG(dbgs() << "selectRet\n");
1680
338
1681
338
  if (!FuncInfo.CanLowerReturn)
1682
0
    return false;
1683
338
1684
338
  // Build a list of return value registers.
1685
338
  SmallVector<unsigned, 4> RetRegs;
1686
338
1687
338
  if (Ret->getNumOperands() > 0) {
1688
53
    CallingConv::ID CC = F.getCallingConv();
1689
53
1690
53
    // Do not handle FastCC.
1691
53
    if (CC == CallingConv::Fast)
1692
0
      return false;
1693
53
1694
53
    SmallVector<ISD::OutputArg, 4> Outs;
1695
53
    GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1696
53
1697
53
    // Analyze operands of the call, assigning locations to each operand.
1698
53
    SmallVector<CCValAssign, 16> ValLocs;
1699
53
    MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1700
53
                       I->getContext());
1701
53
    CCAssignFn *RetCC = RetCC_Mips;
1702
53
    CCInfo.AnalyzeReturn(Outs, RetCC);
1703
53
1704
53
    // Only handle a single return value for now.
1705
53
    if (ValLocs.size() != 1)
1706
5
      return false;
1707
48
1708
48
    CCValAssign &VA = ValLocs[0];
1709
48
    const Value *RV = Ret->getOperand(0);
1710
48
1711
48
    // Don't bother handling odd stuff for now.
1712
48
    if ((VA.getLocInfo() != CCValAssign::Full) &&
1713
48
        
(VA.getLocInfo() != CCValAssign::BCvt)0
)
1714
0
      return false;
1715
48
1716
48
    // Only handle register returns for now.
1717
48
    if (!VA.isRegLoc())
1718
0
      return false;
1719
48
1720
48
    unsigned Reg = getRegForValue(RV);
1721
48
    if (Reg == 0)
1722
0
      return false;
1723
48
1724
48
    unsigned SrcReg = Reg + VA.getValNo();
1725
48
    unsigned DestReg = VA.getLocReg();
1726
48
    // Avoid a cross-class copy. This is very unlikely.
1727
48
    if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1728
0
      return false;
1729
48
1730
48
    EVT RVEVT = TLI.getValueType(DL, RV->getType());
1731
48
    if (!RVEVT.isSimple())
1732
0
      return false;
1733
48
1734
48
    if (RVEVT.isVector())
1735
0
      return false;
1736
48
1737
48
    MVT RVVT = RVEVT.getSimpleVT();
1738
48
    if (RVVT == MVT::f128)
1739
0
      return false;
1740
48
1741
48
    // Do not handle FGR64 returns for now.
1742
48
    if (RVVT == MVT::f64 && 
UnsupportedFPMode5
) {
1743
0
      LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1744
0
      return false;
1745
0
    }
1746
48
1747
48
    MVT DestVT = VA.getValVT();
1748
48
    // Special handling for extended integers.
1749
48
    if (RVVT != DestVT) {
1750
16
      if (RVVT != MVT::i1 && 
RVVT != MVT::i813
&&
RVVT != MVT::i165
)
1751
0
        return false;
1752
16
1753
16
      if (Outs[0].Flags.isZExt() || 
Outs[0].Flags.isSExt()15
) {
1754
9
        bool IsZExt = Outs[0].Flags.isZExt();
1755
9
        SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1756
9
        if (SrcReg == 0)
1757
0
          return false;
1758
48
      }
1759
16
    }
1760
48
1761
48
    // Make the copy.
1762
48
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1763
48
            TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1764
48
1765
48
    // Add register to return instruction.
1766
48
    RetRegs.push_back(VA.getLocReg());
1767
48
  }
1768
338
  MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1769
381
  for (unsigned i = 0, e = RetRegs.size(); i != e; 
++i48
)
1770
48
    MIB.addReg(RetRegs[i], RegState::Implicit);
1771
333
  return true;
1772
338
}
1773
1774
36
bool MipsFastISel::selectTrunc(const Instruction *I) {
1775
36
  // The high bits for a type smaller than the register size are assumed to be
1776
36
  // undefined.
1777
36
  Value *Op = I->getOperand(0);
1778
36
1779
36
  EVT SrcVT, DestVT;
1780
36
  SrcVT = TLI.getValueType(DL, Op->getType(), true);
1781
36
  DestVT = TLI.getValueType(DL, I->getType(), true);
1782
36
1783
36
  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1784
0
    return false;
1785
36
  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1786
0
    return false;
1787
36
1788
36
  unsigned SrcReg = getRegForValue(Op);
1789
36
  if (!SrcReg)
1790
0
    return false;
1791
36
1792
36
  // Because the high bits are undefined, a truncate doesn't generate
1793
36
  // any code.
1794
36
  updateValueMap(I, SrcReg);
1795
36
  return true;
1796
36
}
1797
1798
131
bool MipsFastISel::selectIntExt(const Instruction *I) {
1799
131
  Type *DestTy = I->getType();
1800
131
  Value *Src = I->getOperand(0);
1801
131
  Type *SrcTy = Src->getType();
1802
131
1803
131
  bool isZExt = isa<ZExtInst>(I);
1804
131
  unsigned SrcReg = getRegForValue(Src);
1805
131
  if (!SrcReg)
1806
0
    return false;
1807
131
1808
131
  EVT SrcEVT, DestEVT;
1809
131
  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1810
131
  DestEVT = TLI.getValueType(DL, DestTy, true);
1811
131
  if (!SrcEVT.isSimple())
1812
0
    return false;
1813
131
  if (!DestEVT.isSimple())
1814
0
    return false;
1815
131
1816
131
  MVT SrcVT = SrcEVT.getSimpleVT();
1817
131
  MVT DestVT = DestEVT.getSimpleVT();
1818
131
  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1819
131
1820
131
  if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1821
0
    return false;
1822
131
  updateValueMap(I, ResultReg);
1823
131
  return true;
1824
131
}
1825
1826
bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1827
43
                                   unsigned DestReg) {
1828
43
  unsigned ShiftAmt;
1829
43
  switch (SrcVT.SimpleTy) {
1830
43
  default:
1831
0
    return false;
1832
43
  case MVT::i8:
1833
25
    ShiftAmt = 24;
1834
25
    break;
1835
43
  case MVT::i16:
1836
18
    ShiftAmt = 16;
1837
18
    break;
1838
43
  }
1839
43
  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1840
43
  emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1841
43
  emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1842
43
  return true;
1843
43
}
1844
1845
bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1846
43
                                   unsigned DestReg) {
1847
43
  switch (SrcVT.SimpleTy) {
1848
43
  default:
1849
0
    return false;
1850
43
  case MVT::i8:
1851
23
    emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1852
23
    break;
1853
43
  case MVT::i16:
1854
20
    emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1855
20
    break;
1856
43
  }
1857
43
  return true;
1858
43
}
1859
1860
bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1861
86
                               unsigned DestReg) {
1862
86
  if ((DestVT != MVT::i32) && 
(DestVT != MVT::i16)8
)
1863
0
    return false;
1864
86
  if (Subtarget->hasMips32r2())
1865
43
    return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1866
43
  return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1867
43
}
1868
1869
bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1870
118
                               unsigned DestReg) {
1871
118
  int64_t Imm;
1872
118
1873
118
  switch (SrcVT.SimpleTy) {
1874
118
  default:
1875
0
    return false;
1876
118
  case MVT::i1:
1877
86
    Imm = 1;
1878
86
    break;
1879
118
  case MVT::i8:
1880
18
    Imm = 0xff;
1881
18
    break;
1882
118
  case MVT::i16:
1883
14
    Imm = 0xffff;
1884
14
    break;
1885
118
  }
1886
118
1887
118
  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1888
118
  return true;
1889
118
}
1890
1891
bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1892
204
                              unsigned DestReg, bool IsZExt) {
1893
204
  // FastISel does not have plumbing to deal with extensions where the SrcVT or
1894
204
  // DestVT are odd things, so test to make sure that they are both types we can
1895
204
  // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1896
204
  // bail out to SelectionDAG.
1897
204
  if (((DestVT != MVT::i8) && 
(DestVT != MVT::i16)182
&&
(DestVT != MVT::i32)162
) ||
1898
204
      ((SrcVT != MVT::i1) && 
(SrcVT != MVT::i8)118
&&
(SrcVT != MVT::i16)52
))
1899
0
    return false;
1900
204
  if (IsZExt)
1901
118
    return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1902
86
  return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1903
86
}
1904
1905
unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1906
53
                                  bool isZExt) {
1907
53
  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1908
53
  bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1909
53
  return Success ? DestReg : 
00
;
1910
53
}
1911
1912
8
bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1913
8
  EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1914
8
  if (!DestEVT.isSimple())
1915
0
    return false;
1916
8
1917
8
  MVT DestVT = DestEVT.getSimpleVT();
1918
8
  if (DestVT != MVT::i32)
1919
0
    return false;
1920
8
1921
8
  unsigned DivOpc;
1922
8
  switch (ISDOpcode) {
1923
8
  default:
1924
0
    return false;
1925
8
  case ISD::SDIV:
1926
4
  case ISD::SREM:
1927
4
    DivOpc = Mips::SDIV;
1928
4
    break;
1929
4
  case ISD::UDIV:
1930
4
  case ISD::UREM:
1931
4
    DivOpc = Mips::UDIV;
1932
4
    break;
1933
8
  }
1934
8
1935
8
  unsigned Src0Reg = getRegForValue(I->getOperand(0));
1936
8
  unsigned Src1Reg = getRegForValue(I->getOperand(1));
1937
8
  if (!Src0Reg || !Src1Reg)
1938
0
    return false;
1939
8
1940
8
  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1941
8
  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1942
8
1943
8
  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1944
8
  if (!ResultReg)
1945
0
    return false;
1946
8
1947
8
  unsigned MFOpc = (ISDOpcode == ISD::SREM || 
ISDOpcode == ISD::UREM6
)
1948
8
                       ? 
Mips::MFHI4
1949
8
                       : 
Mips::MFLO4
;
1950
8
  emitInst(MFOpc, ResultReg);
1951
8
1952
8
  updateValueMap(I, ResultReg);
1953
8
  return true;
1954
8
}
1955
1956
12
bool MipsFastISel::selectShift(const Instruction *I) {
1957
12
  MVT RetVT;
1958
12
1959
12
  if (!isTypeSupported(I->getType(), RetVT))
1960
0
    return false;
1961
12
1962
12
  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1963
12
  if (!ResultReg)
1964
0
    return false;
1965
12
1966
12
  unsigned Opcode = I->getOpcode();
1967
12
  const Value *Op0 = I->getOperand(0);
1968
12
  unsigned Op0Reg = getRegForValue(Op0);
1969
12
  if (!Op0Reg)
1970
0
    return false;
1971
12
1972
12
  // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1973
12
  if (Opcode == Instruction::AShr || 
Opcode == Instruction::LShr8
) {
1974
8
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1975
8
    if (!TempReg)
1976
0
      return false;
1977
8
1978
8
    MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1979
8
    bool IsZExt = Opcode == Instruction::LShr;
1980
8
    if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1981
0
      return false;
1982
8
1983
8
    Op0Reg = TempReg;
1984
8
  }
1985
12
1986
12
  if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1987
6
    uint64_t ShiftVal = C->getZExtValue();
1988
6
1989
6
    switch (Opcode) {
1990
6
    default:
1991
0
      llvm_unreachable("Unexpected instruction.");
1992
6
    case Instruction::Shl:
1993
2
      Opcode = Mips::SLL;
1994
2
      break;
1995
6
    case Instruction::AShr:
1996
2
      Opcode = Mips::SRA;
1997
2
      break;
1998
6
    case Instruction::LShr:
1999
2
      Opcode = Mips::SRL;
2000
2
      break;
2001
6
    }
2002
6
2003
6
    emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
2004
6
    updateValueMap(I, ResultReg);
2005
6
    return true;
2006
6
  }
2007
6
2008
6
  unsigned Op1Reg = getRegForValue(I->getOperand(1));
2009
6
  if (!Op1Reg)
2010
0
    return false;
2011
6
2012
6
  switch (Opcode) {
2013
6
  default:
2014
0
    llvm_unreachable("Unexpected instruction.");
2015
6
  case Instruction::Shl:
2016
2
    Opcode = Mips::SLLV;
2017
2
    break;
2018
6
  case Instruction::AShr:
2019
2
    Opcode = Mips::SRAV;
2020
2
    break;
2021
6
  case Instruction::LShr:
2022
2
    Opcode = Mips::SRLV;
2023
2
    break;
2024
6
  }
2025
6
2026
6
  emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2027
6
  updateValueMap(I, ResultReg);
2028
6
  return true;
2029
6
}
2030
2031
1.27k
bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2032
1.27k
  switch (I->getOpcode()) {
2033
1.27k
  default:
2034
38
    break;
2035
1.27k
  case Instruction::Load:
2036
324
    return selectLoad(I);
2037
1.27k
  case Instruction::Store:
2038
259
    return selectStore(I);
2039
1.27k
  case Instruction::SDiv:
2040
2
    if (!selectBinaryOp(I, ISD::SDIV))
2041
2
      return selectDivRem(I, ISD::SDIV);
2042
0
    return true;
2043
2
  case Instruction::UDiv:
2044
2
    if (!selectBinaryOp(I, ISD::UDIV))
2045
2
      return selectDivRem(I, ISD::UDIV);
2046
0
    return true;
2047
2
  case Instruction::SRem:
2048
2
    if (!selectBinaryOp(I, ISD::SREM))
2049
2
      return selectDivRem(I, ISD::SREM);
2050
0
    return true;
2051
2
  case Instruction::URem:
2052
2
    if (!selectBinaryOp(I, ISD::UREM))
2053
2
      return selectDivRem(I, ISD::UREM);
2054
0
    return true;
2055
12
  case Instruction::Shl:
2056
12
  case Instruction::LShr:
2057
12
  case Instruction::AShr:
2058
12
    return selectShift(I);
2059
42
  case Instruction::And:
2060
42
  case Instruction::Or:
2061
42
  case Instruction::Xor:
2062
42
    return selectLogicalOp(I);
2063
42
  case Instruction::Br:
2064
16
    return selectBranch(I);
2065
338
  case Instruction::Ret:
2066
338
    return selectRet(I);
2067
42
  case Instruction::Trunc:
2068
36
    return selectTrunc(I);
2069
131
  case Instruction::ZExt:
2070
131
  case Instruction::SExt:
2071
131
    return selectIntExt(I);
2072
131
  case Instruction::FPTrunc:
2073
2
    return selectFPTrunc(I);
2074
131
  case Instruction::FPExt:
2075
2
    return selectFPExt(I);
2076
131
  case Instruction::FPToSI:
2077
4
    return selectFPToInt(I, /*isSigned*/ true);
2078
131
  case Instruction::FPToUI:
2079
0
    return selectFPToInt(I, /*isSigned*/ false);
2080
131
  case Instruction::ICmp:
2081
53
  case Instruction::FCmp:
2082
53
    return selectCmp(I);
2083
53
  case Instruction::Select:
2084
8
    return selectSelect(I);
2085
38
  }
2086
38
  return false;
2087
38
}
2088
2089
unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2090
123
                                                           bool IsUnsigned) {
2091
123
  unsigned VReg = getRegForValue(V);
2092
123
  if (VReg == 0)
2093
0
    return 0;
2094
123
  MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2095
123
2096
123
  if (VMVT == MVT::i1)
2097
11
    return 0;
2098
112
2099
112
  if ((VMVT == MVT::i8) || 
(VMVT == MVT::i16)110
) {
2100
4
    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2101
4
    if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2102
0
      return 0;
2103
4
    VReg = TempReg;
2104
4
  }
2105
112
  return VReg;
2106
112
}
2107
2108
566
void MipsFastISel::simplifyAddress(Address &Addr) {
2109
566
  if (!isInt<16>(Addr.getOffset())) {
2110
4
    unsigned TempReg =
2111
4
        materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2112
4
    unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2113
4
    emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2114
4
    Addr.setReg(DestReg);
2115
4
    Addr.setOffset(0);
2116
4
  }
2117
566
}
2118
2119
unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2120
                                       const TargetRegisterClass *RC,
2121
                                       unsigned Op0, bool Op0IsKill,
2122
22
                                       unsigned Op1, bool Op1IsKill) {
2123
22
  // We treat the MUL instruction in a special way because it clobbers
2124
22
  // the HI0 & LO0 registers. The TableGen definition of this instruction can
2125
22
  // mark these registers only as implicitly defined. As a result, the
2126
22
  // register allocator runs out of registers when this instruction is
2127
22
  // followed by another instruction that defines the same registers too.
2128
22
  // We can fix this by explicitly marking those registers as dead.
2129
22
  if (MachineInstOpcode == Mips::MUL) {
2130
2
    unsigned ResultReg = createResultReg(RC);
2131
2
    const MCInstrDesc &II = TII.get(MachineInstOpcode);
2132
2
    Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2133
2
    Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2134
2
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2135
2
      .addReg(Op0, getKillRegState(Op0IsKill))
2136
2
      .addReg(Op1, getKillRegState(Op1IsKill))
2137
2
      .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2138
2
      .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2139
2
    return ResultReg;
2140
2
  }
2141
20
2142
20
  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2143
20
                                   Op1IsKill);
2144
20
}
2145
2146
namespace llvm {
2147
2148
FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2149
339
                               const TargetLibraryInfo *libInfo) {
2150
339
  return new MipsFastISel(funcInfo, libInfo);
2151
339
}
2152
2153
} // end namespace llvm