Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsISelLowering.cpp
Line
Count
Source (jump to first uncovered line)
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//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file defines the interfaces that Mips uses to lower LLVM code into a
10
// selection DAG.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "MipsISelLowering.h"
15
#include "MCTargetDesc/MipsBaseInfo.h"
16
#include "MCTargetDesc/MipsInstPrinter.h"
17
#include "MCTargetDesc/MipsMCTargetDesc.h"
18
#include "MipsCCState.h"
19
#include "MipsInstrInfo.h"
20
#include "MipsMachineFunction.h"
21
#include "MipsRegisterInfo.h"
22
#include "MipsSubtarget.h"
23
#include "MipsTargetMachine.h"
24
#include "MipsTargetObjectFile.h"
25
#include "llvm/ADT/APFloat.h"
26
#include "llvm/ADT/ArrayRef.h"
27
#include "llvm/ADT/SmallVector.h"
28
#include "llvm/ADT/Statistic.h"
29
#include "llvm/ADT/StringRef.h"
30
#include "llvm/ADT/StringSwitch.h"
31
#include "llvm/CodeGen/CallingConvLower.h"
32
#include "llvm/CodeGen/FunctionLoweringInfo.h"
33
#include "llvm/CodeGen/ISDOpcodes.h"
34
#include "llvm/CodeGen/MachineBasicBlock.h"
35
#include "llvm/CodeGen/MachineFrameInfo.h"
36
#include "llvm/CodeGen/MachineFunction.h"
37
#include "llvm/CodeGen/MachineInstr.h"
38
#include "llvm/CodeGen/MachineInstrBuilder.h"
39
#include "llvm/CodeGen/MachineJumpTableInfo.h"
40
#include "llvm/CodeGen/MachineMemOperand.h"
41
#include "llvm/CodeGen/MachineOperand.h"
42
#include "llvm/CodeGen/MachineRegisterInfo.h"
43
#include "llvm/CodeGen/RuntimeLibcalls.h"
44
#include "llvm/CodeGen/SelectionDAG.h"
45
#include "llvm/CodeGen/SelectionDAGNodes.h"
46
#include "llvm/CodeGen/TargetFrameLowering.h"
47
#include "llvm/CodeGen/TargetInstrInfo.h"
48
#include "llvm/CodeGen/TargetRegisterInfo.h"
49
#include "llvm/CodeGen/ValueTypes.h"
50
#include "llvm/IR/CallingConv.h"
51
#include "llvm/IR/Constants.h"
52
#include "llvm/IR/DataLayout.h"
53
#include "llvm/IR/DebugLoc.h"
54
#include "llvm/IR/DerivedTypes.h"
55
#include "llvm/IR/Function.h"
56
#include "llvm/IR/GlobalValue.h"
57
#include "llvm/IR/Type.h"
58
#include "llvm/IR/Value.h"
59
#include "llvm/MC/MCContext.h"
60
#include "llvm/MC/MCRegisterInfo.h"
61
#include "llvm/Support/Casting.h"
62
#include "llvm/Support/CodeGen.h"
63
#include "llvm/Support/CommandLine.h"
64
#include "llvm/Support/Compiler.h"
65
#include "llvm/Support/ErrorHandling.h"
66
#include "llvm/Support/MachineValueType.h"
67
#include "llvm/Support/MathExtras.h"
68
#include "llvm/Target/TargetMachine.h"
69
#include "llvm/Target/TargetOptions.h"
70
#include <algorithm>
71
#include <cassert>
72
#include <cctype>
73
#include <cstdint>
74
#include <deque>
75
#include <iterator>
76
#include <utility>
77
#include <vector>
78
79
using namespace llvm;
80
81
#define DEBUG_TYPE "mips-lower"
82
83
STATISTIC(NumTailCalls, "Number of tail calls");
84
85
static cl::opt<bool>
86
LargeGOT("mxgot", cl::Hidden,
87
         cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
88
89
static cl::opt<bool>
90
NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
91
               cl::desc("MIPS: Don't trap on integer division by zero."),
92
               cl::init(false));
93
94
extern cl::opt<bool> EmitJalrReloc;
95
96
static const MCPhysReg Mips64DPRegs[8] = {
97
  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
98
  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
99
};
100
101
// If I is a shifted mask, set the size (Size) and the first bit of the
102
// mask (Pos), and return true.
103
// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
104
910
static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
105
910
  if (!isShiftedMask_64(I))
106
53
    return false;
107
857
108
857
  Size = countPopulation(I);
109
857
  Pos = countTrailingZeros(I);
110
857
  return true;
111
857
}
112
113
// The MIPS MSA ABI passes vector arguments in the integer register set.
114
// The number of integer registers used is dependant on the ABI used.
115
MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
116
                                                      CallingConv::ID CC,
117
60.7k
                                                      EVT VT) const {
118
60.7k
  if (VT.isVector()) {
119
2.15k
      if (Subtarget.isABI_O32()) {
120
1.09k
        return MVT::i32;
121
1.09k
      } else {
122
1.06k
        return (VT.getSizeInBits() == 32) ? 
MVT::i32104
:
MVT::i64962
;
123
1.06k
      }
124
58.5k
  }
125
58.5k
  return MipsTargetLowering::getRegisterType(Context, VT);
126
58.5k
}
127
128
unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
129
                                                           CallingConv::ID CC,
130
61.5k
                                                           EVT VT) const {
131
61.5k
  if (VT.isVector())
132
1.66k
    return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 
32806
:
64856
)),
133
1.66k
                    1U);
134
59.8k
  return MipsTargetLowering::getNumRegisters(Context, VT);
135
59.8k
}
136
137
unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
138
    LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
139
497
    unsigned &NumIntermediates, MVT &RegisterVT) const {
140
497
  // Break down vector types to either 2 i64s or 4 i32s.
141
497
  RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT);
142
497
  IntermediateVT = RegisterVT;
143
497
  NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
144
497
                         ? 
VT.getVectorNumElements()0
145
497
                         : VT.getSizeInBits() / RegisterVT.getSizeInBits();
146
497
147
497
  return NumIntermediates;
148
497
}
149
150
8.67k
SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
151
8.67k
  MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
152
8.67k
  return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
153
8.67k
}
154
155
SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
156
                                          SelectionDAG &DAG,
157
13.8k
                                          unsigned Flag) const {
158
13.8k
  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
159
13.8k
}
160
161
SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
162
                                          SelectionDAG &DAG,
163
664
                                          unsigned Flag) const {
164
664
  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
165
664
}
166
167
SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
168
                                          SelectionDAG &DAG,
169
36
                                          unsigned Flag) const {
170
36
  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
171
36
}
172
173
SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
174
                                          SelectionDAG &DAG,
175
54
                                          unsigned Flag) const {
176
54
  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
177
54
}
178
179
SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
180
                                          SelectionDAG &DAG,
181
1.15k
                                          unsigned Flag) const {
182
1.15k
  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
183
1.15k
                                   N->getOffset(), Flag);
184
1.15k
}
185
186
0
const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
187
0
  switch ((MipsISD::NodeType)Opcode) {
188
0
  case MipsISD::FIRST_NUMBER:      break;
189
0
  case MipsISD::JmpLink:           return "MipsISD::JmpLink";
190
0
  case MipsISD::TailCall:          return "MipsISD::TailCall";
191
0
  case MipsISD::Highest:           return "MipsISD::Highest";
192
0
  case MipsISD::Higher:            return "MipsISD::Higher";
193
0
  case MipsISD::Hi:                return "MipsISD::Hi";
194
0
  case MipsISD::Lo:                return "MipsISD::Lo";
195
0
  case MipsISD::GotHi:             return "MipsISD::GotHi";
196
0
  case MipsISD::TlsHi:             return "MipsISD::TlsHi";
197
0
  case MipsISD::GPRel:             return "MipsISD::GPRel";
198
0
  case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
199
0
  case MipsISD::Ret:               return "MipsISD::Ret";
200
0
  case MipsISD::ERet:              return "MipsISD::ERet";
201
0
  case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
202
0
  case MipsISD::FMS:               return "MipsISD::FMS";
203
0
  case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
204
0
  case MipsISD::FPCmp:             return "MipsISD::FPCmp";
205
0
  case MipsISD::FSELECT:           return "MipsISD::FSELECT";
206
0
  case MipsISD::MTC1_D64:          return "MipsISD::MTC1_D64";
207
0
  case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
208
0
  case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
209
0
  case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
210
0
  case MipsISD::MFHI:              return "MipsISD::MFHI";
211
0
  case MipsISD::MFLO:              return "MipsISD::MFLO";
212
0
  case MipsISD::MTLOHI:            return "MipsISD::MTLOHI";
213
0
  case MipsISD::Mult:              return "MipsISD::Mult";
214
0
  case MipsISD::Multu:             return "MipsISD::Multu";
215
0
  case MipsISD::MAdd:              return "MipsISD::MAdd";
216
0
  case MipsISD::MAddu:             return "MipsISD::MAddu";
217
0
  case MipsISD::MSub:              return "MipsISD::MSub";
218
0
  case MipsISD::MSubu:             return "MipsISD::MSubu";
219
0
  case MipsISD::DivRem:            return "MipsISD::DivRem";
220
0
  case MipsISD::DivRemU:           return "MipsISD::DivRemU";
221
0
  case MipsISD::DivRem16:          return "MipsISD::DivRem16";
222
0
  case MipsISD::DivRemU16:         return "MipsISD::DivRemU16";
223
0
  case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
224
0
  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
225
0
  case MipsISD::Wrapper:           return "MipsISD::Wrapper";
226
0
  case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
227
0
  case MipsISD::Sync:              return "MipsISD::Sync";
228
0
  case MipsISD::Ext:               return "MipsISD::Ext";
229
0
  case MipsISD::Ins:               return "MipsISD::Ins";
230
0
  case MipsISD::CIns:              return "MipsISD::CIns";
231
0
  case MipsISD::LWL:               return "MipsISD::LWL";
232
0
  case MipsISD::LWR:               return "MipsISD::LWR";
233
0
  case MipsISD::SWL:               return "MipsISD::SWL";
234
0
  case MipsISD::SWR:               return "MipsISD::SWR";
235
0
  case MipsISD::LDL:               return "MipsISD::LDL";
236
0
  case MipsISD::LDR:               return "MipsISD::LDR";
237
0
  case MipsISD::SDL:               return "MipsISD::SDL";
238
0
  case MipsISD::SDR:               return "MipsISD::SDR";
239
0
  case MipsISD::EXTP:              return "MipsISD::EXTP";
240
0
  case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
241
0
  case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
242
0
  case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
243
0
  case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
244
0
  case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
245
0
  case MipsISD::SHILO:             return "MipsISD::SHILO";
246
0
  case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
247
0
  case MipsISD::MULSAQ_S_W_PH:     return "MipsISD::MULSAQ_S_W_PH";
248
0
  case MipsISD::MAQ_S_W_PHL:       return "MipsISD::MAQ_S_W_PHL";
249
0
  case MipsISD::MAQ_S_W_PHR:       return "MipsISD::MAQ_S_W_PHR";
250
0
  case MipsISD::MAQ_SA_W_PHL:      return "MipsISD::MAQ_SA_W_PHL";
251
0
  case MipsISD::MAQ_SA_W_PHR:      return "MipsISD::MAQ_SA_W_PHR";
252
0
  case MipsISD::DPAU_H_QBL:        return "MipsISD::DPAU_H_QBL";
253
0
  case MipsISD::DPAU_H_QBR:        return "MipsISD::DPAU_H_QBR";
254
0
  case MipsISD::DPSU_H_QBL:        return "MipsISD::DPSU_H_QBL";
255
0
  case MipsISD::DPSU_H_QBR:        return "MipsISD::DPSU_H_QBR";
256
0
  case MipsISD::DPAQ_S_W_PH:       return "MipsISD::DPAQ_S_W_PH";
257
0
  case MipsISD::DPSQ_S_W_PH:       return "MipsISD::DPSQ_S_W_PH";
258
0
  case MipsISD::DPAQ_SA_L_W:       return "MipsISD::DPAQ_SA_L_W";
259
0
  case MipsISD::DPSQ_SA_L_W:       return "MipsISD::DPSQ_SA_L_W";
260
0
  case MipsISD::DPA_W_PH:          return "MipsISD::DPA_W_PH";
261
0
  case MipsISD::DPS_W_PH:          return "MipsISD::DPS_W_PH";
262
0
  case MipsISD::DPAQX_S_W_PH:      return "MipsISD::DPAQX_S_W_PH";
263
0
  case MipsISD::DPAQX_SA_W_PH:     return "MipsISD::DPAQX_SA_W_PH";
264
0
  case MipsISD::DPAX_W_PH:         return "MipsISD::DPAX_W_PH";
265
0
  case MipsISD::DPSX_W_PH:         return "MipsISD::DPSX_W_PH";
266
0
  case MipsISD::DPSQX_S_W_PH:      return "MipsISD::DPSQX_S_W_PH";
267
0
  case MipsISD::DPSQX_SA_W_PH:     return "MipsISD::DPSQX_SA_W_PH";
268
0
  case MipsISD::MULSA_W_PH:        return "MipsISD::MULSA_W_PH";
269
0
  case MipsISD::MULT:              return "MipsISD::MULT";
270
0
  case MipsISD::MULTU:             return "MipsISD::MULTU";
271
0
  case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSP";
272
0
  case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
273
0
  case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
274
0
  case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
275
0
  case MipsISD::SHLL_DSP:          return "MipsISD::SHLL_DSP";
276
0
  case MipsISD::SHRA_DSP:          return "MipsISD::SHRA_DSP";
277
0
  case MipsISD::SHRL_DSP:          return "MipsISD::SHRL_DSP";
278
0
  case MipsISD::SETCC_DSP:         return "MipsISD::SETCC_DSP";
279
0
  case MipsISD::SELECT_CC_DSP:     return "MipsISD::SELECT_CC_DSP";
280
0
  case MipsISD::VALL_ZERO:         return "MipsISD::VALL_ZERO";
281
0
  case MipsISD::VANY_ZERO:         return "MipsISD::VANY_ZERO";
282
0
  case MipsISD::VALL_NONZERO:      return "MipsISD::VALL_NONZERO";
283
0
  case MipsISD::VANY_NONZERO:      return "MipsISD::VANY_NONZERO";
284
0
  case MipsISD::VCEQ:              return "MipsISD::VCEQ";
285
0
  case MipsISD::VCLE_S:            return "MipsISD::VCLE_S";
286
0
  case MipsISD::VCLE_U:            return "MipsISD::VCLE_U";
287
0
  case MipsISD::VCLT_S:            return "MipsISD::VCLT_S";
288
0
  case MipsISD::VCLT_U:            return "MipsISD::VCLT_U";
289
0
  case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
290
0
  case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
291
0
  case MipsISD::VNOR:              return "MipsISD::VNOR";
292
0
  case MipsISD::VSHF:              return "MipsISD::VSHF";
293
0
  case MipsISD::SHF:               return "MipsISD::SHF";
294
0
  case MipsISD::ILVEV:             return "MipsISD::ILVEV";
295
0
  case MipsISD::ILVOD:             return "MipsISD::ILVOD";
296
0
  case MipsISD::ILVL:              return "MipsISD::ILVL";
297
0
  case MipsISD::ILVR:              return "MipsISD::ILVR";
298
0
  case MipsISD::PCKEV:             return "MipsISD::PCKEV";
299
0
  case MipsISD::PCKOD:             return "MipsISD::PCKOD";
300
0
  case MipsISD::INSVE:             return "MipsISD::INSVE";
301
0
  }
302
0
  return nullptr;
303
0
}
304
305
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
306
                                       const MipsSubtarget &STI)
307
11.3k
    : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
308
11.3k
  // Mips does not have i1 type, so use i32 for
309
11.3k
  // setcc operations results (slt, sgt, ...).
310
11.3k
  setBooleanContents(ZeroOrOneBooleanContent);
311
11.3k
  setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
312
11.3k
  // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
313
11.3k
  // does. Integer booleans still use 0 and 1.
314
11.3k
  if (Subtarget.hasMips32r6())
315
1.45k
    setBooleanContents(ZeroOrOneBooleanContent,
316
1.45k
                       ZeroOrNegativeOneBooleanContent);
317
11.3k
318
11.3k
  // Load extented operations for i1 types must be promoted
319
68.0k
  for (MVT VT : MVT::integer_valuetypes()) {
320
68.0k
    setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
321
68.0k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
322
68.0k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
323
68.0k
  }
324
11.3k
325
11.3k
  // MIPS doesn't have extending float->double load/store.  Set LoadExtAction
326
11.3k
  // for f32, f16
327
68.0k
  for (MVT VT : MVT::fp_valuetypes()) {
328
68.0k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
329
68.0k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
330
68.0k
  }
331
11.3k
332
11.3k
  // Set LoadExtAction for f16 vectors to Expand
333
374k
  for (MVT VT : MVT::fp_vector_valuetypes()) {
334
374k
    MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
335
374k
    if (F16VT.isValid())
336
204k
      setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
337
374k
  }
338
11.3k
339
11.3k
  setTruncStoreAction(MVT::f32, MVT::f16, Expand);
340
11.3k
  setTruncStoreAction(MVT::f64, MVT::f16, Expand);
341
11.3k
342
11.3k
  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
343
11.3k
344
11.3k
  // Used by legalize types to correctly generate the setcc result.
345
11.3k
  // Without this, every float setcc comes with a AND/OR with the result,
346
11.3k
  // we don't want this, since the fpcmp result goes to a flag register,
347
11.3k
  // which is used implicitly by brcond and select operations.
348
11.3k
  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
349
11.3k
350
11.3k
  // Mips Custom Operations
351
11.3k
  setOperationAction(ISD::BR_JT,              MVT::Other, Expand);
352
11.3k
  setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
353
11.3k
  setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
354
11.3k
  setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
355
11.3k
  setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
356
11.3k
  setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
357
11.3k
  setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
358
11.3k
  setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
359
11.3k
  setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
360
11.3k
  setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
361
11.3k
  setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
362
11.3k
  setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
363
11.3k
  setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
364
11.3k
  setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
365
11.3k
  setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
366
11.3k
367
11.3k
  if (!(TM.Options.NoNaNsFPMath || 
Subtarget.inAbs2008Mode()11.1k
)) {
368
9.69k
    setOperationAction(ISD::FABS, MVT::f32, Custom);
369
9.69k
    setOperationAction(ISD::FABS, MVT::f64, Custom);
370
9.69k
  }
371
11.3k
372
11.3k
  if (Subtarget.isGP64bit()) {
373
3.76k
    setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
374
3.76k
    setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
375
3.76k
    setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
376
3.76k
    setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
377
3.76k
    setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
378
3.76k
    setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
379
3.76k
    setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
380
3.76k
    setOperationAction(ISD::STORE,              MVT::i64,   Custom);
381
3.76k
    setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
382
3.76k
    setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);
383
3.76k
    setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);
384
3.76k
    setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);
385
3.76k
  }
386
11.3k
387
11.3k
  if (!Subtarget.isGP64bit()) {
388
7.58k
    setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
389
7.58k
    setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
390
7.58k
    setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
391
7.58k
  }
392
11.3k
393
11.3k
  setOperationAction(ISD::EH_DWARF_CFA,         MVT::i32,   Custom);
394
11.3k
  if (Subtarget.isGP64bit())
395
3.76k
    setOperationAction(ISD::EH_DWARF_CFA,       MVT::i64,   Custom);
396
11.3k
397
11.3k
  setOperationAction(ISD::SDIV, MVT::i32, Expand);
398
11.3k
  setOperationAction(ISD::SREM, MVT::i32, Expand);
399
11.3k
  setOperationAction(ISD::UDIV, MVT::i32, Expand);
400
11.3k
  setOperationAction(ISD::UREM, MVT::i32, Expand);
401
11.3k
  setOperationAction(ISD::SDIV, MVT::i64, Expand);
402
11.3k
  setOperationAction(ISD::SREM, MVT::i64, Expand);
403
11.3k
  setOperationAction(ISD::UDIV, MVT::i64, Expand);
404
11.3k
  setOperationAction(ISD::UREM, MVT::i64, Expand);
405
11.3k
406
11.3k
  // Operations not directly supported by Mips.
407
11.3k
  setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);
408
11.3k
  setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);
409
11.3k
  setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);
410
11.3k
  setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);
411
11.3k
  setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);
412
11.3k
  setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);
413
11.3k
  setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);
414
11.3k
  setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);
415
11.3k
  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
416
11.3k
  setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
417
11.3k
  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
418
11.3k
  setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
419
11.3k
  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
420
11.3k
  if (Subtarget.hasCnMips()) {
421
20
    setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);
422
20
    setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);
423
11.3k
  } else {
424
11.3k
    setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
425
11.3k
    setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
426
11.3k
  }
427
11.3k
  setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
428
11.3k
  setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
429
11.3k
  setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
430
11.3k
  setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
431
11.3k
  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
432
11.3k
  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
433
11.3k
434
11.3k
  if (!Subtarget.hasMips32r2())
435
5.87k
    setOperationAction(ISD::ROTR, MVT::i32,   Expand);
436
11.3k
437
11.3k
  if (!Subtarget.hasMips64r2())
438
9.53k
    setOperationAction(ISD::ROTR, MVT::i64,   Expand);
439
11.3k
440
11.3k
  setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
441
11.3k
  setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
442
11.3k
  setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
443
11.3k
  setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
444
11.3k
  setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
445
11.3k
  setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);
446
11.3k
  setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
447
11.3k
  setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
448
11.3k
  setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
449
11.3k
  setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
450
11.3k
  setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
451
11.3k
  setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
452
11.3k
  setOperationAction(ISD::FMA,               MVT::f32,   Expand);
453
11.3k
  setOperationAction(ISD::FMA,               MVT::f64,   Expand);
454
11.3k
  setOperationAction(ISD::FREM,              MVT::f32,   Expand);
455
11.3k
  setOperationAction(ISD::FREM,              MVT::f64,   Expand);
456
11.3k
457
11.3k
  // Lower f16 conversion operations into library calls
458
11.3k
  setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);
459
11.3k
  setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);
460
11.3k
  setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);
461
11.3k
  setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);
462
11.3k
463
11.3k
  setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
464
11.3k
465
11.3k
  setOperationAction(ISD::VASTART,           MVT::Other, Custom);
466
11.3k
  setOperationAction(ISD::VAARG,             MVT::Other, Custom);
467
11.3k
  setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
468
11.3k
  setOperationAction(ISD::VAEND,             MVT::Other, Expand);
469
11.3k
470
11.3k
  // Use the default for now
471
11.3k
  setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
472
11.3k
  setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
473
11.3k
474
11.3k
  if (!Subtarget.isGP64bit()) {
475
7.58k
    setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);
476
7.58k
    setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);
477
7.58k
  }
478
11.3k
479
11.3k
  if (!Subtarget.hasMips32r2()) {
480
5.87k
    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
481
5.87k
    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
482
5.87k
  }
483
11.3k
484
11.3k
  // MIPS16 lacks MIPS32's clz and clo instructions.
485
11.3k
  if (!Subtarget.hasMips32() || 
Subtarget.inMips16Mode()10.7k
)
486
3.40k
    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
487
11.3k
  if (!Subtarget.hasMips64())
488
8.08k
    setOperationAction(ISD::CTLZ, MVT::i64, Expand);
489
11.3k
490
11.3k
  if (!Subtarget.hasMips32r2())
491
5.87k
    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
492
11.3k
  if (!Subtarget.hasMips64r2())
493
9.53k
    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
494
11.3k
495
11.3k
  if (Subtarget.isGP64bit()) {
496
3.76k
    setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
497
3.76k
    setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
498
3.76k
    setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
499
3.76k
    setTruncStoreAction(MVT::i64, MVT::i32, Custom);
500
3.76k
  }
501
11.3k
502
11.3k
  setOperationAction(ISD::TRAP, MVT::Other, Legal);
503
11.3k
504
11.3k
  setTargetDAGCombine(ISD::SDIVREM);
505
11.3k
  setTargetDAGCombine(ISD::UDIVREM);
506
11.3k
  setTargetDAGCombine(ISD::SELECT);
507
11.3k
  setTargetDAGCombine(ISD::AND);
508
11.3k
  setTargetDAGCombine(ISD::OR);
509
11.3k
  setTargetDAGCombine(ISD::ADD);
510
11.3k
  setTargetDAGCombine(ISD::SUB);
511
11.3k
  setTargetDAGCombine(ISD::AssertZext);
512
11.3k
  setTargetDAGCombine(ISD::SHL);
513
11.3k
514
11.3k
  if (ABI.IsO32()) {
515
7.58k
    // These libcalls are not available in 32-bit.
516
7.58k
    setLibcallName(RTLIB::SHL_I128, nullptr);
517
7.58k
    setLibcallName(RTLIB::SRL_I128, nullptr);
518
7.58k
    setLibcallName(RTLIB::SRA_I128, nullptr);
519
7.58k
  }
520
11.3k
521
11.3k
  setMinFunctionAlignment(Subtarget.isGP64bit() ? 
33.76k
:
27.58k
);
522
11.3k
523
11.3k
  // The arguments on the stack are defined in terms of 4-byte slots on O32
524
11.3k
  // and 8-byte slots on N32/N64.
525
11.3k
  setMinStackArgumentAlignment((ABI.IsN32() || 
ABI.IsN64()10.8k
) ?
83.76k
:
47.58k
);
526
11.3k
527
11.3k
  setStackPointerRegisterToSaveRestore(ABI.IsN64() ? 
Mips::SP_643.24k
:
Mips::SP8.10k
);
528
11.3k
529
11.3k
  MaxStoresPerMemcpy = 16;
530
11.3k
531
11.3k
  isMicroMips = Subtarget.inMicroMipsMode();
532
11.3k
}
533
534
const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
535
11.3k
                                                     const MipsSubtarget &STI) {
536
11.3k
  if (STI.inMips16Mode())
537
2.91k
    return createMips16TargetLowering(TM, STI);
538
8.43k
539
8.43k
  return createMipsSETargetLowering(TM, STI);
540
8.43k
}
541
542
// Create a fast isel object.
543
FastISel *
544
MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
545
516
                                  const TargetLibraryInfo *libInfo) const {
546
516
  const MipsTargetMachine &TM =
547
516
      static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
548
516
549
516
  // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
550
516
  bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
551
516
                     
!Subtarget.hasMips32r6()513
&&
!Subtarget.inMips16Mode()437
&&
552
516
                     
!Subtarget.inMicroMipsMode()434
;
553
516
554
516
  // Disable if either of the following is true:
555
516
  // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
556
516
  if (!TM.isPositionIndependent() || 
!TM.getABI().IsO32()467
||
LargeGOT380
)
557
138
    UseFastISel = false;
558
516
559
516
  return UseFastISel ? 
Mips::createFastISel(funcInfo, libInfo)339
:
nullptr177
;
560
516
}
561
562
EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
563
8.74k
                                           EVT VT) const {
564
8.74k
  if (!VT.isVector())
565
8.20k
    return MVT::i32;
566
537
  return VT.changeVectorElementTypeToInteger();
567
537
}
568
569
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
570
                                    TargetLowering::DAGCombinerInfo &DCI,
571
34
                                    const MipsSubtarget &Subtarget) {
572
34
  if (DCI.isBeforeLegalizeOps())
573
28
    return SDValue();
574
6
575
6
  EVT Ty = N->getValueType(0);
576
6
  unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : 
Mips::LO0_640
;
577
6
  unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : 
Mips::HI0_640
;
578
6
  unsigned Opc = N->getOpcode() == ISD::SDIVREM ? 
MipsISD::DivRem163
:
579
6
                                                  
MipsISD::DivRemU163
;
580
6
  SDLoc DL(N);
581
6
582
6
  SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
583
6
                               N->getOperand(0), N->getOperand(1));
584
6
  SDValue InChain = DAG.getEntryNode();
585
6
  SDValue InGlue = DivRem;
586
6
587
6
  // insert MFLO
588
6
  if (N->hasAnyUseOfValue(0)) {
589
4
    SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
590
4
                                            InGlue);
591
4
    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
592
4
    InChain = CopyFromLo.getValue(1);
593
4
    InGlue = CopyFromLo.getValue(2);
594
4
  }
595
6
596
6
  // insert MFHI
597
6
  if (N->hasAnyUseOfValue(1)) {
598
4
    SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
599
4
                                            HI, Ty, InGlue);
600
4
    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
601
4
  }
602
6
603
6
  return SDValue();
604
6
}
605
606
450
static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
607
450
  switch (CC) {
608
450
  
default: 0
llvm_unreachable0
("Unknown fp condition code!");
609
450
  case ISD::SETEQ:
610
57
  case ISD::SETOEQ: return Mips::FCOND_OEQ;
611
57
  
case ISD::SETUNE: return Mips::FCOND_UNE21
;
612
62
  case ISD::SETLT:
613
62
  case ISD::SETOLT: return Mips::FCOND_OLT;
614
65
  case ISD::SETGT:
615
65
  case ISD::SETOGT: return Mips::FCOND_OGT;
616
65
  case ISD::SETLE:
617
48
  case ISD::SETOLE: return Mips::FCOND_OLE;
618
48
  case ISD::SETGE:
619
36
  case ISD::SETOGE: return Mips::FCOND_OGE;
620
36
  
case ISD::SETULT: return Mips::FCOND_ULT12
;
621
36
  
case ISD::SETULE: return Mips::FCOND_ULE18
;
622
36
  
case ISD::SETUGT: return Mips::FCOND_UGT20
;
623
36
  
case ISD::SETUGE: return Mips::FCOND_UGE22
;
624
36
  
case ISD::SETUO: return Mips::FCOND_UN12
;
625
36
  
case ISD::SETO: return Mips::FCOND_OR27
;
626
36
  case ISD::SETNE:
627
36
  case ISD::SETONE: return Mips::FCOND_ONE;
628
36
  
case ISD::SETUEQ: return Mips::FCOND_UEQ14
;
629
450
  }
630
450
}
631
632
/// This function returns true if the floating point conditional branches and
633
/// conditional moves which use condition code CC should be inverted.
634
450
static bool invertFPCondCodeUser(Mips::CondCode CC) {
635
450
  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
636
223
    return false;
637
227
638
227
  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
639
227
         "Illegal Condition Code");
640
227
641
227
  return true;
642
227
}
643
644
// Creates and returns an FPCmp node from a setcc node.
645
// Returns Op if setcc is not a floating point comparison.
646
3.23k
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
647
3.23k
  // must be a SETCC node
648
3.23k
  if (Op.getOpcode() != ISD::SETCC)
649
1.17k
    return Op;
650
2.06k
651
2.06k
  SDValue LHS = Op.getOperand(0);
652
2.06k
653
2.06k
  if (!LHS.getValueType().isFloatingPoint())
654
1.61k
    return Op;
655
450
656
450
  SDValue RHS = Op.getOperand(1);
657
450
  SDLoc DL(Op);
658
450
659
450
  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
660
450
  // node if necessary.
661
450
  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
662
450
663
450
  return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
664
450
                     DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
665
450
}
666
667
// Creates and returns a CMovFPT/F node.
668
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
669
386
                            SDValue False, const SDLoc &DL) {
670
386
  ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
671
386
  bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
672
386
  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
673
386
674
386
  return DAG.getNode((invert ? 
MipsISD::CMovFP_F186
:
MipsISD::CMovFP_T200
), DL,
675
386
                     True.getValueType(), True, FCC0, False, Cond);
676
386
}
677
678
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
679
                                    TargetLowering::DAGCombinerInfo &DCI,
680
3.18k
                                    const MipsSubtarget &Subtarget) {
681
3.18k
  if (DCI.isBeforeLegalizeOps())
682
1.85k
    return SDValue();
683
1.32k
684
1.32k
  SDValue SetCC = N->getOperand(0);
685
1.32k
686
1.32k
  if ((SetCC.getOpcode() != ISD::SETCC) ||
687
1.32k
      
!SetCC.getOperand(0).getValueType().isInteger()799
)
688
553
    return SDValue();
689
773
690
773
  SDValue False = N->getOperand(2);
691
773
  EVT FalseTy = False.getValueType();
692
773
693
773
  if (!FalseTy.isInteger())
694
12
    return SDValue();
695
761
696
761
  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
697
761
698
761
  // If the RHS (False) is 0, we swap the order of the operands
699
761
  // of ISD::SELECT (obviously also inverting the condition) so that we can
700
761
  // take advantage of conditional moves using the $0 register.
701
761
  // Example:
702
761
  //   return (a != 0) ? x : 0;
703
761
  //     load $reg, x
704
761
  //     movz $reg, $0, a
705
761
  if (!FalseC)
706
467
    return SDValue();
707
294
708
294
  const SDLoc DL(N);
709
294
710
294
  if (!FalseC->getZExtValue()) {
711
117
    ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
712
117
    SDValue True = N->getOperand(1);
713
117
714
117
    SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
715
117
                         SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
716
117
717
117
    return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
718
117
  }
719
177
720
177
  // If both operands are integer constants there's a possibility that we
721
177
  // can do some interesting optimizations.
722
177
  SDValue True = N->getOperand(1);
723
177
  ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
724
177
725
177
  if (!TrueC || !True.getValueType().isInteger())
726
0
    return SDValue();
727
177
728
177
  // We'll also ignore MVT::i64 operands as this optimizations proves
729
177
  // to be ineffective because of the required sign extensions as the result
730
177
  // of a SETCC operator is always MVT::i32 for non-vector types.
731
177
  if (True.getValueType() == MVT::i64)
732
14
    return SDValue();
733
163
734
163
  int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
735
163
736
163
  // 1)  (a < x) ? y : y-1
737
163
  //  slti $reg1, a, x
738
163
  //  addiu $reg2, $reg1, y-1
739
163
  if (Diff == 1)
740
43
    return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
741
120
742
120
  // 2)  (a < x) ? y-1 : y
743
120
  //  slti $reg1, a, x
744
120
  //  xor $reg1, $reg1, 1
745
120
  //  addiu $reg2, $reg1, y-1
746
120
  if (Diff == -1) {
747
8
    ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
748
8
    SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
749
8
                         SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
750
8
    return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
751
8
  }
752
112
753
112
  // Could not optimize.
754
112
  return SDValue();
755
112
}
756
757
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
758
                                    TargetLowering::DAGCombinerInfo &DCI,
759
565
                                    const MipsSubtarget &Subtarget) {
760
565
  if (DCI.isBeforeLegalizeOps())
761
0
    return SDValue();
762
565
763
565
  SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
764
565
765
565
  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
766
565
  if (!FalseC || 
FalseC->getZExtValue()355
)
767
389
    return SDValue();
768
176
769
176
  // Since RHS (False) is 0, we swap the order of the True/False operands
770
176
  // (obviously also inverting the condition) so that we can
771
176
  // take advantage of conditional moves using the $0 register.
772
176
  // Example:
773
176
  //   return (a != 0) ? x : 0;
774
176
  //     load $reg, x
775
176
  //     movz $reg, $0, a
776
176
  unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? 
MipsISD::CMovFP_F86
:
777
176
                                                         
MipsISD::CMovFP_T90
;
778
176
779
176
  SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
780
176
  return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
781
176
                     ValueIfFalse, FCC, ValueIfTrue, Glue);
782
176
}
783
784
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
785
                                 TargetLowering::DAGCombinerInfo &DCI,
786
3.97k
                                 const MipsSubtarget &Subtarget) {
787
3.97k
  if (DCI.isBeforeLegalizeOps() || 
!Subtarget.hasExtractInsert()1.98k
)
788
2.81k
    return SDValue();
789
1.16k
790
1.16k
  SDValue FirstOperand = N->getOperand(0);
791
1.16k
  unsigned FirstOperandOpc = FirstOperand.getOpcode();
792
1.16k
  SDValue Mask = N->getOperand(1);
793
1.16k
  EVT ValTy = N->getValueType(0);
794
1.16k
  SDLoc DL(N);
795
1.16k
796
1.16k
  uint64_t Pos = 0, SMPos, SMSize;
797
1.16k
  ConstantSDNode *CN;
798
1.16k
  SDValue NewOperand;
799
1.16k
  unsigned Opc;
800
1.16k
801
1.16k
  // Op's second operand must be a shifted mask.
802
1.16k
  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
803
1.16k
      
!isShiftedMask(CN->getZExtValue(), SMPos, SMSize)881
)
804
338
    return SDValue();
805
828
806
828
  if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
807
28
    // Pattern match EXT.
808
28
    //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
809
28
    //  => ext $dst, $src, pos, size
810
28
811
28
    // The second operand of the shift must be an immediate.
812
28
    if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
813
20
      return SDValue();
814
8
815
8
    Pos = CN->getZExtValue();
816
8
817
8
    // Return if the shifted mask does not start at bit 0 or the sum of its size
818
8
    // and Pos exceeds the word's size.
819
8
    if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
820
0
      return SDValue();
821
8
822
8
    Opc = MipsISD::Ext;
823
8
    NewOperand = FirstOperand.getOperand(0);
824
800
  } else if (FirstOperandOpc == ISD::SHL && 
Subtarget.hasCnMips()5
) {
825
5
    // Pattern match CINS.
826
5
    //  $dst = and (shl $src , pos), mask
827
5
    //  => cins $dst, $src, pos, size
828
5
    // mask is a shifted mask with consecutive 1's, pos = shift amount,
829
5
    // size = population count.
830
5
831
5
    // The second operand of the shift must be an immediate.
832
5
    if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
833
0
      return SDValue();
834
5
835
5
    Pos = CN->getZExtValue();
836
5
837
5
    if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
838
5
        Pos + SMSize > ValTy.getSizeInBits())
839
0
      return SDValue();
840
5
841
5
    NewOperand = FirstOperand.getOperand(0);
842
5
    // SMSize is 'location' (position) in this case, not size.
843
5
    SMSize--;
844
5
    Opc = MipsISD::CIns;
845
795
  } else {
846
795
    // Pattern match EXT.
847
795
    //  $dst = and $src, (2**size - 1) , if size > 16
848
795
    //  => ext $dst, $src, pos, size , pos = 0
849
795
850
795
    // If the mask is <= 0xffff, andi can be used instead.
851
795
    if (CN->getZExtValue() <= 0xffff)
852
700
      return SDValue();
853
95
854
95
    // Return if the mask doesn't start at position 0.
855
95
    if (SMPos)
856
71
      return SDValue();
857
24
858
24
    Opc = MipsISD::Ext;
859
24
    NewOperand = FirstOperand;
860
24
  }
861
828
  return DAG.getNode(Opc, DL, ValTy, NewOperand,
862
37
                     DAG.getConstant(Pos, DL, MVT::i32),
863
37
                     DAG.getConstant(SMSize, DL, MVT::i32));
864
828
}
865
866
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
867
                                TargetLowering::DAGCombinerInfo &DCI,
868
4.33k
                                const MipsSubtarget &Subtarget) {
869
4.33k
  // Pattern match INS.
870
4.33k
  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
871
4.33k
  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
872
4.33k
  //  => ins $dst, $src, size, pos, $src1
873
4.33k
  if (DCI.isBeforeLegalizeOps() || 
!Subtarget.hasExtractInsert()2.55k
)
874
2.68k
    return SDValue();
875
1.65k
876
1.65k
  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
877
1.65k
  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
878
1.65k
  ConstantSDNode *CN, *CN1;
879
1.65k
880
1.65k
  // See if Op's first operand matches (and $src1 , mask0).
881
1.65k
  if (And0.getOpcode() != ISD::AND)
882
1.63k
    return SDValue();
883
22
884
22
  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
885
22
      !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
886
0
    return SDValue();
887
22
888
22
  // See if Op's second operand matches (and (shl $src, pos), mask1).
889
22
  if (And1.getOpcode() == ISD::AND &&
890
22
      
And1.getOperand(0).getOpcode() == ISD::SHL10
) {
891
5
892
5
    if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
893
5
        !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
894
0
      return SDValue();
895
5
896
5
    // The shift masks must have the same position and size.
897
5
    if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
898
0
      return SDValue();
899
5
900
5
    SDValue Shl = And1.getOperand(0);
901
5
902
5
    if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
903
0
      return SDValue();
904
5
905
5
    unsigned Shamt = CN->getZExtValue();
906
5
907
5
    // Return if the shift amount and the first bit position of mask are not the
908
5
    // same.
909
5
    EVT ValTy = N->getValueType(0);
910
5
    if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
911
0
      return SDValue();
912
5
913
5
    SDLoc DL(N);
914
5
    return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
915
5
                       DAG.getConstant(SMPos0, DL, MVT::i32),
916
5
                       DAG.getConstant(SMSize0, DL, MVT::i32),
917
5
                       And0.getOperand(0));
918
17
  } else {
919
17
    // Pattern match DINS.
920
17
    //  $dst = or (and $src, mask0), mask1
921
17
    //  where mask0 = ((1 << SMSize0) -1) << SMPos0
922
17
    //  => dins $dst, $src, pos, size
923
17
    if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
924
17
        ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
925
17
         
(SMSize0 + SMPos0 <= 32)5
)) {
926
14
      // Check if AND instruction has constant as argument
927
14
      bool isConstCase = And1.getOpcode() != ISD::AND;
928
14
      if (And1.getOpcode() == ISD::AND) {
929
5
        if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
930
0
          return SDValue();
931
9
      } else {
932
9
        if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
933
0
          return SDValue();
934
14
      }
935
14
      // Don't generate INS if constant OR operand doesn't fit into bits
936
14
      // cleared by constant AND operand.
937
14
      if (CN->getSExtValue() & CN1->getSExtValue())
938
3
        return SDValue();
939
11
940
11
      SDLoc DL(N);
941
11
      EVT ValTy = N->getOperand(0)->getValueType(0);
942
11
      SDValue Const1;
943
11
      SDValue SrlX;
944
11
      if (!isConstCase) {
945
5
        Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
946
5
        SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
947
5
      }
948
11
      return DAG.getNode(
949
11
          MipsISD::Ins, DL, N->getValueType(0),
950
11
          isConstCase
951
11
              ? 
DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)6
952
11
              : 
SrlX5
,
953
11
          DAG.getConstant(SMPos0, DL, MVT::i32),
954
11
          DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? 
SMSize0 & 311
955
11
                                                        : 
SMSize010
,
956
11
                          DL, MVT::i32),
957
11
          And0->getOperand(0));
958
11
959
11
    }
960
3
    return SDValue();
961
3
  }
962
22
}
963
964
static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
965
867
                                       const MipsSubtarget &Subtarget) {
966
867
  // ROOTNode must have a multiplication as an operand for the match to be
967
867
  // successful.
968
867
  if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
969
867
      
ROOTNode->getOperand(1).getOpcode() != ISD::MUL840
)
970
813
    return SDValue();
971
54
972
54
  // We don't handle vector types here.
973
54
  if (ROOTNode->getValueType(0).isVector())
974
0
    return SDValue();
975
54
976
54
  // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
977
54
  // arithmetic. E.g.
978
54
  // (add (mul a b) c) =>
979
54
  //   let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
980
54
  //   MIPS64:   (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
981
54
  //   or
982
54
  //   MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
983
54
  //
984
54
  // The overhead of setting up the Hi/Lo registers and reassembling the
985
54
  // result makes this a dubious optimzation for MIPS64. The core of the
986
54
  // problem is that Hi/Lo contain the upper and lower 32 bits of the
987
54
  // operand and result.
988
54
  //
989
54
  // It requires a chain of 4 add/mul for MIPS64R2 to get better code
990
54
  // density than doing it naively, 5 for MIPS64. Additionally, using
991
54
  // madd/msub on MIPS64 requires the operands actually be 32 bit sign
992
54
  // extended operands, not true 64 bit values.
993
54
  //
994
54
  // FIXME: For the moment, disable this completely for MIPS64.
995
54
  if (Subtarget.hasMips64())
996
34
    return SDValue();
997
20
998
20
  SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
999
20
                     ? 
ROOTNode->getOperand(0)11
1000
20
                     : 
ROOTNode->getOperand(1)9
;
1001
20
1002
20
  SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1003
20
                     ? 
ROOTNode->getOperand(1)11
1004
20
                     : 
ROOTNode->getOperand(0)9
;
1005
20
1006
20
  // Transform this to a MADD only if the user of this node is the add.
1007
20
  // If there are other users of the mul, this function returns here.
1008
20
  if (!Mult.hasOneUse())
1009
0
    return SDValue();
1010
20
1011
20
  // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1012
20
  // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1013
20
  // of the multiply must have 32 or more sign bits, otherwise we cannot
1014
20
  // perform this optimization. We have to check this here as we're performing
1015
20
  // this optimization pre-legalization.
1016
20
  SDValue MultLHS = Mult->getOperand(0);
1017
20
  SDValue MultRHS = Mult->getOperand(1);
1018
20
1019
20
  bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1020
20
                  
MultRHS->getOpcode() == ISD::SIGN_EXTEND14
;
1021
20
  bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1022
20
                    
MultRHS->getOpcode() == ISD::ZERO_EXTEND6
;
1023
20
1024
20
  if (!IsSigned && 
!IsUnsigned6
)
1025
0
    return SDValue();
1026
20
1027
20
  // Initialize accumulator.
1028
20
  SDLoc DL(ROOTNode);
1029
20
  SDValue TopHalf;
1030
20
  SDValue BottomHalf;
1031
20
  BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1032
20
                              CurDAG.getIntPtrConstant(0, DL));
1033
20
1034
20
  TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1035
20
                           CurDAG.getIntPtrConstant(1, DL));
1036
20
  SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1037
20
                                  BottomHalf,
1038
20
                                  TopHalf);
1039
20
1040
20
  // Create MipsMAdd(u) / MipsMSub(u) node.
1041
20
  bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1042
20
  unsigned Opcode = IsAdd ? 
(IsUnsigned 11
?
MipsISD::MAddu3
:
MipsISD::MAdd8
)
1043
20
                          : 
(IsUnsigned 9
?
MipsISD::MSubu3
:
MipsISD::MSub6
);
1044
20
  SDValue MAddOps[3] = {
1045
20
      CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1046
20
      CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1047
20
  EVT VTs[2] = {MVT::i32, MVT::i32};
1048
20
  SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1049
20
1050
20
  SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1051
20
  SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1052
20
  SDValue Combined =
1053
20
      CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1054
20
  return Combined;
1055
20
}
1056
1057
static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1058
                                 TargetLowering::DAGCombinerInfo &DCI,
1059
1.03k
                                 const MipsSubtarget &Subtarget) {
1060
1.03k
  // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1061
1.03k
  if (DCI.isBeforeLegalizeOps()) {
1062
506
    if (Subtarget.hasMips32() && 
!Subtarget.hasMips32r6()441
&&
1063
506
        
!Subtarget.inMips16Mode()350
&&
N->getValueType(0) == MVT::i64330
)
1064
54
      return performMADD_MSUBCombine(N, DAG, Subtarget);
1065
452
1066
452
    return SDValue();
1067
452
  }
1068
533
1069
533
  return SDValue();
1070
533
}
1071
1072
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1073
                                 TargetLowering::DAGCombinerInfo &DCI,
1074
19.4k
                                 const MipsSubtarget &Subtarget) {
1075
19.4k
  // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1076
19.4k
  if (DCI.isBeforeLegalizeOps()) {
1077
7.46k
    if (Subtarget.hasMips32() && 
!Subtarget.hasMips32r6()7.09k
&&
1078
7.46k
        
!Subtarget.inMips16Mode()5.87k
&&
N->getValueType(0) == MVT::i644.92k
)
1079
813
      return performMADD_MSUBCombine(N, DAG, Subtarget);
1080
6.65k
1081
6.65k
    return SDValue();
1082
6.65k
  }
1083
12.0k
1084
12.0k
  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1085
12.0k
  SDValue Add = N->getOperand(1);
1086
12.0k
1087
12.0k
  if (Add.getOpcode() != ISD::ADD)
1088
11.9k
    return SDValue();
1089
68
1090
68
  SDValue Lo = Add.getOperand(1);
1091
68
1092
68
  if ((Lo.getOpcode() != MipsISD::Lo) ||
1093
68
      
(Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)37
)
1094
46
    return SDValue();
1095
22
1096
22
  EVT ValTy = N->getValueType(0);
1097
22
  SDLoc DL(N);
1098
22
1099
22
  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1100
22
                             Add.getOperand(0));
1101
22
  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1102
22
}
1103
1104
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1105
                                 TargetLowering::DAGCombinerInfo &DCI,
1106
2.94k
                                 const MipsSubtarget &Subtarget) {
1107
2.94k
  // Pattern match CINS.
1108
2.94k
  //  $dst = shl (and $src , imm), pos
1109
2.94k
  //  => cins $dst, $src, pos, size
1110
2.94k
1111
2.94k
  if (DCI.isBeforeLegalizeOps() || 
!Subtarget.hasCnMips()1.99k
)
1112
2.93k
    return SDValue();
1113
7
1114
7
  SDValue FirstOperand = N->getOperand(0);
1115
7
  unsigned FirstOperandOpc = FirstOperand.getOpcode();
1116
7
  SDValue SecondOperand = N->getOperand(1);
1117
7
  EVT ValTy = N->getValueType(0);
1118
7
  SDLoc DL(N);
1119
7
1120
7
  uint64_t Pos = 0, SMPos, SMSize;
1121
7
  ConstantSDNode *CN;
1122
7
  SDValue NewOperand;
1123
7
1124
7
  // The second operand of the shift must be an immediate.
1125
7
  if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1126
0
    return SDValue();
1127
7
1128
7
  Pos = CN->getZExtValue();
1129
7
1130
7
  if (Pos >= ValTy.getSizeInBits())
1131
0
    return SDValue();
1132
7
1133
7
  if (FirstOperandOpc != ISD::AND)
1134
5
    return SDValue();
1135
2
1136
2
  // AND's second operand must be a shifted mask.
1137
2
  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1138
2
      !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1139
0
    return SDValue();
1140
2
1141
2
  // Return if the shifted mask does not start at bit 0 or the sum of its size
1142
2
  // and Pos exceeds the word's size.
1143
2
  if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1144
0
    return SDValue();
1145
2
1146
2
  NewOperand = FirstOperand.getOperand(0);
1147
2
  // SMSize is 'location' (position) in this case, not size.
1148
2
  SMSize--;
1149
2
1150
2
  return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1151
2
                     DAG.getConstant(Pos, DL, MVT::i32),
1152
2
                     DAG.getConstant(SMSize, DL, MVT::i32));
1153
2
}
1154
1155
SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1156
96.0k
  const {
1157
96.0k
  SelectionDAG &DAG = DCI.DAG;
1158
96.0k
  unsigned Opc = N->getOpcode();
1159
96.0k
1160
96.0k
  switch (Opc) {
1161
96.0k
  
default: break60.4k
;
1162
96.0k
  case ISD::SDIVREM:
1163
34
  case ISD::UDIVREM:
1164
34
    return performDivRemCombine(N, DAG, DCI, Subtarget);
1165
3.18k
  case ISD::SELECT:
1166
3.18k
    return performSELECTCombine(N, DAG, DCI, Subtarget);
1167
565
  case MipsISD::CMovFP_F:
1168
565
  case MipsISD::CMovFP_T:
1169
565
    return performCMovFPCombine(N, DAG, DCI, Subtarget);
1170
3.97k
  case ISD::AND:
1171
3.97k
    return performANDCombine(N, DAG, DCI, Subtarget);
1172
4.33k
  case ISD::OR:
1173
4.33k
    return performORCombine(N, DAG, DCI, Subtarget);
1174
19.4k
  case ISD::ADD:
1175
19.4k
    return performADDCombine(N, DAG, DCI, Subtarget);
1176
2.94k
  case ISD::SHL:
1177
2.94k
    return performSHLCombine(N, DAG, DCI, Subtarget);
1178
1.03k
  case ISD::SUB:
1179
1.03k
    return performSUBCombine(N, DAG, DCI, Subtarget);
1180
60.4k
  }
1181
60.4k
1182
60.4k
  return SDValue();
1183
60.4k
}
1184
1185
1
bool MipsTargetLowering::isCheapToSpeculateCttz() const {
1186
1
  return Subtarget.hasMips32();
1187
1
}
1188
1189
9
bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
1190
9
  return Subtarget.hasMips32();
1191
9
}
1192
1193
bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
1194
24
    const SDNode *N, CombineLevel Level) const {
1195
24
  if (N->getOperand(0).getValueType().isVector())
1196
11
    return false;
1197
13
  return true;
1198
13
}
1199
1200
void
1201
MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1202
                                          SmallVectorImpl<SDValue> &Results,
1203
67
                                          SelectionDAG &DAG) const {
1204
67
  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1205
67
1206
67
  if (Res)
1207
160
    
for (unsigned I = 0, E = Res->getNumValues(); 67
I != E;
++I93
)
1208
93
      Results.push_back(Res.getValue(I));
1209
67
}
1210
1211
void
1212
MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1213
                                       SmallVectorImpl<SDValue> &Results,
1214
46
                                       SelectionDAG &DAG) const {
1215
46
  return LowerOperationWrapper(N, Results, DAG);
1216
46
}
1217
1218
SDValue MipsTargetLowering::
1219
LowerOperation(SDValue Op, SelectionDAG &DAG) const
1220
12.9k
{
1221
12.9k
  switch (Op.getOpcode())
1222
12.9k
  {
1223
12.9k
  
case ISD::BRCOND: return lowerBRCOND(Op, DAG)1.11k
;
1224
12.9k
  
case ISD::ConstantPool: return lowerConstantPool(Op, DAG)542
;
1225
12.9k
  
case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG)8.42k
;
1226
12.9k
  
case ISD::BlockAddress: return lowerBlockAddress(Op, DAG)16
;
1227
12.9k
  
case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG)54
;
1228
12.9k
  
case ISD::JumpTable: return lowerJumpTable(Op, DAG)22
;
1229
12.9k
  
case ISD::SELECT: return lowerSELECT(Op, DAG)1.95k
;
1230
12.9k
  
case ISD::SETCC: return lowerSETCC(Op, DAG)176
;
1231
12.9k
  
case ISD::VASTART: return lowerVASTART(Op, DAG)76
;
1232
12.9k
  
case ISD::VAARG: return lowerVAARG(Op, DAG)142
;
1233
12.9k
  
case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG)27
;
1234
12.9k
  
case ISD::FABS: return lowerFABS(Op, DAG)28
;
1235
12.9k
  
case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG)5
;
1236
12.9k
  
case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG)3
;
1237
12.9k
  
case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG)14
;
1238
12.9k
  
case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG)131
;
1239
12.9k
  
case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG)56
;
1240
12.9k
  
case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true)32
;
1241
12.9k
  
case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false)56
;
1242
12.9k
  
case ISD::LOAD: return lowerLOAD(Op, DAG)0
;
1243
12.9k
  
case ISD::STORE: return lowerSTORE(Op, DAG)0
;
1244
12.9k
  
case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG)12
;
1245
12.9k
  
case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG)46
;
1246
0
  }
1247
0
  return SDValue();
1248
0
}
1249
1250
//===----------------------------------------------------------------------===//
1251
//  Lower helper functions
1252
//===----------------------------------------------------------------------===//
1253
1254
// addLiveIn - This helper function adds the specified physical register to the
1255
// MachineFunction as a live in value.  It also creates a corresponding
1256
// virtual register for it.
1257
static unsigned
1258
addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1259
18.3k
{
1260
18.3k
  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1261
18.3k
  MF.getRegInfo().addLiveIn(PReg, VReg);
1262
18.3k
  return VReg;
1263
18.3k
}
1264
1265
static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1266
                                              MachineBasicBlock &MBB,
1267
                                              const TargetInstrInfo &TII,
1268
399
                                              bool Is64Bit, bool IsMicroMips) {
1269
399
  if (NoZeroDivCheck)
1270
66
    return &MBB;
1271
333
1272
333
  // Insert instruction "teq $divisor_reg, $zero, 7".
1273
333
  MachineBasicBlock::iterator I(MI);
1274
333
  MachineInstrBuilder MIB;
1275
333
  MachineOperand &Divisor = MI.getOperand(2);
1276
333
  MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1277
333
                TII.get(IsMicroMips ? 
Mips::TEQ_MM24
:
Mips::TEQ309
))
1278
333
            .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1279
333
            .addReg(Mips::ZERO)
1280
333
            .addImm(7);
1281
333
1282
333
  // Use the 32-bit sub-register if this is a 64-bit division.
1283
333
  if (Is64Bit)
1284
80
    MIB->getOperand(0).setSubReg(Mips::sub_32);
1285
333
1286
333
  // Clear Divisor's kill flag.
1287
333
  Divisor.setIsKill(false);
1288
333
1289
333
  // We would normally delete the original instruction here but in this case
1290
333
  // we only needed to inject an additional instruction rather than replace it.
1291
333
1292
333
  return &MBB;
1293
333
}
1294
1295
MachineBasicBlock *
1296
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1297
858
                                                MachineBasicBlock *BB) const {
1298
858
  switch (MI.getOpcode()) {
1299
858
  default:
1300
0
    llvm_unreachable("Unexpected instr type to insert");
1301
858
  case Mips::ATOMIC_LOAD_ADD_I8:
1302
16
    return emitAtomicBinaryPartword(MI, BB, 1);
1303
858
  case Mips::ATOMIC_LOAD_ADD_I16:
1304
15
    return emitAtomicBinaryPartword(MI, BB, 2);
1305
858
  case Mips::ATOMIC_LOAD_ADD_I32:
1306
48
    return emitAtomicBinary(MI, BB);
1307
858
  case Mips::ATOMIC_LOAD_ADD_I64:
1308
10
    return emitAtomicBinary(MI, BB);
1309
858
1310
858
  case Mips::ATOMIC_LOAD_AND_I8:
1311
0
    return emitAtomicBinaryPartword(MI, BB, 1);
1312
858
  case Mips::ATOMIC_LOAD_AND_I16:
1313
0
    return emitAtomicBinaryPartword(MI, BB, 2);
1314
858
  case Mips::ATOMIC_LOAD_AND_I32:
1315
15
    return emitAtomicBinary(MI, BB);
1316
858
  case Mips::ATOMIC_LOAD_AND_I64:
1317
9
    return emitAtomicBinary(MI, BB);
1318
858
1319
858
  case Mips::ATOMIC_LOAD_OR_I8:
1320
0
    return emitAtomicBinaryPartword(MI, BB, 1);
1321
858
  case Mips::ATOMIC_LOAD_OR_I16:
1322
0
    return emitAtomicBinaryPartword(MI, BB, 2);
1323
858
  case Mips::ATOMIC_LOAD_OR_I32:
1324
15
    return emitAtomicBinary(MI, BB);
1325
858
  case Mips::ATOMIC_LOAD_OR_I64:
1326
9
    return emitAtomicBinary(MI, BB);
1327
858
1328
858
  case Mips::ATOMIC_LOAD_XOR_I8:
1329
0
    return emitAtomicBinaryPartword(MI, BB, 1);
1330
858
  case Mips::ATOMIC_LOAD_XOR_I16:
1331
0
    return emitAtomicBinaryPartword(MI, BB, 2);
1332
858
  case Mips::ATOMIC_LOAD_XOR_I32:
1333
15
    return emitAtomicBinary(MI, BB);
1334
858
  case Mips::ATOMIC_LOAD_XOR_I64:
1335
9
    return emitAtomicBinary(MI, BB);
1336
858
1337
858
  case Mips::ATOMIC_LOAD_NAND_I8:
1338
15
    return emitAtomicBinaryPartword(MI, BB, 1);
1339
858
  case Mips::ATOMIC_LOAD_NAND_I16:
1340
0
    return emitAtomicBinaryPartword(MI, BB, 2);
1341
858
  case Mips::ATOMIC_LOAD_NAND_I32:
1342
15
    return emitAtomicBinary(MI, BB);
1343
858
  case Mips::ATOMIC_LOAD_NAND_I64:
1344
9
    return emitAtomicBinary(MI, BB);
1345
858
1346
858
  case Mips::ATOMIC_LOAD_SUB_I8:
1347
15
    return emitAtomicBinaryPartword(MI, BB, 1);
1348
858
  case Mips::ATOMIC_LOAD_SUB_I16:
1349
0
    return emitAtomicBinaryPartword(MI, BB, 2);
1350
858
  case Mips::ATOMIC_LOAD_SUB_I32:
1351
15
    return emitAtomicBinary(MI, BB);
1352
858
  case Mips::ATOMIC_LOAD_SUB_I64:
1353
9
    return emitAtomicBinary(MI, BB);
1354
858
1355
858
  case Mips::ATOMIC_SWAP_I8:
1356
15
    return emitAtomicBinaryPartword(MI, BB, 1);
1357
858
  case Mips::ATOMIC_SWAP_I16:
1358
0
    return emitAtomicBinaryPartword(MI, BB, 2);
1359
858
  case Mips::ATOMIC_SWAP_I32:
1360
15
    return emitAtomicBinary(MI, BB);
1361
858
  case Mips::ATOMIC_SWAP_I64:
1362
9
    return emitAtomicBinary(MI, BB);
1363
858
1364
858
  case Mips::ATOMIC_CMP_SWAP_I8:
1365
31
    return emitAtomicCmpSwapPartword(MI, BB, 1);
1366
858
  case Mips::ATOMIC_CMP_SWAP_I16:
1367
15
    return emitAtomicCmpSwapPartword(MI, BB, 2);
1368
858
  case Mips::ATOMIC_CMP_SWAP_I32:
1369
33
    return emitAtomicCmpSwap(MI, BB);
1370
858
  case Mips::ATOMIC_CMP_SWAP_I64:
1371
9
    return emitAtomicCmpSwap(MI, BB);
1372
858
  case Mips::PseudoSDIV:
1373
275
  case Mips::PseudoUDIV:
1374
275
  case Mips::DIV:
1375
275
  case Mips::DIVU:
1376
275
  case Mips::MOD:
1377
275
  case Mips::MODU:
1378
275
    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1379
275
                               false);
1380
275
  case Mips::SDIV_MM_Pseudo:
1381
24
  case Mips::UDIV_MM_Pseudo:
1382
24
  case Mips::SDIV_MM:
1383
24
  case Mips::UDIV_MM:
1384
24
  case Mips::DIV_MMR6:
1385
24
  case Mips::DIVU_MMR6:
1386
24
  case Mips::MOD_MMR6:
1387
24
  case Mips::MODU_MMR6:
1388
24
    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1389
100
  case Mips::PseudoDSDIV:
1390
100
  case Mips::PseudoDUDIV:
1391
100
  case Mips::DDIV:
1392
100
  case Mips::DDIVU:
1393
100
  case Mips::DMOD:
1394
100
  case Mips::DMODU:
1395
100
    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1396
100
1397
100
  case Mips::PseudoSELECT_I:
1398
58
  case Mips::PseudoSELECT_I64:
1399
58
  case Mips::PseudoSELECT_S:
1400
58
  case Mips::PseudoSELECT_D32:
1401
58
  case Mips::PseudoSELECT_D64:
1402
58
    return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1403
58
  case Mips::PseudoSELECTFP_F_I:
1404
12
  case Mips::PseudoSELECTFP_F_I64:
1405
12
  case Mips::PseudoSELECTFP_F_S:
1406
12
  case Mips::PseudoSELECTFP_F_D32:
1407
12
  case Mips::PseudoSELECTFP_F_D64:
1408
12
    return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1409
12
  case Mips::PseudoSELECTFP_T_I:
1410
12
  case Mips::PseudoSELECTFP_T_I64:
1411
12
  case Mips::PseudoSELECTFP_T_S:
1412
12
  case Mips::PseudoSELECTFP_T_D32:
1413
12
  case Mips::PseudoSELECTFP_T_D64:
1414
12
    return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1415
12
  case Mips::PseudoD_SELECT_I:
1416
11
  case Mips::PseudoD_SELECT_I64:
1417
11
    return emitPseudoD_SELECT(MI, BB);
1418
858
  }
1419
858
}
1420
1421
// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1422
// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1423
MachineBasicBlock *
1424
MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1425
202
                                     MachineBasicBlock *BB) const {
1426
202
1427
202
  MachineFunction *MF = BB->getParent();
1428
202
  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1429
202
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1430
202
  DebugLoc DL = MI.getDebugLoc();
1431
202
1432
202
  unsigned AtomicOp;
1433
202
  switch (MI.getOpcode()) {
1434
202
  case Mips::ATOMIC_LOAD_ADD_I32:
1435
48
    AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1436
48
    break;
1437
202
  case Mips::ATOMIC_LOAD_SUB_I32:
1438
15
    AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1439
15
    break;
1440
202
  case Mips::ATOMIC_LOAD_AND_I32:
1441
15
    AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1442
15
    break;
1443
202
  case Mips::ATOMIC_LOAD_OR_I32:
1444
15
    AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1445
15
    break;
1446
202
  case Mips::ATOMIC_LOAD_XOR_I32:
1447
15
    AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1448
15
    break;
1449
202
  case Mips::ATOMIC_LOAD_NAND_I32:
1450
15
    AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1451
15
    break;
1452
202
  case Mips::ATOMIC_SWAP_I32:
1453
15
    AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1454
15
    break;
1455
202
  case Mips::ATOMIC_LOAD_ADD_I64:
1456
10
    AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1457
10
    break;
1458
202
  case Mips::ATOMIC_LOAD_SUB_I64:
1459
9
    AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1460
9
    break;
1461
202
  case Mips::ATOMIC_LOAD_AND_I64:
1462
9
    AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1463
9
    break;
1464
202
  case Mips::ATOMIC_LOAD_OR_I64:
1465
9
    AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1466
9
    break;
1467
202
  case Mips::ATOMIC_LOAD_XOR_I64:
1468
9
    AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1469
9
    break;
1470
202
  case Mips::ATOMIC_LOAD_NAND_I64:
1471
9
    AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1472
9
    break;
1473
202
  case Mips::ATOMIC_SWAP_I64:
1474
9
    AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1475
9
    break;
1476
202
  default:
1477
0
    llvm_unreachable("Unknown pseudo atomic for replacement!");
1478
202
  }
1479
202
1480
202
  unsigned OldVal = MI.getOperand(0).getReg();
1481
202
  unsigned Ptr = MI.getOperand(1).getReg();
1482
202
  unsigned Incr = MI.getOperand(2).getReg();
1483
202
  unsigned Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1484
202
1485
202
  MachineBasicBlock::iterator II(MI);
1486
202
1487
202
  // The scratch registers here with the EarlyClobber | Define | Implicit
1488
202
  // flags is used to persuade the register allocator and the machine
1489
202
  // verifier to accept the usage of this register. This has to be a real
1490
202
  // register which has an UNDEF value but is dead after the instruction which
1491
202
  // is unique among the registers chosen for the instruction.
1492
202
1493
202
  // The EarlyClobber flag has the semantic properties that the operand it is
1494
202
  // attached to is clobbered before the rest of the inputs are read. Hence it
1495
202
  // must be unique among the operands to the instruction.
1496
202
  // The Define flag is needed to coerce the machine verifier that an Undef
1497
202
  // value isn't a problem.
1498
202
  // The Dead flag is needed as the value in scratch isn't used by any other
1499
202
  // instruction. Kill isn't used as Dead is more precise.
1500
202
  // The implicit flag is here due to the interaction between the other flags
1501
202
  // and the machine verifier.
1502
202
1503
202
  // For correctness purpose, a new pseudo is introduced here. We need this
1504
202
  // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1505
202
  // that is spread over >1 basic blocks. A register allocator which
1506
202
  // introduces (or any codegen infact) a store, can violate the expectations
1507
202
  // of the hardware.
1508
202
  //
1509
202
  // An atomic read-modify-write sequence starts with a linked load
1510
202
  // instruction and ends with a store conditional instruction. The atomic
1511
202
  // read-modify-write sequence fails if any of the following conditions
1512
202
  // occur between the execution of ll and sc:
1513
202
  //   * A coherent store is completed by another process or coherent I/O
1514
202
  //     module into the block of synchronizable physical memory containing
1515
202
  //     the word. The size and alignment of the block is
1516
202
  //     implementation-dependent.
1517
202
  //   * A coherent store is executed between an LL and SC sequence on the
1518
202
  //     same processor to the block of synchornizable physical memory
1519
202
  //     containing the word.
1520
202
  //
1521
202
1522
202
  unsigned PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1523
202
  unsigned IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1524
202
1525
202
  BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1526
202
  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1527
202
1528
202
  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1529
202
      .addReg(OldVal, RegState::Define | RegState::EarlyClobber)
1530
202
      .addReg(PtrCopy)
1531
202
      .addReg(IncrCopy)
1532
202
      .addReg(Scratch, RegState::Define | RegState::EarlyClobber |
1533
202
                           RegState::Implicit | RegState::Dead);
1534
202
1535
202
  MI.eraseFromParent();
1536
202
1537
202
  return BB;
1538
202
}
1539
1540
MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1541
    MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1542
0
    unsigned SrcReg) const {
1543
0
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1544
0
  const DebugLoc &DL = MI.getDebugLoc();
1545
0
1546
0
  if (Subtarget.hasMips32r2() && Size == 1) {
1547
0
    BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1548
0
    return BB;
1549
0
  }
1550
0
1551
0
  if (Subtarget.hasMips32r2() && Size == 2) {
1552
0
    BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1553
0
    return BB;
1554
0
  }
1555
0
1556
0
  MachineFunction *MF = BB->getParent();
1557
0
  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1558
0
  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1559
0
  unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1560
0
1561
0
  assert(Size < 32);
1562
0
  int64_t ShiftImm = 32 - (Size * 8);
1563
0
1564
0
  BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1565
0
  BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1566
0
1567
0
  return BB;
1568
0
}
1569
1570
MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1571
76
    MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1572
76
  assert((Size == 1 || Size == 2) &&
1573
76
         "Unsupported size for EmitAtomicBinaryPartial.");
1574
76
1575
76
  MachineFunction *MF = BB->getParent();
1576
76
  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1577
76
  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1578
76
  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1579
76
  const TargetRegisterClass *RCp =
1580
76
    getRegClassFor(ArePtrs64bit ? 
MVT::i6425
:
MVT::i3251
);
1581
76
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1582
76
  DebugLoc DL = MI.getDebugLoc();
1583
76
1584
76
  unsigned Dest = MI.getOperand(0).getReg();
1585
76
  unsigned Ptr = MI.getOperand(1).getReg();
1586
76
  unsigned Incr = MI.getOperand(2).getReg();
1587
76
1588
76
  unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1589
76
  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1590
76
  unsigned Mask = RegInfo.createVirtualRegister(RC);
1591
76
  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1592
76
  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1593
76
  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1594
76
  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1595
76
  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1596
76
  unsigned Scratch = RegInfo.createVirtualRegister(RC);
1597
76
  unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
1598
76
  unsigned Scratch3 = RegInfo.createVirtualRegister(RC);
1599
76
1600
76
  unsigned AtomicOp = 0;
1601
76
  switch (MI.getOpcode()) {
1602
76
  case Mips::ATOMIC_LOAD_NAND_I8:
1603
15
    AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1604
15
    break;
1605
76
  case Mips::ATOMIC_LOAD_NAND_I16:
1606
0
    AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1607
0
    break;
1608
76
  case Mips::ATOMIC_SWAP_I8:
1609
15
    AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1610
15
    break;
1611
76
  case Mips::ATOMIC_SWAP_I16:
1612
0
    AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1613
0
    break;
1614
76
  case Mips::ATOMIC_LOAD_ADD_I8:
1615
16
    AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1616
16
    break;
1617
76
  case Mips::ATOMIC_LOAD_ADD_I16:
1618
15
    AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1619
15
    break;
1620
76
  case Mips::ATOMIC_LOAD_SUB_I8:
1621
15
    AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1622
15
    break;
1623
76
  case Mips::ATOMIC_LOAD_SUB_I16:
1624
0
    AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1625
0
    break;
1626
76
  case Mips::ATOMIC_LOAD_AND_I8:
1627
0
    AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1628
0
    break;
1629
76
  case Mips::ATOMIC_LOAD_AND_I16:
1630
0
    AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1631
0
    break;
1632
76
  case Mips::ATOMIC_LOAD_OR_I8:
1633
0
    AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1634
0
    break;
1635
76
  case Mips::ATOMIC_LOAD_OR_I16:
1636
0
    AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1637
0
    break;
1638
76
  case Mips::ATOMIC_LOAD_XOR_I8:
1639
0
    AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1640
0
    break;
1641
76
  case Mips::ATOMIC_LOAD_XOR_I16:
1642
0
    AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1643
0
    break;
1644
76
  default:
1645
0
    llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1646
76
  }
1647
76
1648
76
  // insert new blocks after the current block
1649
76
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1650
76
  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1651
76
  MachineFunction::iterator It = ++BB->getIterator();
1652
76
  MF->insert(It, exitMBB);
1653
76
1654
76
  // Transfer the remainder of BB and its successor edges to exitMBB.
1655
76
  exitMBB->splice(exitMBB->begin(), BB,
1656
76
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1657
76
  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1658
76
1659
76
  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1660
76
1661
76
  //  thisMBB:
1662
76
  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1663
76
  //    and     alignedaddr,ptr,masklsb2
1664
76
  //    andi    ptrlsb2,ptr,3
1665
76
  //    sll     shiftamt,ptrlsb2,3
1666
76
  //    ori     maskupper,$0,255               # 0xff
1667
76
  //    sll     mask,maskupper,shiftamt
1668
76
  //    nor     mask2,$0,mask
1669
76
  //    sll     incr2,incr,shiftamt
1670
76
1671
76
  int64_t MaskImm = (Size == 1) ? 
25561
:
6553515
;
1672
76
  BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1673
76
    .addReg(ABI.GetNullPtr()).addImm(-4);
1674
76
  BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1675
76
    .addReg(Ptr).addReg(MaskLSB2);
1676
76
  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1677
76
      .addReg(Ptr, 0, ArePtrs64bit ? 
Mips::sub_3225
:
051
).addImm(3);
1678
76
  if (Subtarget.isLittle()) {
1679
66
    BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1680
66
  } else {
1681
10
    unsigned Off = RegInfo.createVirtualRegister(RC);
1682
10
    BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1683
10
      .addReg(PtrLSB2).addImm((Size == 1) ? 
38
:
22
);
1684
10
    BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1685
10
  }
1686
76
  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1687
76
    .addReg(Mips::ZERO).addImm(MaskImm);
1688
76
  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1689
76
    .addReg(MaskUpper).addReg(ShiftAmt);
1690
76
  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1691
76
  BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1692
76
1693
76
1694
76
  // The purposes of the flags on the scratch registers is explained in
1695
76
  // emitAtomicBinary. In summary, we need a scratch register which is going to
1696
76
  // be undef, that is unique among registers chosen for the instruction.
1697
76
1698
76
  BuildMI(BB, DL, TII->get(AtomicOp))
1699
76
      .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1700
76
      .addReg(AlignedAddr)
1701
76
      .addReg(Incr2)
1702
76
      .addReg(Mask)
1703
76
      .addReg(Mask2)
1704
76
      .addReg(ShiftAmt)
1705
76
      .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1706
76
                           RegState::Dead | RegState::Implicit)
1707
76
      .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1708
76
                            RegState::Dead | RegState::Implicit)
1709
76
      .addReg(Scratch3, RegState::EarlyClobber | RegState::Define |
1710
76
                            RegState::Dead | RegState::Implicit);
1711
76
1712
76
  MI.eraseFromParent(); // The instruction is gone now.
1713
76
1714
76
  return exitMBB;
1715
76
}
1716
1717
// Lower atomic compare and swap to a pseudo instruction, taking care to
1718
// define a scratch register for the pseudo instruction's expansion. The
1719
// instruction is expanded after the register allocator as to prevent
1720
// the insertion of stores between the linked load and the store conditional.
1721
1722
MachineBasicBlock *
1723
MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1724
42
                                      MachineBasicBlock *BB) const {
1725
42
1726
42
  assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1727
42
          MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1728
42
         "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1729
42
1730
42
  const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 
433
:
89
;
1731
42
1732
42
  MachineFunction *MF = BB->getParent();
1733
42
  MachineRegisterInfo &MRI = MF->getRegInfo();
1734
42
  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1735
42
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1736
42
  DebugLoc DL = MI.getDebugLoc();
1737
42
1738
42
  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1739
42
                          ? 
Mips::ATOMIC_CMP_SWAP_I32_POSTRA33
1740
42
                          : 
Mips::ATOMIC_CMP_SWAP_I64_POSTRA9
;
1741
42
  unsigned Dest = MI.getOperand(0).getReg();
1742
42
  unsigned Ptr = MI.getOperand(1).getReg();
1743
42
  unsigned OldVal = MI.getOperand(2).getReg();
1744
42
  unsigned NewVal = MI.getOperand(3).getReg();
1745
42
1746
42
  unsigned Scratch = MRI.createVirtualRegister(RC);
1747
42
  MachineBasicBlock::iterator II(MI);
1748
42
1749
42
  // We need to create copies of the various registers and kill them at the
1750
42
  // atomic pseudo. If the copies are not made, when the atomic is expanded
1751
42
  // after fast register allocation, the spills will end up outside of the
1752
42
  // blocks that their values are defined in, causing livein errors.
1753
42
1754
42
  unsigned PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1755
42
  unsigned OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1756
42
  unsigned NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1757
42
1758
42
  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1759
42
  BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1760
42
  BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1761
42
1762
42
  // The purposes of the flags on the scratch registers is explained in
1763
42
  // emitAtomicBinary. In summary, we need a scratch register which is going to
1764
42
  // be undef, that is unique among registers chosen for the instruction.
1765
42
1766
42
  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1767
42
      .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1768
42
      .addReg(PtrCopy, RegState::Kill)
1769
42
      .addReg(OldValCopy, RegState::Kill)
1770
42
      .addReg(NewValCopy, RegState::Kill)
1771
42
      .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1772
42
                           RegState::Dead | RegState::Implicit);
1773
42
1774
42
  MI.eraseFromParent(); // The instruction is gone now.
1775
42
1776
42
  return BB;
1777
42
}
1778
1779
MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1780
46
    MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1781
46
  assert((Size == 1 || Size == 2) &&
1782
46
      "Unsupported size for EmitAtomicCmpSwapPartial.");
1783
46
1784
46
  MachineFunction *MF = BB->getParent();
1785
46
  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1786
46
  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1787
46
  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1788
46
  const TargetRegisterClass *RCp =
1789
46
    getRegClassFor(ArePtrs64bit ? 
MVT::i6415
:
MVT::i3231
);
1790
46
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1791
46
  DebugLoc DL = MI.getDebugLoc();
1792
46
1793
46
  unsigned Dest = MI.getOperand(0).getReg();
1794
46
  unsigned Ptr = MI.getOperand(1).getReg();
1795
46
  unsigned CmpVal = MI.getOperand(2).getReg();
1796
46
  unsigned NewVal = MI.getOperand(3).getReg();
1797
46
1798
46
  unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1799
46
  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1800
46
  unsigned Mask = RegInfo.createVirtualRegister(RC);
1801
46
  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1802
46
  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1803
46
  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1804
46
  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1805
46
  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1806
46
  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1807
46
  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1808
46
  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1809
46
  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1810
46
                          ? 
Mips::ATOMIC_CMP_SWAP_I8_POSTRA31
1811
46
                          : 
Mips::ATOMIC_CMP_SWAP_I16_POSTRA15
;
1812
46
1813
46
  // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
1814
46
  // flags are used to coerce the register allocator and the machine verifier to
1815
46
  // accept the usage of these registers.
1816
46
  // The EarlyClobber flag has the semantic properties that the operand it is
1817
46
  // attached to is clobbered before the rest of the inputs are read. Hence it
1818
46
  // must be unique among the operands to the instruction.
1819
46
  // The Define flag is needed to coerce the machine verifier that an Undef
1820
46
  // value isn't a problem.
1821
46
  // The Dead flag is needed as the value in scratch isn't used by any other
1822
46
  // instruction. Kill isn't used as Dead is more precise.
1823
46
  unsigned Scratch = RegInfo.createVirtualRegister(RC);
1824
46
  unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
1825
46
1826
46
  // insert new blocks after the current block
1827
46
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1828
46
  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1829
46
  MachineFunction::iterator It = ++BB->getIterator();
1830
46
  MF->insert(It, exitMBB);
1831
46
1832
46
  // Transfer the remainder of BB and its successor edges to exitMBB.
1833
46
  exitMBB->splice(exitMBB->begin(), BB,
1834
46
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1835
46
  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1836
46
1837
46
  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1838
46
1839
46
  //  thisMBB:
1840
46
  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1841
46
  //    and     alignedaddr,ptr,masklsb2
1842
46
  //    andi    ptrlsb2,ptr,3
1843
46
  //    xori    ptrlsb2,ptrlsb2,3              # Only for BE
1844
46
  //    sll     shiftamt,ptrlsb2,3
1845
46
  //    ori     maskupper,$0,255               # 0xff
1846
46
  //    sll     mask,maskupper,shiftamt
1847
46
  //    nor     mask2,$0,mask
1848
46
  //    andi    maskedcmpval,cmpval,255
1849
46
  //    sll     shiftedcmpval,maskedcmpval,shiftamt
1850
46
  //    andi    maskednewval,newval,255
1851
46
  //    sll     shiftednewval,maskednewval,shiftamt
1852
46
  int64_t MaskImm = (Size == 1) ? 
25531
:
6553515
;
1853
46
  BuildMI(BB, DL, TII->get(ArePtrs64bit ? 
Mips::DADDiu15
:
Mips::ADDiu31
), MaskLSB2)
1854
46
    .addReg(ABI.GetNullPtr()).addImm(-4);
1855
46
  BuildMI(BB, DL, TII->get(ArePtrs64bit ? 
Mips::AND6415
:
Mips::AND31
), AlignedAddr)
1856
46
    .addReg(Ptr).addReg(MaskLSB2);
1857
46
  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1858
46
      .addReg(Ptr, 0, ArePtrs64bit ? 
Mips::sub_3215
:
031
).addImm(3);
1859
46
  if (Subtarget.isLittle()) {
1860
40
    BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1861
40
  } else {
1862
6
    unsigned Off = RegInfo.createVirtualRegister(RC);
1863
6
    BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1864
6
      .addReg(PtrLSB2).addImm((Size == 1) ? 
34
:
22
);
1865
6
    BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1866
6
  }
1867
46
  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1868
46
    .addReg(Mips::ZERO).addImm(MaskImm);
1869
46
  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1870
46
    .addReg(MaskUpper).addReg(ShiftAmt);
1871
46
  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1872
46
  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1873
46
    .addReg(CmpVal).addImm(MaskImm);
1874
46
  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1875
46
    .addReg(MaskedCmpVal).addReg(ShiftAmt);
1876
46
  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1877
46
    .addReg(NewVal).addImm(MaskImm);
1878
46
  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1879
46
    .addReg(MaskedNewVal).addReg(ShiftAmt);
1880
46
1881
46
  // The purposes of the flags on the scratch registers are explained in
1882
46
  // emitAtomicBinary. In summary, we need a scratch register which is going to
1883
46
  // be undef, that is unique among the register chosen for the instruction.
1884
46
1885
46
  BuildMI(BB, DL, TII->get(AtomicOp))
1886
46
      .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1887
46
      .addReg(AlignedAddr)
1888
46
      .addReg(Mask)
1889
46
      .addReg(ShiftedCmpVal)
1890
46
      .addReg(Mask2)
1891
46
      .addReg(ShiftedNewVal)
1892
46
      .addReg(ShiftAmt)
1893
46
      .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1894
46
                           RegState::Dead | RegState::Implicit)
1895
46
      .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1896
46
                            RegState::Dead | RegState::Implicit);
1897
46
1898
46
  MI.eraseFromParent(); // The instruction is gone now.
1899
46
1900
46
  return exitMBB;
1901
46
}
1902
1903
1.11k
SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1904
1.11k
  // The first operand is the chain, the second is the condition, the third is
1905
1.11k
  // the block to branch to if the condition is true.
1906
1.11k
  SDValue Chain = Op.getOperand(0);
1907
1.11k
  SDValue Dest = Op.getOperand(2);
1908
1.11k
  SDLoc DL(Op);
1909
1.11k
1910
1.11k
  assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1911
1.11k
  SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1912
1.11k
1913
1.11k
  // Return if flag is not set by a floating point comparison.
1914
1.11k
  if (CondRes.getOpcode() != MipsISD::FPCmp)
1915
1.04k
    return Op;
1916
64
1917
64
  SDValue CCNode  = CondRes.getOperand(2);
1918
64
  Mips::CondCode CC =
1919
64
    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1920
64
  unsigned Opc = invertFPCondCodeUser(CC) ? 
Mips::BRANCH_F41
:
Mips::BRANCH_T23
;
1921
64
  SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1922
64
  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1923
64
  return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1924
64
                     FCC0, Dest, CondRes);
1925
64
}
1926
1927
SDValue MipsTargetLowering::
1928
lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1929
1.95k
{
1930
1.95k
  assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1931
1.95k
  SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1932
1.95k
1933
1.95k
  // Return if flag is not set by a floating point comparison.
1934
1.95k
  if (Cond.getOpcode() != MipsISD::FPCmp)
1935
1.74k
    return Op;
1936
210
1937
210
  return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1938
210
                      SDLoc(Op));
1939
210
}
1940
1941
176
SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1942
176
  assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1943
176
  SDValue Cond = createFPCmp(DAG, Op);
1944
176
1945
176
  assert(Cond.getOpcode() == MipsISD::FPCmp &&
1946
176
         "Floating point operand expected.");
1947
176
1948
176
  SDLoc DL(Op);
1949
176
  SDValue True  = DAG.getConstant(1, DL, MVT::i32);
1950
176
  SDValue False = DAG.getConstant(0, DL, MVT::i32);
1951
176
1952
176
  return createCMovFP(DAG, Cond, True, False, DL);
1953
176
}
1954
1955
SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1956
8.42k
                                               SelectionDAG &DAG) const {
1957
8.42k
  EVT Ty = Op.getValueType();
1958
8.42k
  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1959
8.42k
  const GlobalValue *GV = N->getGlobal();
1960
8.42k
1961
8.42k
  if (!isPositionIndependent()) {
1962
3.57k
    const MipsTargetObjectFile *TLOF =
1963
3.57k
        static_cast<const MipsTargetObjectFile *>(
1964
3.57k
            getTargetMachine().getObjFileLowering());
1965
3.57k
    const GlobalObject *GO = GV->getBaseObject();
1966
3.57k
    if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
1967
12
      // %gp_rel relocation
1968
12
      return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
1969
3.55k
1970
3.55k
                                 // %hi/%lo relocation
1971
3.55k
    return Subtarget.hasSym32() ? 
getAddrNonPIC(N, SDLoc(N), Ty, DAG)3.32k
1972
3.55k
                                 // %highest/%higher/%hi/%lo relocation
1973
3.55k
                                 : 
getAddrNonPICSym64(N, SDLoc(N), Ty, DAG)230
;
1974
3.55k
  }
1975
4.85k
1976
4.85k
  // Every other architecture would use shouldAssumeDSOLocal in here, but
1977
4.85k
  // mips is special.
1978
4.85k
  // * In PIC code mips requires got loads even for local statics!
1979
4.85k
  // * To save on got entries, for local statics the got entry contains the
1980
4.85k
  //   page and an additional add instruction takes care of the low bits.
1981
4.85k
  // * It is legal to access a hidden symbol with a non hidden undefined,
1982
4.85k
  //   so one cannot guarantee that all access to a hidden symbol will know
1983
4.85k
  //   it is hidden.
1984
4.85k
  // * Mips linkers don't support creating a page and a full got entry for
1985
4.85k
  //   the same symbol.
1986
4.85k
  // * Given all that, we have to use a full got entry for hidden symbols :-(
1987
4.85k
  if (GV->hasLocalLinkage())
1988
100
    return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || 
ABI.IsN64()99
);
1989
4.75k
1990
4.75k
  if (LargeGOT)
1991
4
    return getAddrGlobalLargeGOT(
1992
4
        N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1993
4
        DAG.getEntryNode(),
1994
4
        MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1995
4.74k
1996
4.74k
  return getAddrGlobal(
1997
4.74k
      N, SDLoc(N), Ty, DAG,
1998
4.74k
      (ABI.IsN32() || 
ABI.IsN64()4.49k
) ?
MipsII::MO_GOT_DISP1.29k
:
MipsII::MO_GOT3.45k
,
1999
4.74k
      DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2000
4.74k
}
2001
2002
SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2003
16
                                              SelectionDAG &DAG) const {
2004
16
  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2005
16
  EVT Ty = Op.getValueType();
2006
16
2007
16
  if (!isPositionIndependent())
2008
10
    return Subtarget.hasSym32() ? 
getAddrNonPIC(N, SDLoc(N), Ty, DAG)8
2009
10
                                : 
getAddrNonPICSym64(N, SDLoc(N), Ty, DAG)2
;
2010
6
2011
6
  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || 
ABI.IsN64()4
);
2012
6
}
2013
2014
SDValue MipsTargetLowering::
2015
lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2016
54
{
2017
54
  // If the relocation model is PIC, use the General Dynamic TLS Model or
2018
54
  // Local Dynamic TLS model, otherwise use the Initial Exec or
2019
54
  // Local Exec TLS Model.
2020
54
2021
54
  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2022
54
  if (DAG.getTarget().useEmulatedTLS())
2023
12
    return LowerToTLSEmulatedModel(GA, DAG);
2024
42
2025
42
  SDLoc DL(GA);
2026
42
  const GlobalValue *GV = GA->getGlobal();
2027
42
  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2028
42
2029
42
  TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2030
42
2031
42
  if (model == TLSModel::GeneralDynamic || 
model == TLSModel::LocalDynamic34
) {
2032
16
    // General Dynamic and Local Dynamic TLS Model.
2033
16
    unsigned Flag = (model == TLSModel::LocalDynamic) ? 
MipsII::MO_TLSLDM8
2034
16
                                                      : 
MipsII::MO_TLSGD8
;
2035
16
2036
16
    SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2037
16
    SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2038
16
                                   getGlobalReg(DAG, PtrVT), TGA);
2039
16
    unsigned PtrSize = PtrVT.getSizeInBits();
2040
16
    IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2041
16
2042
16
    SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2043
16
2044
16
    ArgListTy Args;
2045
16
    ArgListEntry Entry;
2046
16
    Entry.Node = Argument;
2047
16
    Entry.Ty = PtrTy;
2048
16
    Args.push_back(Entry);
2049
16
2050
16
    TargetLowering::CallLoweringInfo CLI(DAG);
2051
16
    CLI.setDebugLoc(DL)
2052
16
        .setChain(DAG.getEntryNode())
2053
16
        .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2054
16
    std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2055
16
2056
16
    SDValue Ret = CallResult.first;
2057
16
2058
16
    if (model != TLSModel::LocalDynamic)
2059
8
      return Ret;
2060
8
2061
8
    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2062
8
                                               MipsII::MO_DTPREL_HI);
2063
8
    SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2064
8
    SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2065
8
                                               MipsII::MO_DTPREL_LO);
2066
8
    SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2067
8
    SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2068
8
    return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2069
8
  }
2070
26
2071
26
  SDValue Offset;
2072
26
  if (model == TLSModel::InitialExec) {
2073
11
    // Initial Exec TLS Model
2074
11
    SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2075
11
                                             MipsII::MO_GOTTPREL);
2076
11
    TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2077
11
                      TGA);
2078
11
    Offset =
2079
11
        DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2080
15
  } else {
2081
15
    // Local Exec TLS Model
2082
15
    assert(model == TLSModel::LocalExec);
2083
15
    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2084
15
                                               MipsII::MO_TPREL_HI);
2085
15
    SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2086
15
                                               MipsII::MO_TPREL_LO);
2087
15
    SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2088
15
    SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2089
15
    Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2090
15
  }
2091
26
2092
26
  SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2093
26
  return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2094
26
}
2095
2096
SDValue MipsTargetLowering::
2097
lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2098
22
{
2099
22
  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2100
22
  EVT Ty = Op.getValueType();
2101
22
2102
22
  if (!isPositionIndependent())
2103
13
    return Subtarget.hasSym32() ? 
getAddrNonPIC(N, SDLoc(N), Ty, DAG)8
2104
13
                                : 
getAddrNonPICSym64(N, SDLoc(N), Ty, DAG)5
;
2105
9
2106
9
  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2107
9
}
2108
2109
SDValue MipsTargetLowering::
2110
lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2111
542
{
2112
542
  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2113
542
  EVT Ty = Op.getValueType();
2114
542
2115
542
  if (!isPositionIndependent()) {
2116
318
    const MipsTargetObjectFile *TLOF =
2117
318
        static_cast<const MipsTargetObjectFile *>(
2118
318
            getTargetMachine().getObjFileLowering());
2119
318
2120
318
    if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2121
318
                                       getTargetMachine()))
2122
0
      // %gp_rel relocation
2123
0
      return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2124
318
2125
318
    return Subtarget.hasSym32() ? 
getAddrNonPIC(N, SDLoc(N), Ty, DAG)282
2126
318
                                : 
getAddrNonPICSym64(N, SDLoc(N), Ty, DAG)36
;
2127
318
  }
2128
224
2129
224
 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || 
ABI.IsN64()189
);
2130
224
}
2131
2132
76
SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2133
76
  MachineFunction &MF = DAG.getMachineFunction();
2134
76
  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2135
76
2136
76
  SDLoc DL(Op);
2137
76
  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2138
76
                                 getPointerTy(MF.getDataLayout()));
2139
76
2140
76
  // vastart just stores the address of the VarArgsFrameIndex slot into the
2141
76
  // memory location argument.
2142
76
  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2143
76
  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2144
76
                      MachinePointerInfo(SV));
2145
76
}
2146
2147
142
SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2148
142
  SDNode *Node = Op.getNode();
2149
142
  EVT VT = Node->getValueType(0);
2150
142
  SDValue Chain = Node->getOperand(0);
2151
142
  SDValue VAListPtr = Node->getOperand(1);
2152
142
  unsigned Align = Node->getConstantOperandVal(3);
2153
142
  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2154
142
  SDLoc DL(Node);
2155
142
  unsigned ArgSlotSizeInBytes = (ABI.IsN32() || 
ABI.IsN64()102
) ?
880
:
462
;
2156
142
2157
142
  SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2158
142
                                   VAListPtr, MachinePointerInfo(SV));
2159
142
  SDValue VAList = VAListLoad;
2160
142
2161
142
  // Re-align the pointer if necessary.
2162
142
  // It should only ever be necessary for 64-bit types on O32 since the minimum
2163
142
  // argument alignment is the same as the maximum type alignment for N32/N64.
2164
142
  //
2165
142
  // FIXME: We currently align too often. The code generator doesn't notice
2166
142
  //        when the pointer is still aligned from the last va_arg (or pair of
2167
142
  //        va_args for the i64 on O32 case).
2168
142
  if (Align > getMinStackArgumentAlignment()) {
2169
19
    assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2170
19
2171
19
    VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2172
19
                         DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2173
19
2174
19
    VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2175
19
                         DAG.getConstant(-(int64_t)Align, DL,
2176
19
                                         VAList.getValueType()));
2177
19
  }
2178
142
2179
142
  // Increment the pointer, VAList, to the next vaarg.
2180
142
  auto &TD = DAG.getDataLayout();
2181
142
  unsigned ArgSizeInBytes =
2182
142
      TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2183
142
  SDValue Tmp3 =
2184
142
      DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2185
142
                  DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2186
142
                                  DL, VAList.getValueType()));
2187
142
  // Store the incremented VAList to the legalized pointer
2188
142
  Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2189
142
                       MachinePointerInfo(SV));
2190
142
2191
142
  // In big-endian mode we must adjust the pointer when the load size is smaller
2192
142
  // than the argument slot size. We must also reduce the known alignment to
2193
142
  // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2194
142
  // the correct half of the slot, and reduce the alignment from 8 (slot
2195
142
  // alignment) down to 4 (type alignment).
2196
142
  if (!Subtarget.isLittle() && 
ArgSizeInBytes < ArgSlotSizeInBytes66
) {
2197
26
    unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2198
26
    VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2199
26
                         DAG.getIntPtrConstant(Adjustment, DL));
2200
26
  }
2201
142
  // Load the actual argument out of the pointer VAList
2202
142
  return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2203
142
}
2204
2205
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2206
11
                                bool HasExtractInsert) {
2207
11
  EVT TyX = Op.getOperand(0).getValueType();
2208
11
  EVT TyY = Op.getOperand(1).getValueType();
2209
11
  SDLoc DL(Op);
2210
11
  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2211
11
  SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2212
11
  SDValue Res;
2213
11
2214
11
  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2215
11
  // to i32.
2216
11
  SDValue X = (TyX == MVT::f32) ?
2217
8
    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2218
11
    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2219
3
                Const1);
2220
11
  SDValue Y = (TyY == MVT::f32) ?
2221
6
    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2222
11
    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2223
5
                Const1);
2224
11
2225
11
  if (HasExtractInsert) {
2226
6
    // ext  E, Y, 31, 1  ; extract bit31 of Y
2227
6
    // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
2228
6
    SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2229
6
    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2230
6
  } else {
2231
5
    // sll SllX, X, 1
2232
5
    // srl SrlX, SllX, 1
2233
5
    // srl SrlY, Y, 31
2234
5
    // sll SllY, SrlX, 31
2235
5
    // or  Or, SrlX, SllY
2236
5
    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2237
5
    SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2238
5
    SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2239
5
    SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2240
5
    Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2241
5
  }
2242
11
2243
11
  if (TyX == MVT::f32)
2244
8
    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2245
3
2246
3
  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2247
3
                             Op.getOperand(0),
2248
3
                             DAG.getConstant(0, DL, MVT::i32));
2249
3
  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2250
3
}
2251
2252
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2253
16
                                bool HasExtractInsert) {
2254
16
  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2255
16
  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2256
16
  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2257
16
  SDLoc DL(Op);
2258
16
  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2259
16
2260
16
  // Bitcast to integer nodes.
2261
16
  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2262
16
  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2263
16
2264
16
  if (HasExtractInsert) {
2265
8
    // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
2266
8
    // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
2267
8
    SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2268
8
                            DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2269
8
2270
8
    if (WidthX > WidthY)
2271
1
      E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2272
7
    else if (WidthY > WidthX)
2273
1
      E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2274
8
2275
8
    SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2276
8
                            DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2277
8
                            X);
2278
8
    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2279
8
  }
2280
8
2281
8
  // (d)sll SllX, X, 1
2282
8
  // (d)srl SrlX, SllX, 1
2283
8
  // (d)srl SrlY, Y, width(Y)-1
2284
8
  // (d)sll SllY, SrlX, width(Y)-1
2285
8
  // or     Or, SrlX, SllY
2286
8
  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2287
8
  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2288
8
  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2289
8
                             DAG.getConstant(WidthY - 1, DL, MVT::i32));
2290
8
2291
8
  if (WidthX > WidthY)
2292
2
    SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2293
6
  else if (WidthY > WidthX)
2294
2
    SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2295
8
2296
8
  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2297
8
                             DAG.getConstant(WidthX - 1, DL, MVT::i32));
2298
8
  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2299
8
  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2300
8
}
2301
2302
SDValue
2303
27
MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2304
27
  if (Subtarget.isGP64bit())
2305
16
    return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2306
11
2307
11
  return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2308
11
}
2309
2310
static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
2311
24
                           bool HasExtractInsert) {
2312
24
  SDLoc DL(Op);
2313
24
  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2314
24
2315
24
  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2316
24
  // to i32.
2317
24
  SDValue X = (Op.getValueType() == MVT::f32)
2318
24
                  ? 
DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))14
2319
24
                  : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2320
10
                                Op.getOperand(0), Const1);
2321
24
2322
24
  // Clear MSB.
2323
24
  if (HasExtractInsert)
2324
10
    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2325
10
                      DAG.getRegister(Mips::ZERO, MVT::i32),
2326
10
                      DAG.getConstant(31, DL, MVT::i32), Const1, X);
2327
14
  else {
2328
14
    // TODO: Provide DAG patterns which transform (and x, cst)
2329
14
    // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2330
14
    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2331
14
    Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2332
14
  }
2333
24
2334
24
  if (Op.getValueType() == MVT::f32)
2335
14
    return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2336
10
2337
10
  // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2338
10
  // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2339
10
  // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2340
10
  // place.
2341
10
  SDValue LowX =
2342
10
      DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2343
10
                  DAG.getConstant(0, DL, MVT::i32));
2344
10
  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2345
10
}
2346
2347
static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
2348
4
                           bool HasExtractInsert) {
2349
4
  SDLoc DL(Op);
2350
4
  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2351
4
2352
4
  // Bitcast to integer node.
2353
4
  SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2354
4
2355
4
  // Clear MSB.
2356
4
  if (HasExtractInsert)
2357
2
    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2358
2
                      DAG.getRegister(Mips::ZERO_64, MVT::i64),
2359
2
                      DAG.getConstant(63, DL, MVT::i32), Const1, X);
2360
2
  else {
2361
2
    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2362
2
    Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2363
2
  }
2364
4
2365
4
  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2366
4
}
2367
2368
28
SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2369
28
  if ((ABI.IsN32() || ABI.IsN64()) && 
(Op.getValueType() == MVT::f64)8
)
2370
4
    return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2371
24
2372
24
  return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2373
24
}
2374
2375
SDValue MipsTargetLowering::
2376
5
lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2377
5
  // check the depth
2378
5
  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2379
1
    DAG.getContext()->emitError(
2380
1
        "return address can be determined only for current frame");
2381
1
    return SDValue();
2382
1
  }
2383
4
2384
4
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2385
4
  MFI.setFrameAddressIsTaken(true);
2386
4
  EVT VT = Op.getValueType();
2387
4
  SDLoc DL(Op);
2388
4
  SDValue FrameAddr = DAG.getCopyFromReg(
2389
4
      DAG.getEntryNode(), DL, ABI.IsN64() ? 
Mips::FP_642
:
Mips::FP2
, VT);
2390
4
  return FrameAddr;
2391
4
}
2392
2393
SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2394
3
                                            SelectionDAG &DAG) const {
2395
3
  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2396
0
    return SDValue();
2397
3
2398
3
  // check the depth
2399
3
  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2400
1
    DAG.getContext()->emitError(
2401
1
        "return address can be determined only for current frame");
2402
1
    return SDValue();
2403
1
  }
2404
2
2405
2
  MachineFunction &MF = DAG.getMachineFunction();
2406
2
  MachineFrameInfo &MFI = MF.getFrameInfo();
2407
2
  MVT VT = Op.getSimpleValueType();
2408
2
  unsigned RA = ABI.IsN64() ? 
Mips::RA_640
: Mips::RA;
2409
2
  MFI.setReturnAddressIsTaken(true);
2410
2
2411
2
  // Return RA, which contains the return address. Mark it an implicit live-in.
2412
2
  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2413
2
  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2414
2
}
2415
2416
// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2417
// generated from __builtin_eh_return (offset, handler)
2418
// The effect of this is to adjust the stack pointer by "offset"
2419
// and then branch to "handler".
2420
SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2421
14
                                                                     const {
2422
14
  MachineFunction &MF = DAG.getMachineFunction();
2423
14
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2424
14
2425
14
  MipsFI->setCallsEhReturn();
2426
14
  SDValue Chain     = Op.getOperand(0);
2427
14
  SDValue Offset    = Op.getOperand(1);
2428
14
  SDValue Handler   = Op.getOperand(2);
2429
14
  SDLoc DL(Op);
2430
14
  EVT Ty = ABI.IsN64() ? 
MVT::i648
:
MVT::i326
;
2431
14
2432
14
  // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2433
14
  // EH_RETURN nodes, so that instructions are emitted back-to-back.
2434
14
  unsigned OffsetReg = ABI.IsN64() ? 
Mips::V1_648
:
Mips::V16
;
2435
14
  unsigned AddrReg = ABI.IsN64() ? 
Mips::V0_648
:
Mips::V06
;
2436
14
  Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2437
14
  Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2438
14
  return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2439
14
                     DAG.getRegister(OffsetReg, Ty),
2440
14
                     DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2441
14
                     Chain.getValue(1));
2442
14
}
2443
2444
SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2445
131
                                              SelectionDAG &DAG) const {
2446
131
  // FIXME: Need pseudo-fence for 'singlethread' fences
2447
131
  // FIXME: Set SType for weaker fences where supported/appropriate.
2448
131
  unsigned SType = 0;
2449
131
  SDLoc DL(Op);
2450
131
  return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2451
131
                     DAG.getConstant(SType, DL, MVT::i32));
2452
131
}
2453
2454
SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2455
56
                                                SelectionDAG &DAG) const {
2456
56
  SDLoc DL(Op);
2457
56
  MVT VT = Subtarget.isGP64bit() ? 
MVT::i647
:
MVT::i3249
;
2458
56
2459
56
  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2460
56
  SDValue Shamt = Op.getOperand(2);
2461
56
  // if shamt < (VT.bits):
2462
56
  //  lo = (shl lo, shamt)
2463
56
  //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2464
56
  // else:
2465
56
  //  lo = 0
2466
56
  //  hi = (shl lo, shamt[4:0])
2467
56
  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2468
56
                            DAG.getConstant(-1, DL, MVT::i32));
2469
56
  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2470
56
                                      DAG.getConstant(1, DL, VT));
2471
56
  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2472
56
  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2473
56
  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2474
56
  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2475
56
  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2476
56
                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2477
56
  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2478
56
                   DAG.getConstant(0, DL, VT), ShiftLeftLo);
2479
56
  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2480
56
2481
56
  SDValue Ops[2] = {Lo, Hi};
2482
56
  return DAG.getMergeValues(Ops, DL);
2483
56
}
2484
2485
SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2486
88
                                                 bool IsSRA) const {
2487
88
  SDLoc DL(Op);
2488
88
  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2489
88
  SDValue Shamt = Op.getOperand(2);
2490
88
  MVT VT = Subtarget.isGP64bit() ? 
MVT::i6414
:
MVT::i3274
;
2491
88
2492
88
  // if shamt < (VT.bits):
2493
88
  //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2494
88
  //  if isSRA:
2495
88
  //    hi = (sra hi, shamt)
2496
88
  //  else:
2497
88
  //    hi = (srl hi, shamt)
2498
88
  // else:
2499
88
  //  if isSRA:
2500
88
  //   lo = (sra hi, shamt[4:0])
2501
88
  //   hi = (sra hi, 31)
2502
88
  //  else:
2503
88
  //   lo = (srl hi, shamt[4:0])
2504
88
  //   hi = 0
2505
88
  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2506
88
                            DAG.getConstant(-1, DL, MVT::i32));
2507
88
  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2508
88
                                     DAG.getConstant(1, DL, VT));
2509
88
  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2510
88
  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2511
88
  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2512
88
  SDValue ShiftRightHi = DAG.getNode(IsSRA ? 
ISD::SRA32
:
ISD::SRL56
,
2513
88
                                     DL, VT, Hi, Shamt);
2514
88
  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2515
88
                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2516
88
  SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2517
88
                            DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2518
88
2519
88
  if (!(Subtarget.hasMips4() || 
Subtarget.hasMips32()76
)) {
2520
11
    SDVTList VTList = DAG.getVTList(VT, VT);
2521
11
    return DAG.getNode(Subtarget.isGP64bit() ? 
Mips::PseudoD_SELECT_I642
2522
11
                                             : 
Mips::PseudoD_SELECT_I9
,
2523
11
                       DL, VTList, Cond, ShiftRightHi,
2524
11
                       IsSRA ? 
Ext4
:
DAG.getConstant(0, DL, VT)7
, Or,
2525
11
                       ShiftRightHi);
2526
11
  }
2527
77
2528
77
  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2529
77
  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2530
77
                   IsSRA ? 
Ext28
:
DAG.getConstant(0, DL, VT)49
, ShiftRightHi);
2531
77
2532
77
  SDValue Ops[2] = {Lo, Hi};
2533
77
  return DAG.getMergeValues(Ops, DL);
2534
77
}
2535
2536
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2537
280
                            SDValue Chain, SDValue Src, unsigned Offset) {
2538
280
  SDValue Ptr = LD->getBasePtr();
2539
280
  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2540
280
  EVT BasePtrVT = Ptr.getValueType();
2541
280
  SDLoc DL(LD);
2542
280
  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2543
280
2544
280
  if (Offset)
2545
140
    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2546
140
                      DAG.getConstant(Offset, DL, BasePtrVT));
2547
280
2548
280
  SDValue Ops[] = { Chain, Ptr, Src };
2549
280
  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2550
280
                                 LD->getMemOperand());
2551
280
}
2552
2553
// Expand an unaligned 32 or 64-bit integer load node.
2554
17.7k
SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2555
17.7k
  LoadSDNode *LD = cast<LoadSDNode>(Op);
2556
17.7k
  EVT MemVT = LD->getMemoryVT();
2557
17.7k
2558
17.7k
  if (Subtarget.systemSupportsUnalignedAccess())
2559
2.57k
    return Op;
2560
15.1k
2561
15.1k
  // Return if load is aligned or if MemVT is neither i32 nor i64.
2562
15.1k
  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2563
15.1k
      
(140
(MemVT != MVT::i32)140
&&
(MemVT != MVT::i64)27
))
2564
15.0k
    return SDValue();
2565
140
2566
140
  bool IsLittle = Subtarget.isLittle();
2567
140
  EVT VT = Op.getValueType();
2568
140
  ISD::LoadExtType ExtType = LD->getExtensionType();
2569
140
  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2570
140
2571
140
  assert((VT == MVT::i32) || (VT == MVT::i64));
2572
140
2573
140
  // Expand
2574
140
  //  (set dst, (i64 (load baseptr)))
2575
140
  // to
2576
140
  //  (set tmp, (ldl (add baseptr, 7), undef))
2577
140
  //  (set dst, (ldr baseptr, tmp))
2578
140
  if ((VT == MVT::i64) && 
(ExtType == ISD::NON_EXTLOAD)45
) {
2579
27
    SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2580
27
                               IsLittle ? 
717
:
010
);
2581
27
    return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2582
27
                        IsLittle ? 
017
:
710
);
2583
27
  }
2584
113
2585
113
  SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2586
113
                             IsLittle ? 
363
:
050
);
2587
113
  SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2588
113
                             IsLittle ? 
063
:
350
);
2589
113
2590
113
  // Expand
2591
113
  //  (set dst, (i32 (load baseptr))) or
2592
113
  //  (set dst, (i64 (sextload baseptr))) or
2593
113
  //  (set dst, (i64 (extload baseptr)))
2594
113
  // to
2595
113
  //  (set tmp, (lwl (add baseptr, 3), undef))
2596
113
  //  (set dst, (lwr baseptr, tmp))
2597
113
  if ((VT == MVT::i32) || 
(ExtType == ISD::SEXTLOAD)18
||
2598
113
      
(ExtType == ISD::EXTLOAD)12
)
2599
101
    return LWR;
2600
12
2601
12
  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2602
12
2603
12
  // Expand
2604
12
  //  (set dst, (i64 (zextload baseptr)))
2605
12
  // to
2606
12
  //  (set tmp0, (lwl (add baseptr, 3), undef))
2607
12
  //  (set tmp1, (lwr baseptr, tmp0))
2608
12
  //  (set tmp2, (shl tmp1, 32))
2609
12
  //  (set dst, (srl tmp2, 32))
2610
12
  SDLoc DL(LD);
2611
12
  SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2612
12
  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2613
12
  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2614
12
  SDValue Ops[] = { SRL, LWR.getValue(1) };
2615
12
  return DAG.getMergeValues(Ops, DL);
2616
12
}
2617
2618
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2619
218
                             SDValue Chain, unsigned Offset) {
2620
218
  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2621
218
  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2622
218
  SDLoc DL(SD);
2623
218
  SDVTList VTList = DAG.getVTList(MVT::Other);
2624
218
2625
218
  if (Offset)
2626
109
    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2627
109
                      DAG.getConstant(Offset, DL, BasePtrVT));
2628
218
2629
218
  SDValue Ops[] = { Chain, Value, Ptr };
2630
218
  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2631
218
                                 SD->getMemOperand());
2632
218
}
2633
2634
// Expand an unaligned 32 or 64-bit integer store node.
2635
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2636
109
                                      bool IsLittle) {
2637
109
  SDValue Value = SD->getValue(), Chain = SD->getChain();
2638
109
  EVT VT = Value.getValueType();
2639
109
2640
109
  // Expand
2641
109
  //  (store val, baseptr) or
2642
109
  //  (truncstore val, baseptr)
2643
109
  // to
2644
109
  //  (swl val, (add baseptr, 3))
2645
109
  //  (swr val, baseptr)
2646
109
  if ((VT == MVT::i32) || 
SD->isTruncatingStore()22
) {
2647
87
    SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2648
87
                                IsLittle ? 
355
:
032
);
2649
87
    return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 
055
:
332
);
2650
87
  }
2651
22
2652
22
  assert(VT == MVT::i64);
2653
22
2654
22
  // Expand
2655
22
  //  (store val, baseptr)
2656
22
  // to
2657
22
  //  (sdl val, (add baseptr, 7))
2658
22
  //  (sdr val, baseptr)
2659
22
  SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 
716
:
06
);
2660
22
  return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 
016
:
76
);
2661
22
}
2662
2663
// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2664
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG,
2665
7.54k
                                     bool SingleFloat) {
2666
7.54k
  SDValue Val = SD->getValue();
2667
7.54k
2668
7.54k
  if (Val.getOpcode() != ISD::FP_TO_SINT ||
2669
7.54k
      
(11
Val.getValueSizeInBits() > 3211
&&
SingleFloat5
))
2670
7.53k
    return SDValue();
2671
10
2672
10
  EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2673
10
  SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2674
10
                           Val.getOperand(0));
2675
10
  return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2676
10
                      SD->getPointerInfo(), SD->getAlignment(),
2677
10
                      SD->getMemOperand()->getFlags());
2678
10
}
2679
2680
7.65k
SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2681
7.65k
  StoreSDNode *SD = cast<StoreSDNode>(Op);
2682
7.65k
  EVT MemVT = SD->getMemoryVT();
2683
7.65k
2684
7.65k
  // Lower unaligned integer stores.
2685
7.65k
  if (!Subtarget.systemSupportsUnalignedAccess() &&
2686
7.65k
      
(SD->getAlignment() < MemVT.getSizeInBits() / 8)6.79k
&&
2687
7.65k
      
(109
(MemVT == MVT::i32)109
||
(MemVT == MVT::i64)22
))
2688
109
    return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2689
7.54k
2690
7.54k
  return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat());
2691
7.54k
}
2692
2693
SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2694
12
                                              SelectionDAG &DAG) const {
2695
12
2696
12
  // Return a fixed StackObject with offset 0 which points to the old stack
2697
12
  // pointer.
2698
12
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2699
12
  EVT ValTy = Op->getValueType(0);
2700
12
  int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2701
12
  return DAG.getFrameIndex(FI, ValTy);
2702
12
}
2703
2704
SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2705
46
                                            SelectionDAG &DAG) const {
2706
46
  if (Op.getValueSizeInBits() > 32 && 
Subtarget.isSingleFloat()3
)
2707
1
    return SDValue();
2708
45
2709
45
  EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2710
45
  SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2711
45
                              Op.getOperand(0));
2712
45
  return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2713
45
}
2714
2715
//===----------------------------------------------------------------------===//
2716
//                      Calling Convention Implementation
2717
//===----------------------------------------------------------------------===//
2718
2719
//===----------------------------------------------------------------------===//
2720
// TODO: Implement a generic logic using tblgen that can support this.
2721
// Mips O32 ABI rules:
2722
// ---
2723
// i32 - Passed in A0, A1, A2, A3 and stack
2724
// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2725
//       an argument. Otherwise, passed in A1, A2, A3 and stack.
2726
// f64 - Only passed in two aliased f32 registers if no int reg has been used
2727
//       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2728
//       not used, it must be shadowed. If only A3 is available, shadow it and
2729
//       go to stack.
2730
// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2731
// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2732
//         with the remainder spilled to the stack.
2733
// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2734
//         spilling the remainder to the stack.
2735
//
2736
//  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2737
//===----------------------------------------------------------------------===//
2738
2739
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2740
                       CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2741
17.1k
                       CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2742
17.1k
  const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2743
17.1k
      State.getMachineFunction().getSubtarget());
2744
17.1k
2745
17.1k
  static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2746
17.1k
2747
17.1k
  const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2748
17.1k
2749
17.1k
  static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2750
17.1k
2751
17.1k
  static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2752
17.1k
2753
17.1k
  // Do not process byval args here.
2754
17.1k
  if (ArgFlags.isByVal())
2755
0
    return true;
2756
17.1k
2757
17.1k
  // Promote i8 and i16
2758
17.1k
  if (ArgFlags.isInReg() && 
!Subtarget.isLittle()10
) {
2759
9
    if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2760
9
      LocVT = MVT::i32;
2761
9
      if (ArgFlags.isSExt())
2762
0
        LocInfo = CCValAssign::SExtUpper;
2763
9
      else if (ArgFlags.isZExt())
2764
0
        LocInfo = CCValAssign::ZExtUpper;
2765
9
      else
2766
9
        LocInfo = CCValAssign::AExtUpper;
2767
9
    }
2768
9
  }
2769
17.1k
2770
17.1k
  // Promote i8 and i16
2771
17.1k
  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2772
0
    LocVT = MVT::i32;
2773
0
    if (ArgFlags.isSExt())
2774
0
      LocInfo = CCValAssign::SExt;
2775
0
    else if (ArgFlags.isZExt())
2776
0
      LocInfo = CCValAssign::ZExt;
2777
0
    else
2778
0
      LocInfo = CCValAssign::AExt;
2779
0
  }
2780
17.1k
2781
17.1k
  unsigned Reg;
2782
17.1k
2783
17.1k
  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2784
17.1k
  // is true: function is vararg, argument is 3rd or higher, there is previous
2785
17.1k
  // argument which is not f32 or f64.
2786
17.1k
  bool AllocateFloatsInIntReg = State.isVarArg() || 
ValNo > 116.5k
||
2787
17.1k
                                
State.getFirstUnallocated(F32Regs) != ValNo11.1k
;
2788
17.1k
  unsigned OrigAlign = ArgFlags.getOrigAlign();
2789
17.1k
  bool isI64 = (ValVT == MVT::i32 && 
OrigAlign == 814.7k
);
2790
17.1k
  bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2791
17.1k
2792
17.1k
  // The MIPS vector ABI for floats passes them in a pair of registers
2793
17.1k
  if (ValVT == MVT::i32 && 
isVectorFloat14.7k
) {
2794
720
    // This is the start of an vector that was scalarized into an unknown number
2795
720
    // of components. It doesn't matter how many there are. Allocate one of the
2796
720
    // notional 8 byte aligned registers which map onto the argument stack, and
2797
720
    // shadow the register lost to alignment requirements.
2798
720
    if (ArgFlags.isSplit()) {
2799
196
      Reg = State.AllocateReg(FloatVectorIntRegs);
2800
196
      if (Reg == Mips::A2)
2801
53
        State.AllocateReg(Mips::A1);
2802
143
      else if (Reg == 0)
2803
64
        State.AllocateReg(Mips::A3);
2804
524
    } else {
2805
524
      // If we're an intermediate component of the split, we can just attempt to
2806
524
      // allocate a register directly.
2807
524
      Reg = State.AllocateReg(IntRegs);
2808
524
    }
2809
16.4k
  } else if (ValVT == MVT::i32 || 
(2.34k
ValVT == MVT::f322.34k
&&
AllocateFloatsInIntReg1.18k
)) {
2810
14.3k
    Reg = State.AllocateReg(IntRegs);
2811
14.3k
    // If this is the first part of an i64 arg,
2812
14.3k
    // the allocated register must be either A0 or A2.
2813
14.3k
    if (isI64 && 
(1.85k
Reg == Mips::A11.85k
||
Reg == Mips::A31.78k
))
2814
70
      Reg = State.AllocateReg(IntRegs);
2815
14.3k
    LocVT = MVT::i32;
2816
14.3k
  } else 
if (2.04k
ValVT == MVT::f642.04k
&&
AllocateFloatsInIntReg1.15k
) {
2817
274
    // Allocate int register and shadow next int register. If first
2818
274
    // available register is Mips::A1 or Mips::A3, shadow it too.
2819
274
    Reg = State.AllocateReg(IntRegs);
2820
274
    if (Reg == Mips::A1 || 
Reg == Mips::A3169
)
2821
117
      Reg = State.AllocateReg(IntRegs);
2822
274
    State.AllocateReg(IntRegs);
2823
274
    LocVT = MVT::i32;
2824
1.77k
  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2825
1.77k
    // we are guaranteed to find an available float register
2826
1.77k
    if (ValVT == MVT::f32) {
2827
894
      Reg = State.AllocateReg(F32Regs);
2828
894
      // Shadow int register
2829
894
      State.AllocateReg(IntRegs);
2830
894
    } else {
2831
878
      Reg = State.AllocateReg(F64Regs);
2832
878
      // Shadow int registers
2833
878
      unsigned Reg2 = State.AllocateReg(IntRegs);
2834
878
      if (Reg2 == Mips::A1 || 
Reg2 == Mips::A3864
)
2835
14
        State.AllocateReg(IntRegs);
2836
878
      State.AllocateReg(IntRegs);
2837
878
    }
2838
1.77k
  } else
2839
1.77k
    
llvm_unreachable0
("Cannot handle this ValVT.");
2840
17.1k
2841
17.1k
  if (!Reg) {
2842
2.23k
    unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2843
2.23k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2844
2.23k
  } else
2845
14.8k
    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2846
17.1k
2847
17.1k
  return false;
2848
17.1k
}
2849
2850
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2851
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
2852
10.8k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2853
10.8k
  static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2854
10.8k
2855
10.8k
  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2856
10.8k
}
2857
2858
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2859
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
2860
6.28k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2861
6.28k
  static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2862
6.28k
2863
6.28k
  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2864
6.28k
}
2865
2866
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2867
                       CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2868
                       CCState &State) LLVM_ATTRIBUTE_UNUSED;
2869
2870
#include "MipsGenCallingConv.inc"
2871
2872
480
 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
2873
480
   return CC_Mips;
2874
480
 }
2875
2876
471
 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
2877
471
   return RetCC_Mips;
2878
471
 }
2879
//===----------------------------------------------------------------------===//
2880
//                  Call Calling Convention Implementation
2881
//===----------------------------------------------------------------------===//
2882
2883
// Return next O32 integer argument register.
2884
149
static unsigned getNextIntArgReg(unsigned Reg) {
2885
149
  assert((Reg == Mips::A0) || (Reg == Mips::A2));
2886
149
  return (Reg == Mips::A0) ? 
Mips::A122
:
Mips::A3127
;
2887
149
}
2888
2889
SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2890
                                           SDValue Chain, SDValue Arg,
2891
                                           const SDLoc &DL, bool IsTailCall,
2892
904
                                           SelectionDAG &DAG) const {
2893
904
  if (!IsTailCall) {
2894
853
    SDValue PtrOff =
2895
853
        DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2896
853
                    DAG.getIntPtrConstant(Offset, DL));
2897
853
    return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2898
853
  }
2899
51
2900
51
  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2901
51
  int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2902
51
  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2903
51
  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2904
51
                      /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2905
51
}
2906
2907
void MipsTargetLowering::
2908
getOpndList(SmallVectorImpl<SDValue> &Ops,
2909
            std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2910
            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2911
            bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2912
3.13k
            SDValue Chain) const {
2913
3.13k
  // Insert node "GP copy globalreg" before call to function.
2914
3.13k
  //
2915
3.13k
  // R_MIPS_CALL* operators (emitted when non-internal functions are called
2916
3.13k
  // in PIC mode) allow symbols to be resolved via lazy binding.
2917
3.13k
  // The lazy binding stub requires GP to point to the GOT.
2918
3.13k
  // Note that we don't need GP to point to the GOT for indirect calls
2919
3.13k
  // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2920
3.13k
  // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2921
3.13k
  // used for the function (that is, Mips linker doesn't generate lazy binding
2922
3.13k
  // stub for a function whose address is taken in the program).
2923
3.13k
  if (IsPICCall && 
!InternalLinkage1.96k
&&
IsCallReloc1.87k
) {
2924
1.69k
    unsigned GPReg = ABI.IsN64() ? 
Mips::GP_64522
:
Mips::GP1.16k
;
2925
1.69k
    EVT Ty = ABI.IsN64() ? 
MVT::i64522
:
MVT::i321.16k
;
2926
1.69k
    RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2927
1.69k
  }
2928
3.13k
2929
3.13k
  // Build a sequence of copy-to-reg nodes chained together with token
2930
3.13k
  // chain and flag operands which copy the outgoing args into registers.
2931
3.13k
  // The InFlag in necessary since all emitted instructions must be
2932
3.13k
  // stuck together.
2933
3.13k
  SDValue InFlag;
2934
3.13k
2935
10.5k
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i7.45k
) {
2936
7.45k
    Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2937
7.45k
                                 RegsToPass[i].second, InFlag);
2938
7.45k
    InFlag = Chain.getValue(1);
2939
7.45k
  }
2940
3.13k
2941
3.13k
  // Add argument registers to the end of the list so that they are
2942
3.13k
  // known live into the call.
2943
10.5k
  for (unsigned i = 0, e = RegsToPass.size(); i != e; 
++i7.45k
)
2944
7.45k
    Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2945
7.45k
                                      RegsToPass[i].second.getValueType()));
2946
3.13k
2947
3.13k
  // Add a register mask operand representing the call-preserved registers.
2948
3.13k
  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2949
3.13k
  const uint32_t *Mask =
2950
3.13k
      TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2951
3.13k
  assert(Mask && "Missing call preserved mask for calling convention");
2952
3.13k
  if (Subtarget.inMips16HardFloat()) {
2953
1.00k
    if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2954
654
      StringRef Sym = G->getGlobal()->getName();
2955
654
      Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2956
654
      if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2957
30
        Mask = MipsRegisterInfo::getMips16RetHelperMask();
2958
30
      }
2959
654
    }
2960
1.00k
  }
2961
3.13k
  Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2962
3.13k
2963
3.13k
  if (InFlag.getNode())
2964
2.65k
    Ops.push_back(InFlag);
2965
3.13k
}
2966
2967
void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
2968
1.39k
                                                       SDNode *Node) const {
2969
1.39k
  switch (MI.getOpcode()) {
2970
1.39k
    default:
2971
22
      return;
2972
1.39k
    case Mips::JALR:
2973
1.37k
    case Mips::JALRPseudo:
2974
1.37k
    case Mips::JALR64:
2975
1.37k
    case Mips::JALR64Pseudo:
2976
1.37k
    case Mips::JALR16_MM:
2977
1.37k
    case Mips::JALRC16_MMR6:
2978
1.37k
    case Mips::TAILCALLREG:
2979
1.37k
    case Mips::TAILCALLREG64:
2980
1.37k
    case Mips::TAILCALLR6REG:
2981
1.37k
    case Mips::TAILCALL64R6REG:
2982
1.37k
    case Mips::TAILCALLREG_MM:
2983
1.37k
    case Mips::TAILCALLREG_MMR6: {
2984
1.37k
      if (!EmitJalrReloc ||
2985
1.37k
          
Subtarget.inMips16Mode()1.06k
||
2986
1.37k
          
!isPositionIndependent()1.06k
||
2987
1.37k
          
Node->getNumOperands() < 11.05k
||
2988
1.37k
          
Node->getOperand(0).getNumOperands() < 21.05k
) {
2989
323
        return;
2990
323
      }
2991
1.05k
      // We are after the callee address, set by LowerCall().
2992
1.05k
      // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
2993
1.05k
      // symbol.
2994
1.05k
      const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
2995
1.05k
      StringRef Sym;
2996
1.05k
      if (const GlobalAddressSDNode *G =
2997
592
              dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
2998
592
        Sym = G->getGlobal()->getName();
2999
592
      }
3000
461
      else if (const ExternalSymbolSDNode *ES =
3001
287
                   dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3002
287
        Sym = ES->getSymbol();
3003
287
      }
3004
1.05k
3005
1.05k
      if (Sym.empty())
3006
174
        return;
3007
879
3008
879
      MachineFunction *MF = MI.getParent()->getParent();
3009
879
      MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym);
3010
879
      MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR));
3011
879
    }
3012
1.39k
  }
3013
1.39k
}
3014
3015
/// LowerCall - functions arguments are copied from virtual regs to
3016
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3017
SDValue
3018
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3019
3.13k
                              SmallVectorImpl<SDValue> &InVals) const {
3020
3.13k
  SelectionDAG &DAG                     = CLI.DAG;
3021
3.13k
  SDLoc DL                              = CLI.DL;
3022
3.13k
  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3023
3.13k
  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
3024
3.13k
  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
3025
3.13k
  SDValue Chain                         = CLI.Chain;
3026
3.13k
  SDValue Callee                        = CLI.Callee;
3027
3.13k
  bool &IsTailCall                      = CLI.IsTailCall;
3028
3.13k
  CallingConv::ID CallConv              = CLI.CallConv;
3029
3.13k
  bool IsVarArg                         = CLI.IsVarArg;
3030
3.13k
3031
3.13k
  MachineFunction &MF = DAG.getMachineFunction();
3032
3.13k
  MachineFrameInfo &MFI = MF.getFrameInfo();
3033
3.13k
  const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3034
3.13k
  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3035
3.13k
  bool IsPIC = isPositionIndependent();
3036
3.13k
3037
3.13k
  // Analyze operands of the call, assigning locations to each operand.
3038
3.13k
  SmallVector<CCValAssign, 16> ArgLocs;
3039
3.13k
  MipsCCState CCInfo(
3040
3.13k
      CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3041
3.13k
      MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
3042
3.13k
3043
3.13k
  const ExternalSymbolSDNode *ES =
3044
3.13k
      dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3045
3.13k
3046
3.13k
  // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3047
3.13k
  // is during the lowering of a call with a byval argument which produces
3048
3.13k
  // a call to memcpy. For the O32 case, this causes the caller to allocate
3049
3.13k
  // stack space for the reserved argument area for the callee, then recursively
3050
3.13k
  // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3051
3.13k
  // ABIs mandate that the callee allocates the reserved argument area. We do
3052
3.13k
  // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3053
3.13k
  //
3054
3.13k
  // If the callee has a byval argument and memcpy is used, we are mandated
3055
3.13k
  // to already have produced a reserved argument area for the callee for O32.
3056
3.13k
  // Therefore, the reserved argument area can be reused for both calls.
3057
3.13k
  //
3058
3.13k
  // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3059
3.13k
  // present, as we have yet to hook that node onto the chain.
3060
3.13k
  //
3061
3.13k
  // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3062
3.13k
  // case. GCC does a similar trick, in that wherever possible, it calculates
3063
3.13k
  // the maximum out going argument area (including the reserved area), and
3064
3.13k
  // preallocates the stack space on entrance to the caller.
3065
3.13k
  //
3066
3.13k
  // FIXME: We should do the same for efficiency and space.
3067
3.13k
3068
3.13k
  // Note: The check on the calling convention below must match
3069
3.13k
  //       MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3070
3.13k
  bool MemcpyInByVal = ES &&
3071
3.13k
                       
StringRef(ES->getSymbol()) == StringRef("memcpy")950
&&
3072
3.13k
                       
CallConv != CallingConv::Fast16
&&
3073
3.13k
                       
Chain.getOpcode() == ISD::CALLSEQ_START16
;
3074
3.13k
3075
3.13k
  // Allocate the reserved argument area. It seems strange to do this from the
3076
3.13k
  // caller side but removing it breaks the frame size calculation.
3077
3.13k
  unsigned ReservedArgArea =
3078
3.13k
      MemcpyInByVal ? 
03
:
ABI.GetCalleeAllocdArgSizeInBytes(CallConv)3.12k
;
3079
3.13k
  CCInfo.AllocateStack(ReservedArgArea, 1);
3080
3.13k
3081
3.13k
  CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3082
3.13k
                             ES ? 
ES->getSymbol()950
:
nullptr2.18k
);
3083
3.13k
3084
3.13k
  // Get a count of how many bytes are to be pushed on the stack.
3085
3.13k
  unsigned NextStackOffset = CCInfo.getNextStackOffset();
3086
3.13k
3087
3.13k
  // Check if it's really possible to do a tail call. Restrict it to functions
3088
3.13k
  // that are part of this compilation unit.
3089
3.13k
  bool InternalLinkage = false;
3090
3.13k
  if (IsTailCall) {
3091
568
    IsTailCall = isEligibleForTailCallOptimization(
3092
568
        CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3093
568
     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3094
480
      InternalLinkage = G->getGlobal()->hasInternalLinkage();
3095
480
      IsTailCall &= (InternalLinkage || 
G->getGlobal()->hasLocalLinkage()392
||
3096
480
                     
G->getGlobal()->hasPrivateLinkage()392
||
3097
480
                     
G->getGlobal()->hasHiddenVisibility()392
||
3098
480
                     
G->getGlobal()->hasProtectedVisibility()368
);
3099
480
     }
3100
568
  }
3101
3.13k
  if (!IsTailCall && 
CLI.CS2.95k
&&
CLI.CS.isMustTailCall()2.00k
)
3102
0
    report_fatal_error("failed to perform tail call elimination on a call "
3103
0
                       "site marked musttail");
3104
3.13k
3105
3.13k
  if (IsTailCall)
3106
177
    ++NumTailCalls;
3107
3.13k
3108
3.13k
  // Chain is the output chain of the last Load/Store or CopyToReg node.
3109
3.13k
  // ByValChain is the output chain of the last Memcpy node created for copying
3110
3.13k
  // byval arguments to the stack.
3111
3.13k
  unsigned StackAlignment = TFL->getStackAlignment();
3112
3.13k
  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3113
3.13k
  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3114
3.13k
3115
3.13k
  if (!(IsTailCall || 
MemcpyInByVal2.95k
))
3116
2.95k
    Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3117
3.13k
3118
3.13k
  SDValue StackPtr =
3119
3.13k
      DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? 
Mips::SP_64845
:
Mips::SP2.28k
,
3120
3.13k
                         getPointerTy(DAG.getDataLayout()));
3121
3.13k
3122
3.13k
  std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3123
3.13k
  SmallVector<SDValue, 8> MemOpChains;
3124
3.13k
3125
3.13k
  CCInfo.rewindByValRegsInfo();
3126
3.13k
3127
3.13k
  // Walk the register/memloc assignments, inserting copies/loads.
3128
9.09k
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i5.96k
) {
3129
5.96k
    SDValue Arg = OutVals[i];
3130
5.96k
    CCValAssign &VA = ArgLocs[i];
3131
5.96k
    MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3132
5.96k
    ISD::ArgFlagsTy Flags = Outs[i].Flags;
3133
5.96k
    bool UseUpperBits = false;
3134
5.96k
3135
5.96k
    // ByVal Arg.
3136
5.96k
    if (Flags.isByVal()) {
3137
61
      unsigned FirstByValReg, LastByValReg;
3138
61
      unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3139
61
      CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3140
61
3141
61
      assert(Flags.getByValSize() &&
3142
61
             "ByVal args of size 0 should have been ignored by front-end.");
3143
61
      assert(ByValIdx < CCInfo.getInRegsParamsCount());
3144
61
      assert(!IsTailCall &&
3145
61
             "Do not tail-call optimize if there is a byval argument.");
3146
61
      passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3147
61
                   FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3148
61
                   VA);
3149
61
      CCInfo.nextInRegsParam();
3150
61
      continue;
3151
61
    }
3152
5.90k
3153
5.90k
    // Promote the value if needed.
3154
5.90k
    switch (VA.getLocInfo()) {
3155
5.90k
    default:
3156
0
      llvm_unreachable("Unknown loc info!");
3157
5.90k
    case CCValAssign::Full:
3158
5.22k
      if (VA.isRegLoc()) {
3159
4.34k
        if ((ValVT == MVT::f32 && 
LocVT == MVT::i32399
) ||
3160
4.34k
            
(4.29k
ValVT == MVT::f644.29k
&&
LocVT == MVT::i64185
) ||
3161
4.34k
            
(4.29k
ValVT == MVT::i644.29k
&&
LocVT == MVT::f64853
))
3162
54
          Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3163
4.29k
        else if (ValVT == MVT::f64 && 
LocVT == MVT::i32185
) {
3164
51
          SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3165
51
                                   Arg, DAG.getConstant(0, DL, MVT::i32));
3166
51
          SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3167
51
                                   Arg, DAG.getConstant(1, DL, MVT::i32));
3168
51
          if (!Subtarget.isLittle())
3169
18
            std::swap(Lo, Hi);
3170
51
          unsigned LocRegLo = VA.getLocReg();
3171
51
          unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3172
51
          RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3173
51
          RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3174
51
          continue;
3175
51
        }
3176
5.17k
      }
3177
5.17k
      break;
3178
5.17k
    case CCValAssign::BCvt:
3179
16
      Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3180
16
      break;
3181
5.17k
    case CCValAssign::SExtUpper:
3182
0
      UseUpperBits = true;
3183
0
      LLVM_FALLTHROUGH;
3184
77
    case CCValAssign::SExt:
3185
77
      Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3186
77
      break;
3187
0
    case CCValAssign::ZExtUpper:
3188
0
      UseUpperBits = true;
3189
0
      LLVM_FALLTHROUGH;
3190
0
    case CCValAssign::ZExt:
3191
0
      Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3192
0
      break;
3193
28
    case CCValAssign::AExtUpper:
3194
28
      UseUpperBits = true;
3195
28
      LLVM_FALLTHROUGH;
3196
580
    case CCValAssign::AExt:
3197
580
      Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3198
580
      break;
3199
5.84k
    }
3200
5.84k
3201
5.84k
    if (UseUpperBits) {
3202
28
      unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3203
28
      unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3204
28
      Arg = DAG.getNode(
3205
28
          ISD::SHL, DL, VA.getLocVT(), Arg,
3206
28
          DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3207
28
    }
3208
5.84k
3209
5.84k
    // Arguments that can be passed on register must be kept at
3210
5.84k
    // RegsToPass vector
3211
5.84k
    if (VA.isRegLoc()) {
3212
4.94k
      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3213
4.94k
      continue;
3214
4.94k
    }
3215
904
3216
904
    // Register can't get to this point...
3217
904
    assert(VA.isMemLoc());
3218
904
3219
904
    // emit ISD::STORE whichs stores the
3220
904
    // parameter value to a stack Location
3221
904
    MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3222
904
                                         Chain, Arg, DL, IsTailCall, DAG));
3223
904
  }
3224
3.13k
3225
3.13k
  // Transform all store nodes into one single node because all store
3226
3.13k
  // nodes are independent of each other.
3227
3.13k
  if (!MemOpChains.empty())
3228
309
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3229
3.13k
3230
3.13k
  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3231
3.13k
  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3232
3.13k
  // node so that legalize doesn't hack it.
3233
3.13k
3234
3.13k
  EVT Ty = Callee.getValueType();
3235
3.13k
  bool GlobalOrExternal = false, IsCallReloc = false;
3236
3.13k
3237
3.13k
  // The long-calls feature is ignored in case of PIC.
3238
3.13k
  // While we do not support -mshared / -mno-shared properly,
3239
3.13k
  // ignore long-calls in case of -mabicalls too.
3240
3.13k
  if (!Subtarget.isABICalls() && 
!IsPIC218
) {
3241
218
    // If the function should be called using "long call",
3242
218
    // get its address into a register to prevent using
3243
218
    // of the `jal` instruction for the direct call.
3244
218
    if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3245
56
      if (Subtarget.useLongCalls())
3246
6
        Callee = Subtarget.hasSym32()
3247
6
                     ? 
getAddrNonPIC(N, SDLoc(N), Ty, DAG)4
3248
6
                     : 
getAddrNonPICSym64(N, SDLoc(N), Ty, DAG)2
;
3249
162
    } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3250
158
      bool UseLongCalls = Subtarget.useLongCalls();
3251
158
      // If the function has long-call/far/near attribute
3252
158
      // it overrides command line switch pased to the backend.
3253
158
      if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3254
158
        if (F->hasFnAttribute("long-call"))
3255
4
          UseLongCalls = true;
3256
154
        else if (F->hasFnAttribute("short-call"))
3257
4
          UseLongCalls = false;
3258
158
      }
3259
158
      if (UseLongCalls)
3260
11
        Callee = Subtarget.hasSym32()
3261
11
                     ? 
getAddrNonPIC(N, SDLoc(N), Ty, DAG)7
3262
11
                     : 
getAddrNonPICSym64(N, SDLoc(N), Ty, DAG)4
;
3263
158
    }
3264
218
  }
3265
3.13k
3266
3.13k
  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3267
1.96k
    if (IsPIC) {
3268
1.22k
      const GlobalValue *Val = G->getGlobal();
3269
1.22k
      InternalLinkage = Val->hasInternalLinkage();
3270
1.22k
3271
1.22k
      if (InternalLinkage)
3272
85
        Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || 
ABI.IsN64()83
);
3273
1.13k
      else if (LargeGOT) {
3274
4
        Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3275
4
                                       MipsII::MO_CALL_LO16, Chain,
3276
4
                                       FuncInfo->callPtrInfo(Val));
3277
4
        IsCallReloc = true;
3278
1.13k
      } else {
3279
1.13k
        Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3280
1.13k
                               FuncInfo->callPtrInfo(Val));
3281
1.13k
        IsCallReloc = true;
3282
1.13k
      }
3283
1.22k
    } else
3284
743
      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3285
743
                                          getPointerTy(DAG.getDataLayout()), 0,
3286
743
                                          MipsII::MO_NO_FLAG);
3287
1.96k
    GlobalOrExternal = true;
3288
1.96k
  }
3289
1.16k
  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3290
944
    const char *Sym = S->getSymbol();
3291
944
3292
944
    if (!IsPIC) // static
3293
391
      Callee = DAG.getTargetExternalSymbol(
3294
391
          Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3295
553
    else if (LargeGOT) {
3296
4
      Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3297
4
                                     MipsII::MO_CALL_LO16, Chain,
3298
4
                                     FuncInfo->callPtrInfo(Sym));
3299
4
      IsCallReloc = true;
3300
549
    } else { // PIC
3301
549
      Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3302
549
                             FuncInfo->callPtrInfo(Sym));
3303
549
      IsCallReloc = true;
3304
549
    }
3305
944
3306
944
    GlobalOrExternal = true;
3307
944
  }
3308
3.13k
3309
3.13k
  SmallVector<SDValue, 8> Ops(1, Chain);
3310
3.13k
  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3311
3.13k
3312
3.13k
  getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3313
3.13k
              IsCallReloc, CLI, Callee, Chain);
3314
3.13k
3315
3.13k
  if (IsTailCall) {
3316
177
    MF.getFrameInfo().setHasTailCall();
3317
177
    return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3318
177
  }
3319
2.95k
3320
2.95k
  Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3321
2.95k
  SDValue InFlag = Chain.getValue(1);
3322
2.95k
3323
2.95k
  // Create the CALLSEQ_END node in the case of where it is not a call to
3324
2.95k
  // memcpy.
3325
2.95k
  if (!(MemcpyInByVal)) {
3326
2.95k
    Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3327
2.95k
                               DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3328
2.95k
    InFlag = Chain.getValue(1);
3329
2.95k
  }
3330
2.95k
3331
2.95k
  // Handle result values, copying them out of physregs into vregs that we
3332
2.95k
  // return.
3333
2.95k
  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3334
2.95k
                         InVals, CLI);
3335
2.95k
}
3336
3337
/// LowerCallResult - Lower the result values of a call into the
3338
/// appropriate copies out of appropriate physical registers.
3339
SDValue MipsTargetLowering::LowerCallResult(
3340
    SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3341
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3342
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3343
2.95k
    TargetLowering::CallLoweringInfo &CLI) const {
3344
2.95k
  // Assign locations to each value returned by this call.
3345
2.95k
  SmallVector<CCValAssign, 16> RVLocs;
3346
2.95k
  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3347
2.95k
                     *DAG.getContext());
3348
2.95k
3349
2.95k
  const ExternalSymbolSDNode *ES =
3350
2.95k
      dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3351
2.95k
  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3352
2.95k
                           ES ? 
ES->getSymbol()950
:
nullptr2.00k
);
3353
2.95k
3354
2.95k
  // Copy all of the result registers out of their specified physreg.
3355
5.39k
  for (unsigned i = 0; i != RVLocs.size(); 
++i2.44k
) {
3356
2.44k
    CCValAssign &VA = RVLocs[i];
3357
2.44k
    assert(VA.isRegLoc() && "Can only return in registers!");
3358
2.44k
3359
2.44k
    SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3360
2.44k
                                     RVLocs[i].getLocVT(), InFlag);
3361
2.44k
    Chain = Val.getValue(1);
3362
2.44k
    InFlag = Val.getValue(2);
3363
2.44k
3364
2.44k
    if (VA.isUpperBitsInLoc()) {
3365
0
      unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3366
0
      unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3367
0
      unsigned Shift =
3368
0
          VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3369
0
      Val = DAG.getNode(
3370
0
          Shift, DL, VA.getLocVT(), Val,
3371
0
          DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3372
0
    }
3373
2.44k
3374
2.44k
    switch (VA.getLocInfo()) {
3375
2.44k
    default:
3376
0
      llvm_unreachable("Unknown loc info!");
3377
2.44k
    case CCValAssign::Full:
3378
2.43k
      break;
3379
2.44k
    case CCValAssign::BCvt:
3380
14
      Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3381
14
      break;
3382
2.44k
    case CCValAssign::AExt:
3383
0
    case CCValAssign::AExtUpper:
3384
0
      Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3385
0
      break;
3386
0
    case CCValAssign::ZExt:
3387
0
    case CCValAssign::ZExtUpper:
3388
0
      Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3389
0
                        DAG.getValueType(VA.getValVT()));
3390
0
      Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3391
0
      break;
3392
0
    case CCValAssign::SExt:
3393
0
    case CCValAssign::SExtUpper:
3394
0
      Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3395
0
                        DAG.getValueType(VA.getValVT()));
3396
0
      Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3397
0
      break;
3398
2.44k
    }
3399
2.44k
3400
2.44k
    InVals.push_back(Val);
3401
2.44k
  }
3402
2.95k
3403
2.95k
  return Chain;
3404
2.95k
}
3405
3406
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3407
                                      EVT ArgVT, const SDLoc &DL,
3408
19.2k
                                      SelectionDAG &DAG) {
3409
19.2k
  MVT LocVT = VA.getLocVT();
3410
19.2k
  EVT ValVT = VA.getValVT();
3411
19.2k
3412
19.2k
  // Shift into the upper bits if necessary.
3413
19.2k
  switch (VA.getLocInfo()) {
3414
19.2k
  default:
3415
19.2k
    break;
3416
19.2k
  case CCValAssign::AExtUpper:
3417
15
  case CCValAssign::SExtUpper:
3418
15
  case CCValAssign::ZExtUpper: {
3419
15
    unsigned ValSizeInBits = ArgVT.getSizeInBits();
3420
15
    unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3421
15
    unsigned Opcode =
3422
15
        VA.getLocInfo() == CCValAssign::ZExtUpper ? 
ISD::SRL0
: ISD::SRA;
3423
15
    Val = DAG.getNode(
3424
15
        Opcode, DL, VA.getLocVT(), Val,
3425
15
        DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3426
15
    break;
3427
19.2k
  }
3428
19.2k
  }
3429
19.2k
3430
19.2k
  // If this is an value smaller than the argument slot size (32-bit for O32,
3431
19.2k
  // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3432
19.2k
  // size. Extract the value and insert any appropriate assertions regarding
3433
19.2k
  // sign/zero extension.
3434
19.2k
  switch (VA.getLocInfo()) {
3435
19.2k
  default:
3436
0
    llvm_unreachable("Unknown loc info!");
3437
19.2k
  case CCValAssign::Full:
3438
16.5k
    break;
3439
19.2k
  case CCValAssign::AExtUpper:
3440
751
  case CCValAssign::AExt:
3441
751
    Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3442
751
    break;
3443
1.82k
  case CCValAssign::SExtUpper:
3444
1.82k
  case CCValAssign::SExt:
3445
1.82k
    Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3446
1.82k
    Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3447
1.82k
    break;
3448
1.82k
  case CCValAssign::ZExtUpper:
3449
112
  case CCValAssign::ZExt:
3450
112
    Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3451
112
    Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3452
112
    break;
3453
112
  case CCValAssign::BCvt:
3454
54
    Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3455
54
    break;
3456
19.2k
  }
3457
19.2k
3458
19.2k
  return Val;
3459
19.2k
}
3460
3461
//===----------------------------------------------------------------------===//
3462
//             Formal Arguments Calling Convention Implementation
3463
//===----------------------------------------------------------------------===//
3464
/// LowerFormalArguments - transform physical registers into virtual registers
3465
/// and generate load operations for arguments places on the stack.
3466
SDValue MipsTargetLowering::LowerFormalArguments(
3467
    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3468
    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3469
12.5k
    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3470
12.5k
  MachineFunction &MF = DAG.getMachineFunction();
3471
12.5k
  MachineFrameInfo &MFI = MF.getFrameInfo();
3472
12.5k
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3473
12.5k
3474
12.5k
  MipsFI->setVarArgsFrameIndex(0);
3475
12.5k
3476
12.5k
  // Used with vargs to acumulate store chains.
3477
12.5k
  std::vector<SDValue> OutChains;
3478
12.5k
3479
12.5k
  // Assign locations to all of the incoming arguments.
3480
12.5k
  SmallVector<CCValAssign, 16> ArgLocs;
3481
12.5k
  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3482
12.5k
                     *DAG.getContext());
3483
12.5k
  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3484
12.5k
  const Function &Func = DAG.getMachineFunction().getFunction();
3485
12.5k
  Function::const_arg_iterator FuncArg = Func.arg_begin();
3486
12.5k
3487
12.5k
  if (Func.hasFnAttribute("interrupt") && 
!Func.arg_empty()12
)
3488
1
    report_fatal_error(
3489
1
        "Functions with the interrupt attribute cannot have arguments!");
3490
12.5k
3491
12.5k
  CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3492
12.5k
  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3493
12.5k
                           CCInfo.getInRegsParamsCount() > 0);
3494
12.5k
3495
12.5k
  unsigned CurArgIdx = 0;
3496
12.5k
  CCInfo.rewindByValRegsInfo();
3497
12.5k
3498
31.8k
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i19.2k
) {
3499
19.2k
    CCValAssign &VA = ArgLocs[i];
3500
19.2k
    if (Ins[i].isOrigArg()) {
3501
19.2k
      std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3502
19.2k
      CurArgIdx = Ins[i].getOrigArgIndex();
3503
19.2k
    }
3504
19.2k
    EVT ValVT = VA.getValVT();
3505
19.2k
    ISD::ArgFlagsTy Flags = Ins[i].Flags;
3506
19.2k
    bool IsRegLoc = VA.isRegLoc();
3507
19.2k
3508
19.2k
    if (Flags.isByVal()) {
3509
19
      assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3510
19
      unsigned FirstByValReg, LastByValReg;
3511
19
      unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3512
19
      CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3513
19
3514
19
      assert(Flags.getByValSize() &&
3515
19
             "ByVal args of size 0 should have been ignored by front-end.");
3516
19
      assert(ByValIdx < CCInfo.getInRegsParamsCount());
3517
19
      copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3518
19
                    FirstByValReg, LastByValReg, VA, CCInfo);
3519
19
      CCInfo.nextInRegsParam();
3520
19
      continue;
3521
19
    }
3522
19.2k
3523
19.2k
    // Arguments stored on registers
3524
19.2k
    if (IsRegLoc) {
3525
17.7k
      MVT RegVT = VA.getLocVT();
3526
17.7k
      unsigned ArgReg = VA.getLocReg();
3527
17.7k
      const TargetRegisterClass *RC = getRegClassFor(RegVT);
3528
17.7k
3529
17.7k
      // Transform the arguments stored on
3530
17.7k
      // physical registers into virtual ones
3531
17.7k
      unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3532
17.7k
      SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3533
17.7k
3534
17.7k
      ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3535
17.7k
3536
17.7k
      // Handle floating point arguments passed in integer registers and
3537
17.7k
      // long double arguments passed in floating point registers.
3538
17.7k
      if ((RegVT == MVT::i32 && 
ValVT == MVT::f329.86k
) ||
3539
17.7k
          
(17.6k
RegVT == MVT::i6417.6k
&&
ValVT == MVT::f645.15k
) ||
3540
17.7k
          
(17.6k
RegVT == MVT::f6417.6k
&&
ValVT == MVT::i641.39k
))
3541
182
        ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3542
17.6k
      else if (ABI.IsO32() && 
RegVT == MVT::i3211.0k
&&
3543
17.6k
               
ValVT == MVT::f649.63k
) {
3544
98
        unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3545
98
                                  getNextIntArgReg(ArgReg), RC);
3546
98
        SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3547
98
        if (!Subtarget.isLittle())
3548
40
          std::swap(ArgValue, ArgValue2);
3549
98
        ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3550
98
                               ArgValue, ArgValue2);
3551
98
      }
3552
17.7k
3553
17.7k
      InVals.push_back(ArgValue);
3554
17.7k
    } else { // VA.isRegLoc()
3555
1.46k
      MVT LocVT = VA.getLocVT();
3556
1.46k
3557
1.46k
      if (ABI.IsO32()) {
3558
1.39k
        // We ought to be able to use LocVT directly but O32 sets it to i32
3559
1.39k
        // when allocating floating point values to integer registers.
3560
1.39k
        // This shouldn't influence how we load the value into registers unless
3561
1.39k
        // we are targeting softfloat.
3562
1.39k
        if (VA.getValVT().isFloatingPoint() && 
!Subtarget.useSoftFloat()213
)
3563
213
          LocVT = VA.getValVT();
3564
1.39k
      }
3565
1.46k
3566
1.46k
      // sanity check
3567
1.46k
      assert(VA.isMemLoc());
3568
1.46k
3569
1.46k
      // The stack pointer offset is relative to the caller stack frame.
3570
1.46k
      int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3571
1.46k
                                     VA.getLocMemOffset(), true);
3572
1.46k
3573
1.46k
      // Create load nodes to retrieve arguments from the stack
3574
1.46k
      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3575
1.46k
      SDValue ArgValue = DAG.getLoad(
3576
1.46k
          LocVT, DL, Chain, FIN,
3577
1.46k
          MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3578
1.46k
      OutChains.push_back(ArgValue.getValue(1));
3579
1.46k
3580
1.46k
      ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3581
1.46k
3582
1.46k
      InVals.push_back(ArgValue);
3583
1.46k
    }
3584
19.2k
  }
3585
12.5k
3586
31.6k
  for (unsigned i = 0, e = ArgLocs.size(); i != e; 
++i19.1k
) {
3587
19.1k
    // The mips ABIs for returning structs by value requires that we copy
3588
19.1k
    // the sret argument into $v0 for the return. Save the argument into
3589
19.1k
    // a virtual register so that we can access it from the return points.
3590
19.1k
    if (Ins[i].Flags.isSRet()) {
3591
47
      unsigned Reg = MipsFI->getSRetReturnReg();
3592
47
      if (!Reg) {
3593
47
        Reg = MF.getRegInfo().createVirtualRegister(
3594
47
            getRegClassFor(ABI.IsN64() ? 
MVT::i646
:
MVT::i3241
));
3595
47
        MipsFI->setSRetReturnReg(Reg);
3596
47
      }
3597
47
      SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3598
47
      Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3599
47
      break;
3600
47
    }
3601
19.1k
  }
3602
12.5k
3603
12.5k
  if (IsVarArg)
3604
113
    writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3605
12.5k
3606
12.5k
  // All stores are grouped in one node to allow the matching between
3607
12.5k
  // the size of Ins and InVals. This only happens when on varg functions
3608
12.5k
  if (!OutChains.empty()) {
3609
614
    OutChains.push_back(Chain);
3610
614
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3611
614
  }
3612
12.5k
3613
12.5k
  return Chain;
3614
12.5k
}
3615
3616
//===----------------------------------------------------------------------===//
3617
//               Return Value Calling Convention Implementation
3618
//===----------------------------------------------------------------------===//
3619
3620
bool
3621
MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3622
                                   MachineFunction &MF, bool IsVarArg,
3623
                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
3624
16.0k
                                   LLVMContext &Context) const {
3625
16.0k
  SmallVector<CCValAssign, 16> RVLocs;
3626
16.0k
  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3627
16.0k
  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3628
16.0k
}
3629
3630
bool
3631
3.34k
MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3632
3.34k
  if ((ABI.IsN32() || 
ABI.IsN64()3.18k
) &&
Type == MVT::i321.20k
)
3633
185
      return true;
3634
3.15k
3635
3.15k
  return IsSigned;
3636
3.15k
}
3637
3638
SDValue
3639
MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3640
                                         const SDLoc &DL,
3641
11
                                         SelectionDAG &DAG) const {
3642
11
  MachineFunction &MF = DAG.getMachineFunction();
3643
11
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3644
11
3645
11
  MipsFI->setISR();
3646
11
3647
11
  return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3648
11
}
3649
3650
SDValue
3651
MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3652
                                bool IsVarArg,
3653
                                const SmallVectorImpl<ISD::OutputArg> &Outs,
3654
                                const SmallVectorImpl<SDValue> &OutVals,
3655
12.4k
                                const SDLoc &DL, SelectionDAG &DAG) const {
3656
12.4k
  // CCValAssign - represent the assignment of
3657
12.4k
  // the return value to a location
3658
12.4k
  SmallVector<CCValAssign, 16> RVLocs;
3659
12.4k
  MachineFunction &MF = DAG.getMachineFunction();
3660
12.4k
3661
12.4k
  // CCState - Info about the registers and stack slot.
3662
12.4k
  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3663
12.4k
3664
12.4k
  // Analyze return values.
3665
12.4k
  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3666
12.4k
3667
12.4k
  SDValue Flag;
3668
12.4k
  SmallVector<SDValue, 4> RetOps(1, Chain);
3669
12.4k
3670
12.4k
  // Copy the result values into the output registers.
3671
21.8k
  for (unsigned i = 0; i != RVLocs.size(); 
++i9.47k
) {
3672
9.47k
    SDValue Val = OutVals[i];
3673
9.47k
    CCValAssign &VA = RVLocs[i];
3674
9.47k
    assert(VA.isRegLoc() && "Can only return in registers!");
3675
9.47k
    bool UseUpperBits = false;
3676
9.47k
3677
9.47k
    switch (VA.getLocInfo()) {
3678
9.47k
    default:
3679
0
      llvm_unreachable("Unknown loc info!");
3680
9.47k
    case CCValAssign::Full:
3681
9.43k
      break;
3682
9.47k
    case CCValAssign::BCvt:
3683
20
      Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3684
20
      break;
3685
9.47k
    case CCValAssign::AExtUpper:
3686
6
      UseUpperBits = true;
3687
6
      LLVM_FALLTHROUGH;
3688
12
    case CCValAssign::AExt:
3689
12
      Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3690
12
      break;
3691
6
    case CCValAssign::ZExtUpper:
3692
0
      UseUpperBits = true;
3693
0
      LLVM_FALLTHROUGH;
3694
0
    case CCValAssign::ZExt:
3695
0
      Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3696
0
      break;
3697
0
    case CCValAssign::SExtUpper:
3698
0
      UseUpperBits = true;
3699
0
      LLVM_FALLTHROUGH;
3700
0
    case CCValAssign::SExt:
3701
0
      Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3702
0
      break;
3703
9.47k
    }
3704
9.47k
3705
9.47k
    if (UseUpperBits) {
3706
6
      unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3707
6
      unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3708
6
      Val = DAG.getNode(
3709
6
          ISD::SHL, DL, VA.getLocVT(), Val,
3710
6
          DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3711
6
    }
3712
9.47k
3713
9.47k
    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3714
9.47k
3715
9.47k
    // Guarantee that all emitted copies are stuck together with flags.
3716
9.47k
    Flag = Chain.getValue(1);
3717
9.47k
    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3718
9.47k
  }
3719
12.4k
3720
12.4k
  // The mips ABIs for returning structs by value requires that we copy
3721
12.4k
  // the sret argument into $v0 for the return. We saved the argument into
3722
12.4k
  // a virtual register in the entry block, so now we copy the value out
3723
12.4k
  // and into $v0.
3724
12.4k
  if (MF.getFunction().hasStructRetAttr()) {
3725
9
    MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3726
9
    unsigned Reg = MipsFI->getSRetReturnReg();
3727
9
3728
9
    if (!Reg)
3729
9
      
llvm_unreachable0
("sret virtual register not created in the entry block");
3730
9
    SDValue Val =
3731
9
        DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3732
9
    unsigned V0 = ABI.IsN64() ? 
Mips::V0_644
:
Mips::V05
;
3733
9
3734
9
    Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3735
9
    Flag = Chain.getValue(1);
3736
9
    RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3737
9
  }
3738
12.4k
3739
12.4k
  RetOps[0] = Chain;  // Update chain.
3740
12.4k
3741
12.4k
  // Add the flag if we have it.
3742
12.4k
  if (Flag.getNode())
3743
7.60k
    RetOps.push_back(Flag);
3744
12.4k
3745
12.4k
  // ISRs must use "eret".
3746
12.4k
  if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3747
11
    return LowerInterruptReturn(RetOps, DL, DAG);
3748
12.3k
3749
12.3k
  // Standard return on Mips is a "jr $ra"
3750
12.3k
  return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3751
12.3k
}
3752
3753
//===----------------------------------------------------------------------===//
3754
//                           Mips Inline Assembly Support
3755
//===----------------------------------------------------------------------===//
3756
3757
/// getConstraintType - Given a constraint letter, return the type of
3758
/// constraint it is for this target.
3759
MipsTargetLowering::ConstraintType
3760
8.81k
MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3761
8.81k
  // Mips specific constraints
3762
8.81k
  // GCC config/mips/constraints.md
3763
8.81k
  //
3764
8.81k
  // 'd' : An address register. Equivalent to r
3765
8.81k
  //       unless generating MIPS16 code.
3766
8.81k
  // 'y' : Equivalent to r; retained for
3767
8.81k
  //       backwards compatibility.
3768
8.81k
  // 'c' : A register suitable for use in an indirect
3769
8.81k
  //       jump. This will always be $25 for -mabicalls.
3770
8.81k
  // 'l' : The lo register. 1 word storage.
3771
8.81k
  // 'x' : The hilo register pair. Double word storage.
3772
8.81k
  if (Constraint.size() == 1) {
3773
1.14k
    switch (Constraint[0]) {
3774
1.14k
      
default : break1.01k
;
3775
1.14k
      case 'd':
3776
111
      case 'y':
3777
111
      case 'f':
3778
111
      case 'c':
3779
111
      case 'l':
3780
111
      case 'x':
3781
111
        return C_RegisterClass;
3782
111
      case 'R':
3783
12
        return C_Memory;
3784
8.69k
    }
3785
8.69k
  }
3786
8.69k
3787
8.69k
  if (Constraint == "ZC")
3788
113
    return C_Memory;
3789
8.58k
3790
8.58k
  return TargetLowering::getConstraintType(Constraint);
3791
8.58k
}
3792
3793
/// Examine constraint type and operand type and determine a weight value.
3794
/// This object must already have been set up with the operand type
3795
/// and the current alternative constraint selected.
3796
TargetLowering::ConstraintWeight
3797
MipsTargetLowering::getSingleConstraintMatchWeight(
3798
0
    AsmOperandInfo &info, const char *constraint) const {
3799
0
  ConstraintWeight weight = CW_Invalid;
3800
0
  Value *CallOperandVal = info.CallOperandVal;
3801
0
    // If we don't have a value, we can't do a match,
3802
0
    // but allow it at the lowest weight.
3803
0
  if (!CallOperandVal)
3804
0
    return CW_Default;
3805
0
  Type *type = CallOperandVal->getType();
3806
0
  // Look at the constraint type.
3807
0
  switch (*constraint) {
3808
0
  default:
3809
0
    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3810
0
    break;
3811
0
  case 'd':
3812
0
  case 'y':
3813
0
    if (type->isIntegerTy())
3814
0
      weight = CW_Register;
3815
0
    break;
3816
0
  case 'f': // FPU or MSA register
3817
0
    if (Subtarget.hasMSA() && type->isVectorTy() &&
3818
0
        cast<VectorType>(type)->getBitWidth() == 128)
3819
0
      weight = CW_Register;
3820
0
    else if (type->isFloatTy())
3821
0
      weight = CW_Register;
3822
0
    break;
3823
0
  case 'c': // $25 for indirect jumps
3824
0
  case 'l': // lo register
3825
0
  case 'x': // hilo register pair
3826
0
    if (type->isIntegerTy())
3827
0
      weight = CW_SpecificReg;
3828
0
    break;
3829
0
  case 'I': // signed 16 bit immediate
3830
0
  case 'J': // integer zero
3831
0
  case 'K': // unsigned 16 bit immediate
3832
0
  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3833
0
  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3834
0
  case 'O': // signed 15 bit immediate (+- 16383)
3835
0
  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3836
0
    if (isa<ConstantInt>(CallOperandVal))
3837
0
      weight = CW_Constant;
3838
0
    break;
3839
0
  case 'R':
3840
0
    weight = CW_Memory;
3841
0
    break;
3842
0
  }
3843
0
  return weight;
3844
0
}
3845
3846
/// This is a helper function to parse a physical register string and split it
3847
/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3848
/// that is returned indicates whether parsing was successful. The second flag
3849
/// is true if the numeric part exists.
3850
static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3851
3.24k
                                              unsigned long long &Reg) {
3852
3.24k
  if (C.front() != '{' || 
C.back() != '}'3.16k
)
3853
79
    return std::make_pair(false, false);
3854
3.16k
3855
3.16k
  // Search for the first numeric character.
3856
3.16k
  StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3857
3.16k
  I = std::find_if(B, E, isdigit);
3858
3.16k
3859
3.16k
  Prefix = StringRef(B, I - B);
3860
3.16k
3861
3.16k
  // The second flag is set to false if no numeric characters were found.
3862
3.16k
  if (I == E)
3863
26
    return std::make_pair(true, false);
3864
3.13k
3865
3.13k
  // Parse the numeric characters.
3866
3.13k
  return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3867
3.13k
                        true);
3868
3.13k
}
3869
3870
EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
3871
2.89k
                                            ISD::NodeType) const {
3872
2.89k
  bool Cond = !Subtarget.isABI_O32() && 
VT.getSizeInBits() == 321.35k
;
3873
2.89k
  EVT MinVT = getRegisterType(Context, Cond ? 
MVT::i64229
:
MVT::i322.66k
);
3874
2.89k
  return VT.bitsLT(MinVT) ? 
MinVT1.72k
:
VT1.16k
;
3875
2.89k
}
3876
3877
std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3878
3.24k
parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3879
3.24k
  const TargetRegisterInfo *TRI =
3880
3.24k
      Subtarget.getRegisterInfo();
3881
3.24k
  const TargetRegisterClass *RC;
3882
3.24k
  StringRef Prefix;
3883
3.24k
  unsigned long long Reg;
3884
3.24k
3885
3.24k
  std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3886
3.24k
3887
3.24k
  if (!R.first)
3888
79
    return std::make_pair(0U, nullptr);
3889
3.16k
3890
3.16k
  if ((Prefix == "hi" || 
Prefix == "lo"3.16k
)) { // Parse hi/lo.
3891
4
    // No numeric characters follow "hi" or "lo".
3892
4
    if (R.second)
3893
0
      return std::make_pair(0U, nullptr);
3894
4
3895
4
    RC = TRI->getRegClass(Prefix == "hi" ?
3896
2
                          Mips::HI32RegClassID : Mips::LO32RegClassID);
3897
4
    return std::make_pair(*(RC->begin()), RC);
3898
3.16k
  } else if (Prefix.startswith("$msa")) {
3899
0
    // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3900
0
3901
0
    // No numeric characters follow the name.
3902
0
    if (R.second)
3903
0
      return std::make_pair(0U, nullptr);
3904
0
3905
0
    Reg = StringSwitch<unsigned long long>(Prefix)
3906
0
              .Case("$msair", Mips::MSAIR)
3907
0
              .Case("$msacsr", Mips::MSACSR)
3908
0
              .Case("$msaaccess", Mips::MSAAccess)
3909
0
              .Case("$msasave", Mips::MSASave)
3910
0
              .Case("$msamodify", Mips::MSAModify)
3911
0
              .Case("$msarequest", Mips::MSARequest)
3912
0
              .Case("$msamap", Mips::MSAMap)
3913
0
              .Case("$msaunmap", Mips::MSAUnmap)
3914
0
              .Default(0);
3915
0
3916
0
    if (!Reg)
3917
0
      return std::make_pair(0U, nullptr);
3918
0
3919
0
    RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3920
0
    return std::make_pair(Reg, RC);
3921
0
  }
3922
3.16k
3923
3.16k
  if (!R.second)
3924
22
    return std::make_pair(0U, nullptr);
3925
3.13k
3926
3.13k
  if (Prefix == "$f") { // Parse $f0-$f31.
3927
2.19k
    // If the size of FP registers is 64-bit or Reg is an even number, select
3928
2.19k
    // the 64-bit register class. Otherwise, select the 32-bit register class.
3929
2.19k
    if (VT == MVT::Other)
3930
2.18k
      VT = (Subtarget.isFP64bit() || 
!(Reg % 2)758
) ?
MVT::f641.80k
:
MVT::f32380
;
3931
2.19k
3932
2.19k
    RC = getRegClassFor(VT);
3933
2.19k
3934
2.19k
    if (RC == &Mips::AFGR64RegClass) {
3935
378
      assert(Reg % 2 == 0);
3936
378
      Reg >>= 1;
3937
378
    }
3938
2.19k
  } else 
if (947
Prefix == "$fcc"947
) // Parse $fcc0-$fcc7.
3939
0
    RC = TRI->getRegClass(Mips::FCCRegClassID);
3940
947
  else if (Prefix == "$w") { // Parse $w0-$w31.
3941
10
    RC = getRegClassFor((VT == MVT::Other) ? 
MVT::v16i82
:
VT8
);
3942
937
  } else { // Parse $0-$31.
3943
937
    assert(Prefix == "$");
3944
937
    RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : 
VT0
);
3945
937
  }
3946
3.13k
3947
3.13k
  assert(Reg < RC->getNumRegs());
3948
3.13k
  return std::make_pair(*(RC->begin() + Reg), RC);
3949
3.13k
}
3950
3951
/// Given a register class constraint, like 'r', if this corresponds directly
3952
/// to an LLVM register class, return a register of 0 and the register class
3953
/// pointer.
3954
std::pair<unsigned, const TargetRegisterClass *>
3955
MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3956
                                                 StringRef Constraint,
3957
3.49k
                                                 MVT VT) const {
3958
3.49k
  if (Constraint.size() == 1) {
3959
331
    switch (Constraint[0]) {
3960
331
    case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3961
224
    case 'y': // Same as 'r'. Exists for compatibility.
3962
224
    case 'r':
3963
224
      if (VT == MVT::i32 || 
VT == MVT::i1640
||
VT == MVT::i826
) {
3964
202
        if (Subtarget.inMips16Mode())
3965
0
          return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3966
202
        return std::make_pair(0U, &Mips::GPR32RegClass);
3967
202
      }
3968
22
      if (VT == MVT::i64 && !Subtarget.isGP64bit())
3969
20
        return std::make_pair(0U, &Mips::GPR32RegClass);
3970
2
      if (VT == MVT::i64 && Subtarget.isGP64bit())
3971
2
        return std::make_pair(0U, &Mips::GPR64RegClass);
3972
0
      // This will generate an error message
3973
0
      return std::make_pair(0U, nullptr);
3974
17
    case 'f': // FPU or MSA register
3975
17
      if (VT == MVT::v16i8)
3976
0
        return std::make_pair(0U, &Mips::MSA128BRegClass);
3977
17
      else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3978
0
        return std::make_pair(0U, &Mips::MSA128HRegClass);
3979
17
      else if (VT == MVT::v4i32 || 
VT == MVT::v4f3212
)
3980
5
        return std::make_pair(0U, &Mips::MSA128WRegClass);
3981
12
      else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3982
0
        return std::make_pair(0U, &Mips::MSA128DRegClass);
3983
12
      else if (VT == MVT::f32)
3984
6
        return std::make_pair(0U, &Mips::FGR32RegClass);
3985
6
      else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3986
6
        if (Subtarget.isFP64bit())
3987
3
          return std::make_pair(0U, &Mips::FGR64RegClass);
3988
3
        return std::make_pair(0U, &Mips::AFGR64RegClass);
3989
3
      }
3990
0
      break;
3991
6
    case 'c': // register suitable for indirect jump
3992
6
      if (VT == MVT::i32)
3993
5
        return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3994
1
      if (VT == MVT::i64)
3995
0
        return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3996
1
      // This will generate an error message
3997
1
      return std::make_pair(0U, nullptr);
3998
5
    case 'l': // use the `lo` register to store values
3999
5
              // that are no bigger than a word
4000
5
      if (VT == MVT::i32 || 
VT == MVT::i163
||
VT == MVT::i80
)
4001
5
        return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
4002
0
      return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4003
0
    case 'x': // use the concatenated `hi` and `lo` registers
4004
0
              // to store doubleword values
4005
0
      // Fixme: Not triggering the use of both hi and low
4006
0
      // This will generate an error message
4007
0
      return std::make_pair(0U, nullptr);
4008
3.24k
    }
4009
3.24k
  }
4010
3.24k
4011
3.24k
  std::pair<unsigned, const TargetRegisterClass *> R;
4012
3.24k
  R = parseRegForInlineAsmConstraint(Constraint, VT);
4013
3.24k
4014
3.24k
  if (R.second)
4015
3.14k
    return R;
4016
101
4017
101
  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4018
101
}
4019
4020
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4021
/// vector.  If it is invalid, don't add anything to Ops.
4022
void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4023
                                                     std::string &Constraint,
4024
                                                     std::vector<SDValue>&Ops,
4025
91
                                                     SelectionDAG &DAG) const {
4026
91
  SDLoc DL(Op);
4027
91
  SDValue Result;
4028
91
4029
91
  // Only support length 1 constraints for now.
4030
91
  if (Constraint.length() > 1) 
return0
;
4031
91
4032
91
  char ConstraintLetter = Constraint[0];
4033
91
  switch (ConstraintLetter) {
4034
91
  
default: break17
; // This will fall through to the generic implementation
4035
91
  case 'I': // Signed 16 bit constant
4036
44
    // If this fails, the parent routine will give an error
4037
44
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4038
44
      EVT Type = Op.getValueType();
4039
44
      int64_t Val = C->getSExtValue();
4040
44
      if (isInt<16>(Val)) {
4041
43
        Result = DAG.getTargetConstant(Val, DL, Type);
4042
43
        break;
4043
43
      }
4044
1
    }
4045
1
    return;
4046
15
  case 'J': // integer zero
4047
15
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4048
15
      EVT Type = Op.getValueType();
4049
15
      int64_t Val = C->getZExtValue();
4050
15
      if (Val == 0) {
4051
10
        Result = DAG.getTargetConstant(0, DL, Type);
4052
10
        break;
4053
10
      }
4054
5
    }
4055
5
    return;
4056
5
  case 'K': // unsigned 16 bit immediate
4057
3
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4058
3
      EVT Type = Op.getValueType();
4059
3
      uint64_t Val = (uint64_t)C->getZExtValue();
4060
3
      if (isUInt<16>(Val)) {
4061
2
        Result = DAG.getTargetConstant(Val, DL, Type);
4062
2
        break;
4063
2
      }
4064
1
    }
4065
1
    return;
4066
3
  case 'L': // signed 32 bit immediate where lower 16 bits are 0
4067
3
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4068
3
      EVT Type = Op.getValueType();
4069
3
      int64_t Val = C->getSExtValue();
4070
3
      if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4071
2
        Result = DAG.getTargetConstant(Val, DL, Type);
4072
2
        break;
4073
2
      }
4074
1
    }
4075
1
    return;
4076
3
  case 'N': // immediate in the range of -65535 to -1 (inclusive)
4077
3
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4078
3
      EVT Type = Op.getValueType();
4079
3
      int64_t Val = C->getSExtValue();
4080
3
      if ((Val >= -65535) && (Val <= -1)) {
4081
2
        Result = DAG.getTargetConstant(Val, DL, Type);
4082
2
        break;
4083
2
      }
4084
1
    }
4085
1
    return;
4086
3
  case 'O': // signed 15 bit immediate
4087
3
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4088
3
      EVT Type = Op.getValueType();
4089
3
      int64_t Val = C->getSExtValue();
4090
3
      if ((isInt<15>(Val))) {
4091
2
        Result = DAG.getTargetConstant(Val, DL, Type);
4092
2
        break;
4093
2
      }
4094
1
    }
4095
1
    return;
4096
3
  case 'P': // immediate in the range of 1 to 65535 (inclusive)
4097
3
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4098
3
      EVT Type = Op.getValueType();
4099
3
      int64_t Val = C->getSExtValue();
4100
3
      if ((Val <= 65535) && 
(Val >= 1)2
) {
4101
2
        Result = DAG.getTargetConstant(Val, DL, Type);
4102
2
        break;
4103
2
      }
4104
1
    }
4105
1
    return;
4106
80
  }
4107
80
4108
80
  if (Result.getNode()) {
4109
63
    Ops.push_back(Result);
4110
63
    return;
4111
63
  }
4112
17
4113
17
  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4114
17
}
4115
4116
bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4117
                                               const AddrMode &AM, Type *Ty,
4118
102k
                                               unsigned AS, Instruction *I) const {
4119
102k
  // No global is ever allowed as a base.
4120
102k
  if (AM.BaseGV)
4121
9.62k
    return false;
4122
92.9k
4123
92.9k
  switch (AM.Scale) {
4124
92.9k
  case 0: // "r+i" or just "i", depending on HasBaseReg.
4125
92.5k
    break;
4126
92.9k
  case 1:
4127
122
    if (!AM.HasBaseReg) // allow "r+i".
4128
0
      break;
4129
122
    return false; // disallow "r+r" or "r+r+i".
4130
223
  default:
4131
223
    return false;
4132
92.5k
  }
4133
92.5k
4134
92.5k
  return true;
4135
92.5k
}
4136
4137
bool
4138
4.59k
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4139
4.59k
  // The Mips target isn't yet aware of offsets.
4140
4.59k
  return false;
4141
4.59k
}
4142
4143
EVT MipsTargetLowering::getOptimalMemOpType(
4144
    uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
4145
    bool ZeroMemset, bool MemcpyStrSrc,
4146
65
    const AttributeList &FuncAttributes) const {
4147
65
  if (Subtarget.hasMips64())
4148
36
    return MVT::i64;
4149
29
4150
29
  return MVT::i32;
4151
29
}
4152
4153
bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
4154
910
                                      bool ForCodeSize) const {
4155
910
  if (VT != MVT::f32 && 
VT != MVT::f64459
)
4156
0
    return false;
4157
910
  if (Imm.isNegZero())
4158
72
    return false;
4159
838
  return Imm.isZero();
4160
838
}
4161
4162
31
unsigned MipsTargetLowering::getJumpTableEncoding() const {
4163
31
4164
31
  // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4165
31
  if (ABI.IsN64() && 
isPositionIndependent()15
)
4166
10
    return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4167
21
4168
21
  return TargetLowering::getJumpTableEncoding();
4169
21
}
4170
4171
3.18k
bool MipsTargetLowering::useSoftFloat() const {
4172
3.18k
  return Subtarget.useSoftFloat();
4173
3.18k
}
4174
4175
void MipsTargetLowering::copyByValRegs(
4176
    SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4177
    SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4178
    SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4179
    unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4180
19
    MipsCCState &State) const {
4181
19
  MachineFunction &MF = DAG.getMachineFunction();
4182
19
  MachineFrameInfo &MFI = MF.getFrameInfo();
4183
19
  unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4184
19
  unsigned NumRegs = LastReg - FirstReg;
4185
19
  unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4186
19
  unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4187
19
  int FrameObjOffset;
4188
19
  ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4189
19
4190
19
  if (RegAreaSize)
4191
19
    FrameObjOffset =
4192
19
        (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4193
19
        (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4194
0
  else
4195
0
    FrameObjOffset = VA.getLocMemOffset();
4196
19
4197
19
  // Create frame object.
4198
19
  EVT PtrTy = getPointerTy(DAG.getDataLayout());
4199
19
  // Make the fixed object stored to mutable so that the load instructions
4200
19
  // referencing it have their memory dependencies added.
4201
19
  // Set the frame object as isAliased which clears the underlying objects
4202
19
  // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4203
19
  // stores as dependencies for loads referencing this fixed object.
4204
19
  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4205
19
  SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4206
19
  InVals.push_back(FIN);
4207
19
4208
19
  if (!NumRegs)
4209
0
    return;
4210
19
4211
19
  // Copy arg registers.
4212
19
  MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4213
19
  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4214
19
4215
56
  for (unsigned I = 0; I < NumRegs; 
++I37
) {
4216
37
    unsigned ArgReg = ByValArgRegs[FirstReg + I];
4217
37
    unsigned VReg = addLiveIn(MF, ArgReg, RC);
4218
37
    unsigned Offset = I * GPRSizeInBytes;
4219
37
    SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4220
37
                                   DAG.getConstant(Offset, DL, PtrTy));
4221
37
    SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4222
37
                                 StorePtr, MachinePointerInfo(FuncArg, Offset));
4223
37
    OutChains.push_back(Store);
4224
37
  }
4225
19
}
4226
4227
// Copy byVal arg to registers and stack.
4228
void MipsTargetLowering::passByValArg(
4229
    SDValue Chain, const SDLoc &DL,
4230
    std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4231
    SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4232
    MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4233
    unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4234
61
    const CCValAssign &VA) const {
4235
61
  unsigned ByValSizeInBytes = Flags.getByValSize();
4236
61
  unsigned OffsetInBytes = 0; // From beginning of struct
4237
61
  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4238
61
  unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4239
61
  EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4240
61
      RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4241
61
  unsigned NumRegs = LastReg - FirstReg;
4242
61
4243
61
  if (NumRegs) {
4244
60
    ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4245
60
    bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4246
60
    unsigned I = 0;
4247
60
4248
60
    // Copy words to registers.
4249
148
    for (; I < NumRegs - LeftoverBytes; 
++I, OffsetInBytes += RegSizeInBytes88
) {
4250
88
      SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4251
88
                                    DAG.getConstant(OffsetInBytes, DL, PtrTy));
4252
88
      SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4253
88
                                    MachinePointerInfo(), Alignment);
4254
88
      MemOpChains.push_back(LoadVal.getValue(1));
4255
88
      unsigned ArgReg = ArgRegs[FirstReg + I];
4256
88
      RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4257
88
    }
4258
60
4259
60
    // Return if the struct has been fully copied.
4260
60
    if (ByValSizeInBytes == OffsetInBytes)
4261
28
      return;
4262
32
4263
32
    // Copy the remainder of the byval argument with sub-word loads and shifts.
4264
32
    if (LeftoverBytes) {
4265
27
      SDValue Val;
4266
27
4267
27
      for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4268
83
           OffsetInBytes < ByValSizeInBytes; 
LoadSizeInBytes /= 256
) {
4269
56
        unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4270
56
4271
56
        if (RemainingSizeInBytes < LoadSizeInBytes)
4272
1
          continue;
4273
55
4274
55
        // Load subword.
4275
55
        SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4276
55
                                      DAG.getConstant(OffsetInBytes, DL,
4277
55
                                                      PtrTy));
4278
55
        SDValue LoadVal = DAG.getExtLoad(
4279
55
            ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4280
55
            MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4281
55
        MemOpChains.push_back(LoadVal.getValue(1));
4282
55
4283
55
        // Shift the loaded value.
4284
55
        unsigned Shamt;
4285
55
4286
55
        if (isLittle)
4287
28
          Shamt = TotalBytesLoaded * 8;
4288
27
        else
4289
27
          Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4290
55
4291
55
        SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4292
55
                                    DAG.getConstant(Shamt, DL, MVT::i32));
4293
55
4294
55
        if (Val.getNode())
4295
28
          Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4296
27
        else
4297
27
          Val = Shift;
4298
55
4299
55
        OffsetInBytes += LoadSizeInBytes;
4300
55
        TotalBytesLoaded += LoadSizeInBytes;
4301
55
        Alignment = std::min(Alignment, LoadSizeInBytes);
4302
55
      }
4303
27
4304
27
      unsigned ArgReg = ArgRegs[FirstReg + I];
4305
27
      RegsToPass.push_back(std::make_pair(ArgReg, Val));
4306
27
      return;
4307
27
    }
4308
6
  }
4309
6
4310
6
  // Copy remainder of byval arg to it with memcpy.
4311
6
  unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4312
6
  SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4313
6
                            DAG.getConstant(OffsetInBytes, DL, PtrTy));
4314
6
  SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4315
6
                            DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4316
6
  Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4317
6
                        DAG.getConstant(MemCpySize, DL, PtrTy),
4318
6
                        Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4319
6
                        /*isTailCall=*/false,
4320
6
                        MachinePointerInfo(), MachinePointerInfo());
4321
6
  MemOpChains.push_back(Chain);
4322
6
}
4323
4324
void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4325
                                         SDValue Chain, const SDLoc &DL,
4326
                                         SelectionDAG &DAG,
4327
113
                                         CCState &State) const {
4328
113
  ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4329
113
  unsigned Idx = State.getFirstUnallocated(ArgRegs);
4330
113
  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4331
113
  MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4332
113
  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4333
113
  MachineFunction &MF = DAG.getMachineFunction();
4334
113
  MachineFrameInfo &MFI = MF.getFrameInfo();
4335
113
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4336
113
4337
113
  // Offset of the first variable argument from stack pointer.
4338
113
  int VaArgOffset;
4339
113
4340
113
  if (ArgRegs.size() == Idx)
4341
20
    VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4342
93
  else {
4343
93
    VaArgOffset =
4344
93
        (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4345
93
        (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4346
93
  }
4347
113
4348
113
  // Record the frame index of the first variable argument
4349
113
  // which is a value necessary to VASTART.
4350
113
  int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4351
113
  MipsFI->setVarArgsFrameIndex(FI);
4352
113
4353
113
  // Copy the integer registers that have not been used for argument passing
4354
113
  // to the argument register save area. For O32, the save area is allocated
4355
113
  // in the caller's stack frame, while for N32/64, it is allocated in the
4356
113
  // callee's stack frame.
4357
587
  for (unsigned I = Idx; I < ArgRegs.size();
4358
474
       ++I, VaArgOffset += RegSizeInBytes) {
4359
474
    unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4360
474
    SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4361
474
    FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4362
474
    SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4363
474
    SDValue Store =
4364
474
        DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4365
474
    cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4366
474
        (Value *)nullptr);
4367
474
    OutChains.push_back(Store);
4368
474
  }
4369
113
}
4370
4371
void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4372
80
                                     unsigned Align) const {
4373
80
  const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4374
80
4375
80
  assert(Size && "Byval argument's size shouldn't be 0.");
4376
80
4377
80
  Align = std::min(Align, TFL->getStackAlignment());
4378
80
4379
80
  unsigned FirstReg = 0;
4380
80
  unsigned NumRegs = 0;
4381
80
4382
80
  if (State->getCallingConv() != CallingConv::Fast) {
4383
79
    unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4384
79
    ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4385
79
    // FIXME: The O32 case actually describes no shadow registers.
4386
79
    const MCPhysReg *ShadowRegs =
4387
79
        ABI.IsO32() ? 
IntArgRegs.data()57
:
Mips64DPRegs22
;
4388
79
4389
79
    // We used to check the size as well but we can't do that anymore since
4390
79
    // CCState::HandleByVal() rounds up the size after calling this function.
4391
79
    assert(!(Align % RegSizeInBytes) &&
4392
79
           "Byval argument's alignment should be a multiple of"
4393
79
           "RegSizeInBytes.");
4394
79
4395
79
    FirstReg = State->getFirstUnallocated(IntArgRegs);
4396
79
4397
79
    // If Align > RegSizeInBytes, the first arg register must be even.
4398
79
    // FIXME: This condition happens to do the right thing but it's not the
4399
79
    //        right way to test it. We want to check that the stack frame offset
4400
79
    //        of the register is aligned.
4401
79
    if ((Align > RegSizeInBytes) && 
(FirstReg % 2)4
) {
4402
2
      State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4403
2
      ++FirstReg;
4404
2
    }
4405
79
4406
79
    // Mark the registers allocated.
4407
79
    Size = alignTo(Size, RegSizeInBytes);
4408
231
    for (unsigned I = FirstReg; Size > 0 && 
(I < IntArgRegs.size())161
;
4409
152
         Size -= RegSizeInBytes, ++I, ++NumRegs)
4410
152
      State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4411
79
  }
4412
80
4413
80
  State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4414
80
}
4415
4416
MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4417
                                                        MachineBasicBlock *BB,
4418
                                                        bool isFPCmp,
4419
82
                                                        unsigned Opc) const {
4420
82
  assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4421
82
         "Subtarget already supports SELECT nodes with the use of"
4422
82
         "conditional-move instructions.");
4423
82
4424
82
  const TargetInstrInfo *TII =
4425
82
      Subtarget.getInstrInfo();
4426
82
  DebugLoc DL = MI.getDebugLoc();
4427
82
4428
82
  // To "insert" a SELECT instruction, we actually have to insert the
4429
82
  // diamond control-flow pattern.  The incoming instruction knows the
4430
82
  // destination vreg to set, the condition code register to branch on, the
4431
82
  // true/false values to select between, and a branch opcode to use.
4432
82
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
4433
82
  MachineFunction::iterator It = ++BB->getIterator();
4434
82
4435
82
  //  thisMBB:
4436
82
  //  ...
4437
82
  //   TrueVal = ...
4438
82
  //   setcc r1, r2, r3
4439
82
  //   bNE   r1, r0, copy1MBB
4440
82
  //   fallthrough --> copy0MBB
4441
82
  MachineBasicBlock *thisMBB  = BB;
4442
82
  MachineFunction *F = BB->getParent();
4443
82
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4444
82
  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
4445
82
  F->insert(It, copy0MBB);
4446
82
  F->insert(It, sinkMBB);
4447
82
4448
82
  // Transfer the remainder of BB and its successor edges to sinkMBB.
4449
82
  sinkMBB->splice(sinkMBB->begin(), BB,
4450
82
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
4451
82
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4452
82
4453
82
  // Next, add the true and fallthrough blocks as its successors.
4454
82
  BB->addSuccessor(copy0MBB);
4455
82
  BB->addSuccessor(sinkMBB);
4456
82
4457
82
  if (isFPCmp) {
4458
24
    // bc1[tf] cc, sinkMBB
4459
24
    BuildMI(BB, DL, TII->get(Opc))
4460
24
        .addReg(MI.getOperand(1).getReg())
4461
24
        .addMBB(sinkMBB);
4462
58
  } else {
4463
58
    // bne rs, $0, sinkMBB
4464
58
    BuildMI(BB, DL, TII->get(Opc))
4465
58
        .addReg(MI.getOperand(1).getReg())
4466
58
        .addReg(Mips::ZERO)
4467
58
        .addMBB(sinkMBB);
4468
58
  }
4469
82
4470
82
  //  copy0MBB:
4471
82
  //   %FalseValue = ...
4472
82
  //   # fallthrough to sinkMBB
4473
82
  BB = copy0MBB;
4474
82
4475
82
  // Update machine-CFG edges
4476
82
  BB->addSuccessor(sinkMBB);
4477
82
4478
82
  //  sinkMBB:
4479
82
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4480
82
  //  ...
4481
82
  BB = sinkMBB;
4482
82
4483
82
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4484
82
      .addReg(MI.getOperand(2).getReg())
4485
82
      .addMBB(thisMBB)
4486
82
      .addReg(MI.getOperand(3).getReg())
4487
82
      .addMBB(copy0MBB);
4488
82
4489
82
  MI.eraseFromParent(); // The pseudo instruction is gone now.
4490
82
4491
82
  return BB;
4492
82
}
4493
4494
MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
4495
11
                                                          MachineBasicBlock *BB) const {
4496
11
  assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4497
11
         "Subtarget already supports SELECT nodes with the use of"
4498
11
         "conditional-move instructions.");
4499
11
4500
11
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
4501
11
  DebugLoc DL = MI.getDebugLoc();
4502
11
4503
11
  // D_SELECT substitutes two SELECT nodes that goes one after another and
4504
11
  // have the same condition operand. On machines which don't have
4505
11
  // conditional-move instruction, it reduces unnecessary branch instructions
4506
11
  // which are result of using two diamond patterns that are result of two
4507
11
  // SELECT pseudo instructions.
4508
11
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
4509
11
  MachineFunction::iterator It = ++BB->getIterator();
4510
11
4511
11
  //  thisMBB:
4512
11
  //  ...
4513
11
  //   TrueVal = ...
4514
11
  //   setcc r1, r2, r3
4515
11
  //   bNE   r1, r0, copy1MBB
4516
11
  //   fallthrough --> copy0MBB
4517
11
  MachineBasicBlock *thisMBB = BB;
4518
11
  MachineFunction *F = BB->getParent();
4519
11
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4520
11
  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4521
11
  F->insert(It, copy0MBB);
4522
11
  F->insert(It, sinkMBB);
4523
11
4524
11
  // Transfer the remainder of BB and its successor edges to sinkMBB.
4525
11
  sinkMBB->splice(sinkMBB->begin(), BB,
4526
11
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
4527
11
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4528
11
4529
11
  // Next, add the true and fallthrough blocks as its successors.
4530
11
  BB->addSuccessor(copy0MBB);
4531
11
  BB->addSuccessor(sinkMBB);
4532
11
4533
11
  // bne rs, $0, sinkMBB
4534
11
  BuildMI(BB, DL, TII->get(Mips::BNE))
4535
11
      .addReg(MI.getOperand(2).getReg())
4536
11
      .addReg(Mips::ZERO)
4537
11
      .addMBB(sinkMBB);
4538
11
4539
11
  //  copy0MBB:
4540
11
  //   %FalseValue = ...
4541
11
  //   # fallthrough to sinkMBB
4542
11
  BB = copy0MBB;
4543
11
4544
11
  // Update machine-CFG edges
4545
11
  BB->addSuccessor(sinkMBB);
4546
11
4547
11
  //  sinkMBB:
4548
11
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4549
11
  //  ...
4550
11
  BB = sinkMBB;
4551
11
4552
11
  // Use two PHI nodes to select two reults
4553
11
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4554
11
      .addReg(MI.getOperand(3).getReg())
4555
11
      .addMBB(thisMBB)
4556
11
      .addReg(MI.getOperand(5).getReg())
4557
11
      .addMBB(copy0MBB);
4558
11
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4559
11
      .addReg(MI.getOperand(4).getReg())
4560
11
      .addMBB(thisMBB)
4561
11
      .addReg(MI.getOperand(6).getReg())
4562
11
      .addMBB(copy0MBB);
4563
11
4564
11
  MI.eraseFromParent(); // The pseudo instruction is gone now.
4565
11
4566
11
  return BB;
4567
11
}
4568
4569
// FIXME? Maybe this could be a TableGen attribute on some registers and
4570
// this table could be generated automatically from RegInfo.
4571
unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4572
3
                                               SelectionDAG &DAG) const {
4573
3
  // Named registers is expected to be fairly rare. For now, just support $28
4574
3
  // since the linux kernel uses it.
4575
3
  if (Subtarget.isGP64bit()) {
4576
2
    unsigned Reg = StringSwitch<unsigned>(RegName)
4577
2
                         .Case("$28", Mips::GP_64)
4578
2
                         .Default(0);
4579
2
    if (Reg)
4580
2
      return Reg;
4581
1
  } else {
4582
1
    unsigned Reg = StringSwitch<unsigned>(RegName)
4583
1
                         .Case("$28", Mips::GP)
4584
1
                         .Default(0);
4585
1
    if (Reg)
4586
1
      return Reg;
4587
0
  }
4588
0
  report_fatal_error("Invalid register name global variable");
4589
0
}