Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsInstrInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the Mips implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MipsInstrInfo.h"
14
#include "MCTargetDesc/MipsBaseInfo.h"
15
#include "MCTargetDesc/MipsMCTargetDesc.h"
16
#include "MipsSubtarget.h"
17
#include "llvm/ADT/SmallVector.h"
18
#include "llvm/CodeGen/MachineBasicBlock.h"
19
#include "llvm/CodeGen/MachineFrameInfo.h"
20
#include "llvm/CodeGen/MachineFunction.h"
21
#include "llvm/CodeGen/MachineInstr.h"
22
#include "llvm/CodeGen/MachineInstrBuilder.h"
23
#include "llvm/CodeGen/MachineOperand.h"
24
#include "llvm/CodeGen/TargetOpcodes.h"
25
#include "llvm/CodeGen/TargetSubtargetInfo.h"
26
#include "llvm/IR/DebugLoc.h"
27
#include "llvm/MC/MCInstrDesc.h"
28
#include "llvm/Target/TargetMachine.h"
29
#include <cassert>
30
31
using namespace llvm;
32
33
#define GET_INSTRINFO_CTOR_DTOR
34
#include "MipsGenInstrInfo.inc"
35
36
// Pin the vtable to this file.
37
0
void MipsInstrInfo::anchor() {}
38
39
MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
40
    : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
41
11.3k
      Subtarget(STI), UncondBrOpc(UncondBr) {}
42
43
11.3k
const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
44
11.3k
  if (STI.inMips16Mode())
45
2.91k
    return createMips16InstrInfo(STI);
46
8.43k
47
8.43k
  return createMipsSEInstrInfo(STI);
48
8.43k
}
49
50
121
bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
51
121
  return op.isImm() && op.getImm() == 0;
52
121
}
53
54
/// insertNoop - If data hazard condition is found insert the target nop
55
/// instruction.
56
// FIXME: This appears to be dead code.
57
void MipsInstrInfo::
58
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
59
0
{
60
0
  DebugLoc DL;
61
0
  BuildMI(MBB, MI, DL, get(Mips::NOP));
62
0
}
63
64
MachineMemOperand *
65
MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
66
9.75k
                             MachineMemOperand::Flags Flags) const {
67
9.75k
  MachineFunction &MF = *MBB.getParent();
68
9.75k
  MachineFrameInfo &MFI = MF.getFrameInfo();
69
9.75k
  unsigned Align = MFI.getObjectAlignment(FI);
70
9.75k
71
9.75k
  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
72
9.75k
                                 Flags, MFI.getObjectSize(FI), Align);
73
9.75k
}
74
75
//===----------------------------------------------------------------------===//
76
// Branch Analysis
77
//===----------------------------------------------------------------------===//
78
79
void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
80
                                  MachineBasicBlock *&BB,
81
17.4k
                                  SmallVectorImpl<MachineOperand> &Cond) const {
82
17.4k
  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
83
17.4k
  int NumOp = Inst->getNumExplicitOperands();
84
17.4k
85
17.4k
  // for both int and fp branches, the last explicit operand is the
86
17.4k
  // MBB.
87
17.4k
  BB = Inst->getOperand(NumOp-1).getMBB();
88
17.4k
  Cond.push_back(MachineOperand::CreateImm(Opc));
89
17.4k
90
45.4k
  for (int i = 0; i < NumOp-1; 
i++28.0k
)
91
28.0k
    Cond.push_back(Inst->getOperand(i));
92
17.4k
}
93
94
bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
95
                                  MachineBasicBlock *&TBB,
96
                                  MachineBasicBlock *&FBB,
97
                                  SmallVectorImpl<MachineOperand> &Cond,
98
132k
                                  bool AllowModify) const {
99
132k
  SmallVector<MachineInstr*, 2> BranchInstrs;
100
132k
  BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
101
132k
102
132k
  return (BT == BT_None) || 
(BT == BT_Indirect)42.1k
;
103
132k
}
104
105
void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
106
                                const DebugLoc &DL,
107
948
                                ArrayRef<MachineOperand> Cond) const {
108
948
  unsigned Opc = Cond[0].getImm();
109
948
  const MCInstrDesc &MCID = get(Opc);
110
948
  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
111
948
112
2.42k
  for (unsigned i = 1; i < Cond.size(); 
++i1.48k
) {
113
1.48k
    assert((Cond[i].isImm() || Cond[i].isReg()) &&
114
1.48k
           "Cannot copy operand for conditional branch!");
115
1.48k
    MIB.add(Cond[i]);
116
1.48k
  }
117
948
  MIB.addMBB(TBB);
118
948
}
119
120
unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
121
                                     MachineBasicBlock *TBB,
122
                                     MachineBasicBlock *FBB,
123
                                     ArrayRef<MachineOperand> Cond,
124
                                     const DebugLoc &DL,
125
1.06k
                                     int *BytesAdded) const {
126
1.06k
  // Shouldn't be a fall through.
127
1.06k
  assert(TBB && "insertBranch must not be told to insert a fallthrough");
128
1.06k
  assert(!BytesAdded && "code size not handled");
129
1.06k
130
1.06k
  // # of condition operands:
131
1.06k
  //  Unconditional branches: 0
132
1.06k
  //  Floating point branches: 1 (opc)
133
1.06k
  //  Int BranchZero: 2 (opc, reg)
134
1.06k
  //  Int Branch: 3 (opc, reg0, reg1)
135
1.06k
  assert((Cond.size() <= 3) &&
136
1.06k
         "# of Mips branch conditions must be <= 3!");
137
1.06k
138
1.06k
  // Two-way Conditional branch.
139
1.06k
  if (FBB) {
140
55
    BuildCondBr(MBB, TBB, DL, Cond);
141
55
    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
142
55
    return 2;
143
55
  }
144
1.00k
145
1.00k
  // One way branch.
146
1.00k
  // Unconditional branch.
147
1.00k
  if (Cond.empty())
148
116
    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
149
893
  else // Conditional branch.
150
893
    BuildCondBr(MBB, TBB, DL, Cond);
151
1.00k
  return 1;
152
1.00k
}
153
154
unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
155
1.24k
                                     int *BytesRemoved) const {
156
1.24k
  assert(!BytesRemoved && "code size not handled");
157
1.24k
158
1.24k
  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
159
1.24k
  unsigned removed = 0;
160
1.24k
161
1.24k
  // Up to 2 branches are removed.
162
1.24k
  // Note that indirect branches are not removed.
163
3.06k
  while (I != REnd && 
removed < 22.86k
) {
164
2.30k
    // Skip past debug instructions.
165
2.30k
    if (I->isDebugInstr()) {
166
1
      ++I;
167
1
      continue;
168
1
    }
169
2.29k
    if (!getAnalyzableBrOpc(I->getOpcode()))
170
479
      break;
171
1.82k
    // Remove the branch.
172
1.82k
    I->eraseFromParent();
173
1.82k
    I = MBB.rbegin();
174
1.82k
    ++removed;
175
1.82k
  }
176
1.24k
177
1.24k
  return removed;
178
1.24k
}
179
180
/// reverseBranchCondition - Return the inverse opcode of the
181
/// specified Branch instruction.
182
bool MipsInstrInfo::reverseBranchCondition(
183
262
    SmallVectorImpl<MachineOperand> &Cond) const {
184
262
  assert( (Cond.size() && Cond.size() <= 3) &&
185
262
          "Invalid Mips branch condition!");
186
262
  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
187
262
  return false;
188
262
}
189
190
MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
191
    MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
192
    SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
193
132k
    SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
194
132k
  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
195
132k
196
132k
  // Skip all the debug instructions.
197
132k
  while (I != REnd && 
I->isDebugInstr()131k
)
198
0
    ++I;
199
132k
200
132k
  if (I == REnd || 
!isUnpredicatedTerminator(*I)131k
) {
201
16.6k
    // This block ends with no branches (it just falls through to its succ).
202
16.6k
    // Leave TBB/FBB null.
203
16.6k
    TBB = FBB = nullptr;
204
16.6k
    return BT_NoBranch;
205
16.6k
  }
206
115k
207
115k
  MachineInstr *LastInst = &*I;
208
115k
  unsigned LastOpc = LastInst->getOpcode();
209
115k
  BranchInstrs.push_back(LastInst);
210
115k
211
115k
  // Not an analyzable branch (e.g., indirect jump).
212
115k
  if (!getAnalyzableBrOpc(LastOpc))
213
92.8k
    return LastInst->isIndirectBranch() ? 
BT_Indirect2.64k
:
BT_None90.2k
;
214
23.0k
215
23.0k
  // Get the second to last instruction in the block.
216
23.0k
  unsigned SecondLastOpc = 0;
217
23.0k
  MachineInstr *SecondLastInst = nullptr;
218
23.0k
219
23.0k
  // Skip past any debug instruction to see if the second last actual
220
23.0k
  // is a branch.
221
23.0k
  ++I;
222
23.1k
  while (I != REnd && 
I->isDebugInstr()20.8k
)
223
22
    ++I;
224
23.0k
225
23.0k
  if (I != REnd) {
226
20.8k
    SecondLastInst = &*I;
227
20.8k
    SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
228
20.8k
229
20.8k
    // Not an analyzable branch (must be an indirect jump).
230
20.8k
    if (isUnpredicatedTerminator(*SecondLastInst) && 
!SecondLastOpc2.98k
)
231
147
      return BT_None;
232
22.9k
  }
233
22.9k
234
22.9k
  // If there is only one terminator instruction, process it.
235
22.9k
  if (!SecondLastOpc) {
236
20.0k
    // Unconditional branch.
237
20.0k
    if (LastInst->isUnconditionalBranch()) {
238
5.51k
      TBB = LastInst->getOperand(0).getMBB();
239
5.51k
      return BT_Uncond;
240
5.51k
    }
241
14.5k
242
14.5k
    // Conditional branch
243
14.5k
    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
244
14.5k
    return BT_Cond;
245
14.5k
  }
246
2.83k
247
2.83k
  // If we reached here, there are two branches.
248
2.83k
  // If there are three terminators, we don't know what sort of block this is.
249
2.83k
  if (++I != REnd && 
isUnpredicatedTerminator(*I)2.45k
)
250
0
    return BT_None;
251
2.83k
252
2.83k
  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
253
2.83k
254
2.83k
  // If second to last instruction is an unconditional branch,
255
2.83k
  // analyze it and remove the last instruction.
256
2.83k
  if (SecondLastInst->isUnconditionalBranch()) {
257
0
    // Return if the last instruction cannot be removed.
258
0
    if (!AllowModify)
259
0
      return BT_None;
260
0
261
0
    TBB = SecondLastInst->getOperand(0).getMBB();
262
0
    LastInst->eraseFromParent();
263
0
    BranchInstrs.pop_back();
264
0
    return BT_Uncond;
265
0
  }
266
2.83k
267
2.83k
  // Conditional branch followed by an unconditional branch.
268
2.83k
  // The last one must be unconditional.
269
2.83k
  if (!LastInst->isUnconditionalBranch())
270
0
    return BT_None;
271
2.83k
272
2.83k
  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
273
2.83k
  FBB = LastInst->getOperand(0).getMBB();
274
2.83k
275
2.83k
  return BT_CondUncond;
276
2.83k
}
277
278
1.97k
bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
279
1.97k
  switch (BranchOpc) {
280
1.97k
  case Mips::B:
281
1.20k
  case Mips::BAL:
282
1.20k
  case Mips::BAL_BR:
283
1.20k
  case Mips::BAL_BR_MM:
284
1.20k
  case Mips::BC1F:
285
1.20k
  case Mips::BC1FL:
286
1.20k
  case Mips::BC1T:
287
1.20k
  case Mips::BC1TL:
288
1.20k
  case Mips::BEQ:     case Mips::BEQ64:
289
1.20k
  case Mips::BEQL:
290
1.20k
  case Mips::BGEZ:    case Mips::BGEZ64:
291
1.20k
  case Mips::BGEZL:
292
1.20k
  case Mips::BGEZAL:
293
1.20k
  case Mips::BGEZALL:
294
1.20k
  case Mips::BGTZ:    case Mips::BGTZ64:
295
1.20k
  case Mips::BGTZL:
296
1.20k
  case Mips::BLEZ:    case Mips::BLEZ64:
297
1.20k
  case Mips::BLEZL:
298
1.20k
  case Mips::BLTZ:    case Mips::BLTZ64:
299
1.20k
  case Mips::BLTZL:
300
1.20k
  case Mips::BLTZAL:
301
1.20k
  case Mips::BLTZALL:
302
1.20k
  case Mips::BNE:     case Mips::BNE64:
303
1.20k
  case Mips::BNEL:
304
1.20k
    return isInt<18>(BrOffset);
305
1.20k
306
1.20k
  // microMIPSr3 branches
307
1.20k
  case Mips::B_MM:
308
89
  case Mips::BC1F_MM:
309
89
  case Mips::BC1T_MM:
310
89
  case Mips::BEQ_MM:
311
89
  case Mips::BGEZ_MM:
312
89
  case Mips::BGEZAL_MM:
313
89
  case Mips::BGTZ_MM:
314
89
  case Mips::BLEZ_MM:
315
89
  case Mips::BLTZ_MM:
316
89
  case Mips::BLTZAL_MM:
317
89
  case Mips::BNE_MM:
318
89
  case Mips::BEQZC_MM:
319
89
  case Mips::BNEZC_MM:
320
89
    return isInt<17>(BrOffset);
321
89
322
89
  // microMIPSR3 short branches.
323
89
  case Mips::B16_MM:
324
0
    return isInt<11>(BrOffset);
325
89
326
89
  case Mips::BEQZ16_MM:
327
8
  case Mips::BNEZ16_MM:
328
8
    return isInt<8>(BrOffset);
329
8
330
8
  // MIPSR6 branches.
331
87
  case Mips::BALC:
332
87
  case Mips::BC:
333
87
    return isInt<28>(BrOffset);
334
87
335
170
  case Mips::BC1EQZ:
336
170
  case Mips::BC1NEZ:
337
170
  case Mips::BC2EQZ:
338
170
  case Mips::BC2NEZ:
339
170
  case Mips::BEQC:   case Mips::BEQC64:
340
170
  case Mips::BNEC:   case Mips::BNEC64:
341
170
  case Mips::BGEC:   case Mips::BGEC64:
342
170
  case Mips::BGEUC:  case Mips::BGEUC64:
343
170
  case Mips::BGEZC:  case Mips::BGEZC64:
344
170
  case Mips::BGTZC:  case Mips::BGTZC64:
345
170
  case Mips::BLEZC:  case Mips::BLEZC64:
346
170
  case Mips::BLTC:   case Mips::BLTC64:
347
170
  case Mips::BLTUC:  case Mips::BLTUC64:
348
170
  case Mips::BLTZC:  case Mips::BLTZC64:
349
170
  case Mips::BNVC:
350
170
  case Mips::BOVC:
351
170
  case Mips::BGEZALC:
352
170
  case Mips::BEQZALC:
353
170
  case Mips::BGTZALC:
354
170
  case Mips::BLEZALC:
355
170
  case Mips::BLTZALC:
356
170
  case Mips::BNEZALC:
357
170
    return isInt<18>(BrOffset);
358
170
359
259
  case Mips::BEQZC:  case Mips::BEQZC64:
360
259
  case Mips::BNEZC:  case Mips::BNEZC64:
361
259
    return isInt<23>(BrOffset);
362
259
363
259
  // microMIPSR6 branches
364
259
  case Mips::BC16_MMR6:
365
0
    return isInt<11>(BrOffset);
366
259
367
259
  case Mips::BEQZC16_MMR6:
368
0
  case Mips::BNEZC16_MMR6:
369
0
    return isInt<8>(BrOffset);
370
0
371
16
  case Mips::BALC_MMR6:
372
16
  case Mips::BC_MMR6:
373
16
    return isInt<27>(BrOffset);
374
16
375
16
  case Mips::BC1EQZC_MMR6:
376
8
  case Mips::BC1NEZC_MMR6:
377
8
  case Mips::BC2EQZC_MMR6:
378
8
  case Mips::BC2NEZC_MMR6:
379
8
  case Mips::BGEZALC_MMR6:
380
8
  case Mips::BEQZALC_MMR6:
381
8
  case Mips::BGTZALC_MMR6:
382
8
  case Mips::BLEZALC_MMR6:
383
8
  case Mips::BLTZALC_MMR6:
384
8
  case Mips::BNEZALC_MMR6:
385
8
  case Mips::BNVC_MMR6:
386
8
  case Mips::BOVC_MMR6:
387
8
    return isInt<17>(BrOffset);
388
8
389
40
  case Mips::BEQC_MMR6:
390
40
  case Mips::BNEC_MMR6:
391
40
  case Mips::BGEC_MMR6:
392
40
  case Mips::BGEUC_MMR6:
393
40
  case Mips::BGEZC_MMR6:
394
40
  case Mips::BGTZC_MMR6:
395
40
  case Mips::BLEZC_MMR6:
396
40
  case Mips::BLTC_MMR6:
397
40
  case Mips::BLTUC_MMR6:
398
40
  case Mips::BLTZC_MMR6:
399
40
    return isInt<18>(BrOffset);
400
40
401
40
  case Mips::BEQZC_MMR6:
402
23
  case Mips::BNEZC_MMR6:
403
23
    return isInt<23>(BrOffset);
404
23
405
23
  // DSP branches.
406
23
  case Mips::BPOSGE32:
407
1
    return isInt<18>(BrOffset);
408
23
  case Mips::BPOSGE32_MM:
409
1
  case Mips::BPOSGE32C_MMR3:
410
1
    return isInt<17>(BrOffset);
411
1
412
1
  // cnMIPS branches.
413
12
  case Mips::BBIT0:
414
12
  case Mips::BBIT032:
415
12
  case Mips::BBIT1:
416
12
  case Mips::BBIT132:
417
12
    return isInt<18>(BrOffset);
418
12
419
12
  // MSA branches.
420
52
  case Mips::BZ_B:
421
52
  case Mips::BZ_H:
422
52
  case Mips::BZ_W:
423
52
  case Mips::BZ_D:
424
52
  case Mips::BZ_V:
425
52
  case Mips::BNZ_B:
426
52
  case Mips::BNZ_H:
427
52
  case Mips::BNZ_W:
428
52
  case Mips::BNZ_D:
429
52
  case Mips::BNZ_V:
430
52
    return isInt<18>(BrOffset);
431
0
  }
432
0
433
0
  llvm_unreachable("Unknown branch instruction!");
434
0
}
435
436
437
/// Return the corresponding compact (no delay slot) form of a branch.
438
unsigned MipsInstrInfo::getEquivalentCompactForm(
439
3.52k
    const MachineBasicBlock::iterator I) const {
440
3.52k
  unsigned Opcode = I->getOpcode();
441
3.52k
  bool canUseShortMicroMipsCTI = false;
442
3.52k
443
3.52k
  if (Subtarget.inMicroMipsMode()) {
444
1.59k
    switch (Opcode) {
445
1.59k
    case Mips::BNE:
446
74
    case Mips::BNE_MM:
447
74
    case Mips::BEQ:
448
74
    case Mips::BEQ_MM:
449
74
    // microMIPS has NE,EQ branches that do not have delay slots provided one
450
74
    // of the operands is zero.
451
74
      if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
452
66
        canUseShortMicroMipsCTI = true;
453
74
      break;
454
74
    // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
455
74
    // expanded to JR_MM, so they can be replaced with JRC16_MM.
456
1.39k
    case Mips::JR:
457
1.39k
    case Mips::PseudoReturn:
458
1.39k
    case Mips::PseudoIndirectBranch:
459
1.39k
      canUseShortMicroMipsCTI = true;
460
1.39k
      break;
461
3.52k
    }
462
3.52k
  }
463
3.52k
464
3.52k
  // MIPSR6 forbids both operands being the zero register.
465
3.52k
  if (Subtarget.hasMips32r6() && 
(I->getNumOperands() > 1)2.73k
&&
466
3.52k
      
(2.39k
I->getOperand(0).isReg()2.39k
&&
467
2.39k
       
(2.25k
I->getOperand(0).getReg() == Mips::ZERO2.25k
||
468
2.25k
        
I->getOperand(0).getReg() == Mips::ZERO_642.23k
)) &&
469
3.52k
      
(20
I->getOperand(1).isReg()20
&&
470
20
       (I->getOperand(1).getReg() == Mips::ZERO ||
471
20
        
I->getOperand(1).getReg() == Mips::ZERO_640
)))
472
20
    return 0;
473
3.50k
474
3.50k
  if (Subtarget.hasMips32r6() || 
canUseShortMicroMipsCTI783
) {
475
3.37k
    switch (Opcode) {
476
3.37k
    case Mips::B:
477
22
      return Mips::BC;
478
3.37k
    case Mips::BAL:
479
0
      return Mips::BALC;
480
3.37k
    case Mips::BEQ:
481
251
    case Mips::BEQ_MM:
482
251
      if (canUseShortMicroMipsCTI)
483
54
        return Mips::BEQZC_MM;
484
197
      else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
485
0
        return 0;
486
197
      return Mips::BEQC;
487
197
    case Mips::BNE:
488
146
    case Mips::BNE_MM:
489
146
      if (canUseShortMicroMipsCTI)
490
12
        return Mips::BNEZC_MM;
491
134
      else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
492
2
        return 0;
493
132
      return Mips::BNEC;
494
132
    case Mips::BGE:
495
0
      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
496
0
        return 0;
497
0
      return Mips::BGEC;
498
0
    case Mips::BGEU:
499
0
      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
500
0
        return 0;
501
0
      return Mips::BGEUC;
502
4
    case Mips::BGEZ:
503
4
      return Mips::BGEZC;
504
6
    case Mips::BGTZ:
505
6
      return Mips::BGTZC;
506
8
    case Mips::BLEZ:
507
8
      return Mips::BLEZC;
508
0
    case Mips::BLT:
509
0
      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
510
0
        return 0;
511
0
      return Mips::BLTC;
512
0
    case Mips::BLTU:
513
0
      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
514
0
        return 0;
515
0
      return Mips::BLTUC;
516
10
    case Mips::BLTZ:
517
10
      return Mips::BLTZC;
518
42
    case Mips::BEQ64:
519
42
      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
520
0
        return 0;
521
42
      return Mips::BEQC64;
522
42
    case Mips::BNE64:
523
15
      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
524
1
        return 0;
525
14
      return Mips::BNEC64;
526
14
    case Mips::BGTZ64:
527
2
      return Mips::BGTZC64;
528
14
    case Mips::BGEZ64:
529
2
      return Mips::BGEZC64;
530
14
    case Mips::BLTZ64:
531
2
      return Mips::BLTZC64;
532
14
    case Mips::BLEZ64:
533
2
      return Mips::BLEZC64;
534
14
    // For MIPSR6, the instruction 'jic' can be used for these cases. Some
535
14
    // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
536
1.82k
    case Mips::JR:
537
1.82k
    case Mips::PseudoIndirectBranchR6:
538
1.82k
    case Mips::PseudoReturn:
539
1.82k
    case Mips::TAILCALLR6REG:
540
1.82k
      if (canUseShortMicroMipsCTI)
541
1.39k
        return Mips::JRC16_MM;
542
436
      return Mips::JIC;
543
436
    case Mips::JALRPseudo:
544
135
      return Mips::JIALC;
545
535
    case Mips::JR64:
546
535
    case Mips::PseudoIndirectBranch64R6:
547
535
    case Mips::PseudoReturn64:
548
535
    case Mips::TAILCALL64R6REG:
549
535
      return Mips::JIC64;
550
535
    case Mips::JALR64Pseudo:
551
231
      return Mips::JIALC64;
552
535
    default:
553
130
      return 0;
554
131
    }
555
131
  }
556
131
557
131
  return 0;
558
131
}
559
560
/// Predicate for distingushing between control transfer instructions and all
561
/// other instructions for handling forbidden slots. Consider inline assembly
562
/// as unsafe as well.
563
241
bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
564
241
  if (MI.isInlineAsm())
565
0
    return false;
566
241
567
241
  return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
568
241
}
569
570
/// Predicate for distingushing instructions that have forbidden slots.
571
13.8k
bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
572
13.8k
  return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
573
13.8k
}
574
575
/// Return the number of bytes of code the specified instruction may be.
576
147k
unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
577
147k
  switch (MI.getOpcode()) {
578
147k
  default:
579
146k
    return MI.getDesc().getSize();
580
147k
  case  TargetOpcode::INLINEASM:
581
888
  case  TargetOpcode::INLINEASM_BR: {       // Inline Asm: Variable size.
582
888
    const MachineFunction *MF = MI.getParent()->getParent();
583
888
    const char *AsmStr = MI.getOperand(0).getSymbolName();
584
888
    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
585
888
  }
586
888
  case Mips::CONSTPOOL_ENTRY:
587
67
    // If this machine instr is a constant pool entry, its size is recorded as
588
67
    // operand #2.
589
67
    return MI.getOperand(2).getImm();
590
147k
  }
591
147k
}
592
593
MachineInstrBuilder
594
MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
595
1.61k
                                  MachineBasicBlock::iterator I) const {
596
1.61k
  MachineInstrBuilder MIB;
597
1.61k
598
1.61k
  // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
599
1.61k
  // Pick the zero form of the branch for readable assembly and for greater
600
1.61k
  // branch distance in non-microMIPS mode.
601
1.61k
  // Additional MIPSR6 does not permit the use of register $zero for compact
602
1.61k
  // branches.
603
1.61k
  // FIXME: Certain atomic sequences on mips64 generate 32bit references to
604
1.61k
  // Mips::ZERO, which is incorrect. This test should be updated to use
605
1.61k
  // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
606
1.61k
  // are fixed.
607
1.61k
  int ZeroOperandPosition = -1;
608
1.61k
  bool BranchWithZeroOperand = false;
609
1.61k
  if (I->isBranch() && 
!I->isPseudo()256
) {
610
243
    auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
611
243
    ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
612
243
    BranchWithZeroOperand = ZeroOperandPosition != -1;
613
243
  }
614
1.61k
615
1.61k
  if (BranchWithZeroOperand) {
616
188
    switch (NewOpc) {
617
188
    case Mips::BEQC:
618
96
      NewOpc = Mips::BEQZC;
619
96
      break;
620
188
    case Mips::BNEC:
621
38
      NewOpc = Mips::BNEZC;
622
38
      break;
623
188
    case Mips::BGEC:
624
0
      NewOpc = Mips::BGEZC;
625
0
      break;
626
188
    case Mips::BLTC:
627
0
      NewOpc = Mips::BLTZC;
628
0
      break;
629
188
    case Mips::BEQC64:
630
20
      NewOpc = Mips::BEQZC64;
631
20
      break;
632
188
    case Mips::BNEC64:
633
1
      NewOpc = Mips::BNEZC64;
634
1
      break;
635
1.61k
    }
636
1.61k
  }
637
1.61k
638
1.61k
  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
639
1.61k
640
1.61k
  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
641
1.61k
  // immediate 0 as an operand and requires the removal of it's implicit-def %ra
642
1.61k
  // implicit operand as copying the implicit operations of the instructio we're
643
1.61k
  // looking at will give us the correct flags.
644
1.61k
  if (NewOpc == Mips::JIC || 
NewOpc == Mips::JIALC1.39k
||
NewOpc == Mips::JIC641.33k
||
645
1.61k
      
NewOpc == Mips::JIALC641.06k
) {
646
664
647
664
    if (NewOpc == Mips::JIALC || 
NewOpc == Mips::JIALC64597
)
648
182
      MIB->RemoveOperand(0);
649
664
650
1.32k
    for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; 
++J664
) {
651
664
      MIB.add(I->getOperand(J));
652
664
    }
653
664
654
664
    MIB.addImm(0);
655
664
656
664
    // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
657
664
    // add it to the new instruction.
658
664
    for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
659
2.44k
         J < E; 
++J1.77k
) {
660
1.77k
      const MachineOperand &MO = I->getOperand(J);
661
1.77k
      if (MO.isMCSymbol() && 
(MO.getTargetFlags() & MipsII::MO_JALR)157
)
662
157
        MIB.addSym(MO.getMCSymbol(), MipsII::MO_JALR);
663
1.77k
    }
664
664
665
664
666
950
  } else {
667
2.36k
    for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; 
++J1.41k
) {
668
1.41k
      if (BranchWithZeroOperand && 
(unsigned)ZeroOperandPosition == J564
)
669
188
        continue;
670
1.23k
671
1.23k
      MIB.add(I->getOperand(J));
672
1.23k
    }
673
950
  }
674
1.61k
675
1.61k
  MIB.copyImplicitOps(*I);
676
1.61k
  MIB.cloneMemRefs(*I);
677
1.61k
  return MIB;
678
1.61k
}
679
680
bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
681
17.2k
                                          unsigned &SrcOpIdx2) const {
682
17.2k
  assert(!MI.isBundle() &&
683
17.2k
         "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
684
17.2k
685
17.2k
  const MCInstrDesc &MCID = MI.getDesc();
686
17.2k
  if (!MCID.isCommutable())
687
0
    return false;
688
17.2k
689
17.2k
  switch (MI.getOpcode()) {
690
17.2k
  case Mips::DPADD_U_H:
691
48
  case Mips::DPADD_U_W:
692
48
  case Mips::DPADD_U_D:
693
48
  case Mips::DPADD_S_H:
694
48
  case Mips::DPADD_S_W:
695
48
  case Mips::DPADD_S_D:
696
48
    // The first operand is both input and output, so it should not commute
697
48
    if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
698
24
      return false;
699
24
700
24
    if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
701
0
      return false;
702
24
    return true;
703
17.2k
  }
704
17.2k
  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
705
17.2k
}
706
707
// ins, ext, dext*, dins have the following constraints:
708
// X <= pos      <  Y
709
// X <  size     <= Y
710
// X <  pos+size <= Y
711
//
712
// dinsm and dinsu have the following constraints:
713
// X <= pos      <  Y
714
// X <= size     <= Y
715
// X <  pos+size <= Y
716
//
717
// The callee of verifyInsExtInstruction however gives the bounds of
718
// dins[um] like the other (d)ins (d)ext(um) instructions, so that this
719
// function doesn't have to vary it's behaviour based on the instruction
720
// being checked.
721
static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
722
                                    const int64_t PosLow, const int64_t PosHigh,
723
                                    const int64_t SizeLow,
724
                                    const int64_t SizeHigh,
725
                                    const int64_t BothLow,
726
1.53k
                                    const int64_t BothHigh) {
727
1.53k
  MachineOperand MOPos = MI.getOperand(2);
728
1.53k
  if (!MOPos.isImm()) {
729
0
    ErrInfo = "Position is not an immediate!";
730
0
    return false;
731
0
  }
732
1.53k
  int64_t Pos = MOPos.getImm();
733
1.53k
  if (!((PosLow <= Pos) && (Pos < PosHigh))) {
734
8
    ErrInfo = "Position operand is out of range!";
735
8
    return false;
736
8
  }
737
1.52k
738
1.52k
  MachineOperand MOSize = MI.getOperand(3);
739
1.52k
  if (!MOSize.isImm()) {
740
0
    ErrInfo = "Size operand is not an immediate!";
741
0
    return false;
742
0
  }
743
1.52k
  int64_t Size = MOSize.getImm();
744
1.52k
  if (!((SizeLow < Size) && (Size <= SizeHigh))) {
745
8
    ErrInfo = "Size operand is out of range!";
746
8
    return false;
747
8
  }
748
1.51k
749
1.51k
  if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
750
7
    ErrInfo = "Position + Size is out of range!";
751
7
    return false;
752
7
  }
753
1.51k
754
1.51k
  return true;
755
1.51k
}
756
757
//  Perform target specific instruction verification.
758
bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
759
658k
                                      StringRef &ErrInfo) const {
760
658k
  // Verify that ins and ext instructions are well formed.
761
658k
  switch (MI.getOpcode()) {
762
658k
    case Mips::EXT:
763
705
    case Mips::EXT_MM:
764
705
    case Mips::INS:
765
705
    case Mips::INS_MM:
766
705
    case Mips::DINS:
767
705
      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
768
705
    case Mips::DINSM:
769
119
      // The ISA spec has a subtle difference between dinsm and dextm
770
119
      // in that it says:
771
119
      // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
772
119
      // To make the bounds checks similar, the range 1 < size <= 64 is checked
773
119
      // for 'dinsm'.
774
119
      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
775
705
    case Mips::DINSU:
776
525
      // The ISA spec has a subtle difference between dinsu and dextu in that
777
525
      // the size range of dinsu is specified as 1 <= size <= 32 whereas size
778
525
      // for dextu is 0 < size <= 32. The range checked for dinsu here is
779
525
      // 0 < size <= 32, which is equivalent and similar to dextu.
780
525
      return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
781
705
    case Mips::DEXT:
782
118
      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
783
705
    case Mips::DEXTM:
784
3
      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
785
705
    case Mips::DEXTU:
786
63
      return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
787
4.33k
    case Mips::TAILCALLREG:
788
4.33k
    case Mips::PseudoIndirectBranch:
789
4.33k
    case Mips::JR:
790
4.33k
    case Mips::JR64:
791
4.33k
    case Mips::JALR:
792
4.33k
    case Mips::JALR64:
793
4.33k
    case Mips::JALRPseudo:
794
4.33k
      if (!Subtarget.useIndirectJumpsHazard())
795
4.33k
        return true;
796
2
797
2
      ErrInfo = "invalid instruction when using jump guards!";
798
2
      return false;
799
652k
    default:
800
652k
      return true;
801
0
  }
802
0
803
0
  return true;
804
0
}
805
806
std::pair<unsigned, unsigned>
807
222
MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
808
222
  return std::make_pair(TF, 0u);
809
222
}
810
811
ArrayRef<std::pair<unsigned, const char*>>
812
230
MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
813
230
 using namespace MipsII;
814
230
815
230
 static const std::pair<unsigned, const char*> Flags[] = {
816
230
    {MO_GOT,          "mips-got"},
817
230
    {MO_GOT_CALL,     "mips-got-call"},
818
230
    {MO_GPREL,        "mips-gprel"},
819
230
    {MO_ABS_HI,       "mips-abs-hi"},
820
230
    {MO_ABS_LO,       "mips-abs-lo"},
821
230
    {MO_TLSGD,        "mips-tlsgd"},
822
230
    {MO_TLSLDM,       "mips-tlsldm"},
823
230
    {MO_DTPREL_HI,    "mips-dtprel-hi"},
824
230
    {MO_DTPREL_LO,    "mips-dtprel-lo"},
825
230
    {MO_GOTTPREL,     "mips-gottprel"},
826
230
    {MO_TPREL_HI,     "mips-tprel-hi"},
827
230
    {MO_TPREL_LO,     "mips-tprel-lo"},
828
230
    {MO_GPOFF_HI,     "mips-gpoff-hi"},
829
230
    {MO_GPOFF_LO,     "mips-gpoff-lo"},
830
230
    {MO_GOT_DISP,     "mips-got-disp"},
831
230
    {MO_GOT_PAGE,     "mips-got-page"},
832
230
    {MO_GOT_OFST,     "mips-got-ofst"},
833
230
    {MO_HIGHER,       "mips-higher"},
834
230
    {MO_HIGHEST,      "mips-highest"},
835
230
    {MO_GOT_HI16,     "mips-got-hi16"},
836
230
    {MO_GOT_LO16,     "mips-got-lo16"},
837
230
    {MO_CALL_HI16,    "mips-call-hi16"},
838
230
    {MO_CALL_LO16,    "mips-call-lo16"},
839
230
    {MO_JALR,         "mips-jalr"}
840
230
  };
841
230
  return makeArrayRef(Flags);
842
230
}