Coverage Report

Created: 2018-05-22 11:14

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsLongBranch.cpp
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Count
Source (jump to first uncovered line)
1
//===- MipsLongBranch.cpp - Emit long branches ----------------------------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This pass expands a branch or jump instruction into a long branch if its
11
// offset is too large to fit into its immediate field.
12
//
13
// FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
14
//===----------------------------------------------------------------------===//
15
16
#include "MCTargetDesc/MipsABIInfo.h"
17
#include "MCTargetDesc/MipsBaseInfo.h"
18
#include "MCTargetDesc/MipsMCNaCl.h"
19
#include "MCTargetDesc/MipsMCTargetDesc.h"
20
#include "Mips.h"
21
#include "MipsInstrInfo.h"
22
#include "MipsMachineFunction.h"
23
#include "MipsSubtarget.h"
24
#include "MipsTargetMachine.h"
25
#include "llvm/ADT/SmallVector.h"
26
#include "llvm/ADT/Statistic.h"
27
#include "llvm/ADT/StringRef.h"
28
#include "llvm/CodeGen/MachineBasicBlock.h"
29
#include "llvm/CodeGen/MachineFunction.h"
30
#include "llvm/CodeGen/MachineFunctionPass.h"
31
#include "llvm/CodeGen/MachineInstr.h"
32
#include "llvm/CodeGen/MachineInstrBuilder.h"
33
#include "llvm/CodeGen/MachineOperand.h"
34
#include "llvm/CodeGen/TargetSubtargetInfo.h"
35
#include "llvm/IR/DebugLoc.h"
36
#include "llvm/Support/CommandLine.h"
37
#include "llvm/Support/ErrorHandling.h"
38
#include "llvm/Support/MathExtras.h"
39
#include "llvm/Target/TargetMachine.h"
40
#include <cassert>
41
#include <cstdint>
42
#include <iterator>
43
44
using namespace llvm;
45
46
#define DEBUG_TYPE "mips-long-branch"
47
48
STATISTIC(LongBranches, "Number of long branches.");
49
50
static cl::opt<bool> SkipLongBranch(
51
  "skip-mips-long-branch",
52
  cl::init(false),
53
  cl::desc("MIPS: Skip long branch pass."),
54
  cl::Hidden);
55
56
static cl::opt<bool> ForceLongBranch(
57
  "force-mips-long-branch",
58
  cl::init(false),
59
  cl::desc("MIPS: Expand all branches to long format."),
60
  cl::Hidden);
61
62
namespace {
63
64
  using Iter = MachineBasicBlock::iterator;
65
  using ReverseIter = MachineBasicBlock::reverse_iterator;
66
67
  struct MBBInfo {
68
    uint64_t Size = 0;
69
    uint64_t Address;
70
    bool HasLongBranch = false;
71
    MachineInstr *Br = nullptr;
72
73
14.3k
    MBBInfo() = default;
74
  };
75
76
  class MipsLongBranch : public MachineFunctionPass {
77
  public:
78
    static char ID;
79
80
1.86k
    MipsLongBranch() : MachineFunctionPass(ID), ABI(MipsABIInfo::Unknown()) {
81
1.86k
      initializeMipsLongBranchPass(*PassRegistry::getPassRegistry());
82
1.86k
    }
83
84
1.83k
    StringRef getPassName() const override { return "Mips Long Branch"; }
85
86
    bool runOnMachineFunction(MachineFunction &F) override;
87
88
1.83k
    MachineFunctionProperties getRequiredProperties() const override {
89
1.83k
      return MachineFunctionProperties().set(
90
1.83k
          MachineFunctionProperties::Property::NoVRegs);
91
1.83k
    }
92
93
  private:
94
    void splitMBB(MachineBasicBlock *MBB);
95
    void initMBBInfo();
96
    int64_t computeOffset(const MachineInstr *Br);
97
    void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
98
                       MachineBasicBlock *MBBOpnd);
99
    void expandToLongBranch(MBBInfo &Info);
100
101
    MachineFunction *MF;
102
    SmallVector<MBBInfo, 16> MBBInfos;
103
    bool IsPIC;
104
    MipsABIInfo ABI;
105
    unsigned LongBranchSeqSize;
106
  };
107
108
} // end anonymous namespace
109
110
char MipsLongBranch::ID = 0;
111
112
INITIALIZE_PASS(MipsLongBranch, DEBUG_TYPE,
113
                "Expand out of range branch instructions", false, false)
114
115
/// Iterate over list of Br's operands and search for a MachineBasicBlock
116
/// operand.
117
1.37k
static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
118
3.47k
  for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; 
++I2.10k
) {
119
3.47k
    const MachineOperand &MO = Br.getOperand(I);
120
3.47k
121
3.47k
    if (MO.isMBB())
122
1.37k
      return MO.getMBB();
123
3.47k
  }
124
1.37k
125
1.37k
  
llvm_unreachable0
("This instruction does not have an MBB operand.");
126
0
}
127
128
// Traverse the list of instructions backwards until a non-debug instruction is
129
// found or it reaches E.
130
29.9k
static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) {
131
29.9k
  for (; B != E; 
++B0
)
132
29.5k
    if (!B->isDebugInstr())
133
29.5k
      return B;
134
29.9k
135
29.9k
  
return E362
;
136
29.9k
}
137
138
// Split MBB if it has two direct jumps/branches.
139
14.3k
void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
140
14.3k
  ReverseIter End = MBB->rend();
141
14.3k
  ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
142
14.3k
143
14.3k
  // Return if MBB has no branch instructions.
144
14.3k
  if ((LastBr == End) ||
145
14.3k
      
(14.2k
!LastBr->isConditionalBranch()14.2k
&&
!LastBr->isUnconditionalBranch()13.2k
))
146
13.0k
    return;
147
1.29k
148
1.29k
  ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End);
149
1.29k
150
1.29k
  // MBB has only one branch instruction if FirstBr is not a branch
151
1.29k
  // instruction.
152
1.29k
  if ((FirstBr == End) ||
153
1.29k
      
(992
!FirstBr->isConditionalBranch()992
&&
!FirstBr->isUnconditionalBranch()961
))
154
1.26k
    return;
155
31
156
31
  assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
157
31
158
31
  // Create a new MBB. Move instructions in MBB to the newly created MBB.
159
31
  MachineBasicBlock *NewMBB =
160
31
    MF->CreateMachineBasicBlock(MBB->getBasicBlock());
161
31
162
31
  // Insert NewMBB and fix control flow.
163
31
  MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
164
31
  NewMBB->transferSuccessors(MBB);
165
31
  NewMBB->removeSuccessor(Tgt, true);
166
31
  MBB->addSuccessor(NewMBB);
167
31
  MBB->addSuccessor(Tgt);
168
31
  MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
169
31
170
31
  NewMBB->splice(NewMBB->end(), MBB, LastBr.getReverse(), MBB->end());
171
31
}
172
173
// Fill MBBInfos.
174
12.1k
void MipsLongBranch::initMBBInfo() {
175
12.1k
  // Split the MBBs if they have two branches. Each basic block should have at
176
12.1k
  // most one branch after this loop is executed.
177
12.1k
  for (auto &MBB : *MF)
178
14.3k
    splitMBB(&MBB);
179
12.1k
180
12.1k
  MF->RenumberBlocks();
181
12.1k
  MBBInfos.clear();
182
12.1k
  MBBInfos.resize(MF->size());
183
12.1k
184
12.1k
  const MipsInstrInfo *TII =
185
12.1k
      static_cast<const MipsInstrInfo *>(MF->getSubtarget().getInstrInfo());
186
26.4k
  for (unsigned I = 0, E = MBBInfos.size(); I < E; 
++I14.3k
) {
187
14.3k
    MachineBasicBlock *MBB = MF->getBlockNumbered(I);
188
14.3k
189
14.3k
    // Compute size of MBB.
190
14.3k
    for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
191
130k
         MI != MBB->instr_end(); 
++MI116k
)
192
116k
      MBBInfos[I].Size += TII->getInstSizeInBytes(*MI);
193
14.3k
194
14.3k
    // Search for MBB's branch instruction.
195
14.3k
    ReverseIter End = MBB->rend();
196
14.3k
    ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
197
14.3k
198
14.3k
    if ((Br != End) && 
!Br->isIndirectBranch()14.2k
&&
199
14.3k
        
(13.1k
Br->isConditionalBranch()13.1k
||
(12.0k
Br->isUnconditionalBranch()12.0k
&&
IsPIC179
)))
200
1.17k
      MBBInfos[I].Br = &*Br;
201
14.3k
  }
202
12.1k
}
203
204
// Compute offset of branch in number of bytes.
205
1.17k
int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
206
1.17k
  int64_t Offset = 0;
207
1.17k
  int ThisMBB = Br->getParent()->getNumber();
208
1.17k
  int TargetMBB = getTargetMBB(*Br)->getNumber();
209
1.17k
210
1.17k
  // Compute offset of a forward branch.
211
1.17k
  if (ThisMBB < TargetMBB) {
212
1.84k
    for (int N = ThisMBB + 1; N < TargetMBB; 
++N1.13k
)
213
1.13k
      Offset += MBBInfos[N].Size;
214
710
215
710
    return Offset + 4;
216
710
  }
217
468
218
468
  // Compute offset of a backward branch.
219
1.42k
  
for (int N = ThisMBB; 468
N >= TargetMBB;
--N959
)
220
959
    Offset += MBBInfos[N].Size;
221
468
222
468
  return -Offset + 4;
223
468
}
224
225
// Replace Br with a branch which has the opposite condition code and a
226
// MachineBasicBlock operand MBBOpnd.
227
void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
228
                                   const DebugLoc &DL,
229
167
                                   MachineBasicBlock *MBBOpnd) {
230
167
  const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
231
167
      MBB.getParent()->getSubtarget().getInstrInfo());
232
167
  unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
233
167
  const MCInstrDesc &NewDesc = TII->get(NewOpc);
234
167
235
167
  MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
236
167
237
390
  for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; 
++I223
) {
238
390
    MachineOperand &MO = Br->getOperand(I);
239
390
240
390
    if (!MO.isReg()) {
241
167
      assert(MO.isMBB() && "MBB operand expected.");
242
167
      break;
243
167
    }
244
223
245
223
    MIB.addReg(MO.getReg());
246
223
  }
247
167
248
167
  MIB.addMBB(MBBOpnd);
249
167
250
167
  if (Br->hasDelaySlot()) {
251
78
    // Bundle the instruction in the delay slot to the newly created branch
252
78
    // and erase the original branch.
253
78
    assert(Br->isBundledWithSucc());
254
78
    MachineBasicBlock::instr_iterator II = Br.getInstrIterator();
255
78
    MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
256
78
  }
257
167
  Br->eraseFromParent();
258
167
}
259
260
// Expand branch instructions to long branches.
261
// TODO: This function has to be fixed for beqz16 and bnez16, because it
262
// currently assumes that all branches have 16-bit offsets, and will produce
263
// wrong code if branches whose allowed offsets are [-128, -126, ..., 126]
264
// are present.
265
167
void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
266
167
  MachineBasicBlock::iterator Pos;
267
167
  MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
268
167
  DebugLoc DL = I.Br->getDebugLoc();
269
167
  const BasicBlock *BB = MBB->getBasicBlock();
270
167
  MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
271
167
  MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
272
167
  const MipsSubtarget &Subtarget =
273
167
      static_cast<const MipsSubtarget &>(MF->getSubtarget());
274
167
  const MipsInstrInfo *TII =
275
167
      static_cast<const MipsInstrInfo *>(Subtarget.getInstrInfo());
276
167
277
167
  MF->insert(FallThroughMBB, LongBrMBB);
278
167
  MBB->replaceSuccessor(TgtMBB, LongBrMBB);
279
167
280
167
  if (IsPIC) {
281
83
    MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
282
83
    MF->insert(FallThroughMBB, BalTgtMBB);
283
83
    LongBrMBB->addSuccessor(BalTgtMBB);
284
83
    BalTgtMBB->addSuccessor(TgtMBB);
285
83
286
83
    // We must select between the MIPS32r6/MIPS64r6 BALC (which is a normal
287
83
    // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
288
83
    // pseudo-instruction wrapping BGEZAL).
289
83
    const unsigned BalOp =
290
83
        Subtarget.hasMips32r6()
291
83
            ? 
Subtarget.inMicroMipsMode() 33
?
Mips::BALC_MMR615
:
Mips::BALC18
292
83
            : 
Subtarget.inMicroMipsMode() 50
?
Mips::BAL_BR_MM10
:
Mips::BAL_BR40
;
293
83
294
83
    if (!ABI.IsN64()) {
295
52
      // Pre R6:
296
52
      // $longbr:
297
52
      //  addiu $sp, $sp, -8
298
52
      //  sw $ra, 0($sp)
299
52
      //  lui $at, %hi($tgt - $baltgt)
300
52
      //  bal $baltgt
301
52
      //  addiu $at, $at, %lo($tgt - $baltgt)
302
52
      // $baltgt:
303
52
      //  addu $at, $ra, $at
304
52
      //  lw $ra, 0($sp)
305
52
      //  jr $at
306
52
      //  addiu $sp, $sp, 8
307
52
      // $fallthrough:
308
52
      //
309
52
310
52
      // R6:
311
52
      // $longbr:
312
52
      //  addiu $sp, $sp, -8
313
52
      //  sw $ra, 0($sp)
314
52
      //  lui $at, %hi($tgt - $baltgt)
315
52
      //  addiu $at, $at, %lo($tgt - $baltgt)
316
52
      //  balc $baltgt
317
52
      // $baltgt:
318
52
      //  addu $at, $ra, $at
319
52
      //  lw $ra, 0($sp)
320
52
      //  addiu $sp, $sp, 8
321
52
      //  jic $at, 0
322
52
      // $fallthrough:
323
52
324
52
      Pos = LongBrMBB->begin();
325
52
326
52
      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
327
52
        .addReg(Mips::SP).addImm(-8);
328
52
      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
329
52
        .addReg(Mips::SP).addImm(0);
330
52
331
52
      // LUi and ADDiu instructions create 32-bit offset of the target basic
332
52
      // block from the target of BAL(C) instruction.  We cannot use immediate
333
52
      // value for this offset because it cannot be determined accurately when
334
52
      // the program has inline assembly statements.  We therefore use the
335
52
      // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
336
52
      // are resolved during the fixup, so the values will always be correct.
337
52
      //
338
52
      // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
339
52
      // expressions at this point (it is possible only at the MC layer),
340
52
      // we replace LUi and ADDiu with pseudo instructions
341
52
      // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
342
52
      // blocks as operands to these instructions.  When lowering these pseudo
343
52
      // instructions to LUi and ADDiu in the MC layer, we will create
344
52
      // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
345
52
      // operands to lowered instructions.
346
52
347
52
      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
348
52
        .addMBB(TgtMBB).addMBB(BalTgtMBB);
349
52
350
52
      MachineInstrBuilder BalInstr =
351
52
          BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
352
52
      MachineInstrBuilder ADDiuInstr =
353
52
          BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
354
52
              .addReg(Mips::AT)
355
52
              .addMBB(TgtMBB)
356
52
              .addMBB(BalTgtMBB);
357
52
      if (Subtarget.hasMips32r6()) {
358
31
        LongBrMBB->insert(Pos, ADDiuInstr);
359
31
        LongBrMBB->insert(Pos, BalInstr);
360
31
      } else {
361
21
        LongBrMBB->insert(Pos, BalInstr);
362
21
        LongBrMBB->insert(Pos, ADDiuInstr);
363
21
        LongBrMBB->rbegin()->bundleWithPred();
364
21
      }
365
52
366
52
      Pos = BalTgtMBB->begin();
367
52
368
52
      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
369
52
        .addReg(Mips::RA).addReg(Mips::AT);
370
52
      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
371
52
        .addReg(Mips::SP).addImm(0);
372
52
      if (Subtarget.isTargetNaCl())
373
1
        // Bundle-align the target of indirect branch JR.
374
1
        TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
375
52
376
52
      // In NaCl, modifying the sp is not allowed in branch delay slot.
377
52
      // For MIPS32R6, we can skip using a delay slot branch.
378
52
      if (Subtarget.isTargetNaCl() ||
379
52
          
(51
Subtarget.hasMips32r6()51
&&
!Subtarget.useIndirectJumpsHazard()31
))
380
31
        BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
381
31
          .addReg(Mips::SP).addImm(8);
382
52
383
52
      if (Subtarget.hasMips32r6() && 
!Subtarget.useIndirectJumpsHazard()31
) {
384
30
        const unsigned JICOp =
385
30
            Subtarget.inMicroMipsMode() ? 
Mips::JIC_MMR615
:
Mips::JIC15
;
386
30
        BuildMI(*BalTgtMBB, Pos, DL, TII->get(JICOp))
387
30
            .addReg(Mips::AT)
388
30
            .addImm(0);
389
30
390
30
      } else {
391
22
        unsigned JROp =
392
22
            Subtarget.useIndirectJumpsHazard()
393
22
                ? 
(Subtarget.hasMips32r6() 2
?
Mips::JR_HB_R61
:
Mips::JR_HB1
)
394
22
                : 
Mips::JR20
;
395
22
        BuildMI(*BalTgtMBB, Pos, DL, TII->get(JROp)).addReg(Mips::AT);
396
22
397
22
        if (Subtarget.isTargetNaCl()) {
398
1
          BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
399
1
        } else
400
21
          BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
401
21
              .addReg(Mips::SP)
402
21
              .addImm(8);
403
22
404
22
        BalTgtMBB->rbegin()->bundleWithPred();
405
22
      }
406
52
    } else {
407
31
      // Pre R6:
408
31
      // $longbr:
409
31
      //  daddiu $sp, $sp, -16
410
31
      //  sd $ra, 0($sp)
411
31
      //  daddiu $at, $zero, %hi($tgt - $baltgt)
412
31
      //  dsll $at, $at, 16
413
31
      //  bal $baltgt
414
31
      //  daddiu $at, $at, %lo($tgt - $baltgt)
415
31
      // $baltgt:
416
31
      //  daddu $at, $ra, $at
417
31
      //  ld $ra, 0($sp)
418
31
      //  jr64 $at
419
31
      //  daddiu $sp, $sp, 16
420
31
      // $fallthrough:
421
31
422
31
      // R6:
423
31
      // $longbr:
424
31
      //  daddiu $sp, $sp, -16
425
31
      //  sd $ra, 0($sp)
426
31
      //  daddiu $at, $zero, %hi($tgt - $baltgt)
427
31
      //  dsll $at, $at, 16
428
31
      //  daddiu $at, $at, %lo($tgt - $baltgt)
429
31
      //  balc $baltgt
430
31
      // $baltgt:
431
31
      //  daddu $at, $ra, $at
432
31
      //  ld $ra, 0($sp)
433
31
      //  daddiu $sp, $sp, 16
434
31
      //  jic $at, 0
435
31
      // $fallthrough:
436
31
437
31
      // We assume the branch is within-function, and that offset is within
438
31
      // +/- 2GB.  High 32 bits will therefore always be zero.
439
31
440
31
      // Note that this will work even if the offset is negative, because
441
31
      // of the +1 modification that's added in that case.  For example, if the
442
31
      // offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is
443
31
      //
444
31
      // 0xFFFFFFFFFFF00000 + 0x80008000 = 0x000000007FF08000
445
31
      //
446
31
      // and the bits [47:32] are zero.  For %highest
447
31
      //
448
31
      // 0xFFFFFFFFFFF00000 + 0x800080008000 = 0x000080007FF08000
449
31
      //
450
31
      // and the bits [63:48] are zero.
451
31
452
31
      Pos = LongBrMBB->begin();
453
31
454
31
      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
455
31
        .addReg(Mips::SP_64).addImm(-16);
456
31
      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
457
31
        .addReg(Mips::SP_64).addImm(0);
458
31
      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
459
31
              Mips::AT_64).addReg(Mips::ZERO_64)
460
31
                          .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB);
461
31
      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
462
31
        .addReg(Mips::AT_64).addImm(16);
463
31
464
31
      MachineInstrBuilder BalInstr =
465
31
          BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
466
31
      MachineInstrBuilder DADDiuInstr =
467
31
          BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
468
31
              .addReg(Mips::AT_64)
469
31
              .addMBB(TgtMBB, MipsII::MO_ABS_LO)
470
31
              .addMBB(BalTgtMBB);
471
31
      if (Subtarget.hasMips32r6()) {
472
2
        LongBrMBB->insert(Pos, DADDiuInstr);
473
2
        LongBrMBB->insert(Pos, BalInstr);
474
29
      } else {
475
29
        LongBrMBB->insert(Pos, BalInstr);
476
29
        LongBrMBB->insert(Pos, DADDiuInstr);
477
29
        LongBrMBB->rbegin()->bundleWithPred();
478
29
      }
479
31
480
31
      Pos = BalTgtMBB->begin();
481
31
482
31
      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
483
31
        .addReg(Mips::RA_64).addReg(Mips::AT_64);
484
31
      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
485
31
        .addReg(Mips::SP_64).addImm(0);
486
31
487
31
      if (Subtarget.hasMips64r6() && 
!Subtarget.useIndirectJumpsHazard()2
) {
488
1
        BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
489
1
            .addReg(Mips::SP_64)
490
1
            .addImm(16);
491
1
        BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JIC64))
492
1
            .addReg(Mips::AT_64)
493
1
            .addImm(0);
494
30
      } else {
495
30
        unsigned JROp =
496
30
            Subtarget.useIndirectJumpsHazard()
497
30
                ? 
(Subtarget.hasMips32r6() 2
?
Mips::JR_HB64_R61
:
Mips::JR_HB641
)
498
30
                : 
Mips::JR6428
;
499
30
        BuildMI(*BalTgtMBB, Pos, DL, TII->get(JROp)).addReg(Mips::AT_64);
500
30
        BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
501
30
            .addReg(Mips::SP_64)
502
30
            .addImm(16);
503
30
        BalTgtMBB->rbegin()->bundleWithPred();
504
30
      }
505
31
    }
506
83
507
83
    assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
508
84
  } else {
509
84
    // Pre R6:                  R6:
510
84
    // $longbr:                 $longbr:
511
84
    //  j $tgt                   bc $tgt
512
84
    //  nop                     $fallthrough
513
84
    // $fallthrough:
514
84
    //
515
84
    Pos = LongBrMBB->begin();
516
84
    LongBrMBB->addSuccessor(TgtMBB);
517
84
    if (Subtarget.hasMips32r6())
518
39
      BuildMI(*LongBrMBB, Pos, DL,
519
39
              TII->get(Subtarget.inMicroMipsMode() ? 
Mips::BC_MMR615
:
Mips::BC24
))
520
39
          .addMBB(TgtMBB);
521
45
    else
522
45
      MIBundleBuilder(*LongBrMBB, Pos)
523
45
        .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
524
45
        .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
525
84
526
84
    assert(LongBrMBB->size() == LongBranchSeqSize);
527
84
  }
528
167
529
167
  if (I.Br->isUnconditionalBranch()) {
530
0
    // Change branch destination.
531
0
    assert(I.Br->getDesc().getNumOperands() == 1);
532
0
    I.Br->RemoveOperand(0);
533
0
    I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
534
0
  } else
535
167
    // Change branch destination and reverse condition.
536
167
    replaceBranch(*MBB, I.Br, DL, &*FallThroughMBB);
537
167
}
538
539
1.78k
static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
540
1.78k
  MachineBasicBlock &MBB = F.front();
541
1.78k
  MachineBasicBlock::iterator I = MBB.begin();
542
1.78k
  DebugLoc DL = MBB.findDebugLoc(MBB.begin());
543
1.78k
  BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
544
1.78k
    .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
545
1.78k
  BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
546
1.78k
    .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
547
1.78k
  MBB.removeLiveIn(Mips::V0);
548
1.78k
}
549
550
12.5k
bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
551
12.5k
  const MipsSubtarget &STI =
552
12.5k
      static_cast<const MipsSubtarget &>(F.getSubtarget());
553
12.5k
  const MipsInstrInfo *TII =
554
12.5k
      static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
555
12.5k
556
12.5k
  const TargetMachine& TM = F.getTarget();
557
12.5k
  IsPIC = TM.isPositionIndependent();
558
12.5k
  ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
559
12.5k
560
12.5k
  LongBranchSeqSize = IsPIC ? 
((5.09k
ABI.IsN64()5.09k
||
STI.isTargetNaCl()3.22k
) ?
101.87k
:
93.21k
)
561
12.5k
                          : 
(STI.hasMips32r6() 7.42k
?
1925
:
26.50k
);
562
12.5k
563
12.5k
  if (STI.inMips16Mode() || 
!STI.enableLongBranchPass()12.1k
)
564
380
    return false;
565
12.1k
  if (IsPIC && 
static_cast<const MipsTargetMachine &>(TM).getABI().IsO32()4.88k
&&
566
12.1k
      
F.getInfo<MipsFunctionInfo>()->globalBaseRegSet()2.66k
)
567
1.78k
    emitGPDisp(F, TII);
568
12.1k
569
12.1k
  if (SkipLongBranch)
570
0
    return true;
571
12.1k
572
12.1k
  MF = &F;
573
12.1k
  initMBBInfo();
574
12.1k
575
12.1k
  SmallVectorImpl<MBBInfo>::iterator I, E = MBBInfos.end();
576
12.1k
  bool EverMadeChange = false, MadeChange = true;
577
12.1k
578
24.4k
  while (MadeChange) {
579
12.3k
    MadeChange = false;
580
12.3k
581
27.1k
    for (I = MBBInfos.begin(); I != E; 
++I14.8k
) {
582
14.8k
      // Skip if this MBB doesn't have a branch or the branch has already been
583
14.8k
      // converted to a long branch.
584
14.8k
      if (!I->Br || 
I->HasLongBranch1.34k
)
585
13.6k
        continue;
586
1.17k
587
1.17k
      int64_t Offset = computeOffset(I->Br);
588
1.17k
589
1.17k
      if (STI.isTargetNaCl()) {
590
2
        // The offset calculation does not include sandboxing instructions
591
2
        // that will be added later in the MC layer.  Since at this point we
592
2
        // don't know the exact amount of code that "sandboxing" will add, we
593
2
        // conservatively estimate that code will not grow more than 100%.
594
2
        Offset *= 2;
595
2
      }
596
1.17k
597
1.17k
      // Check if offset fits into the immediate field of the branch.
598
1.17k
      if (!ForceLongBranch &&
599
1.17k
          
TII->isBranchOffsetInRange(I->Br->getOpcode(), Offset)1.15k
)
600
1.01k
        continue;
601
167
602
167
      I->HasLongBranch = true;
603
167
      I->Size += LongBranchSeqSize * 4;
604
167
      ++LongBranches;
605
167
      EverMadeChange = MadeChange = true;
606
167
    }
607
12.3k
  }
608
12.1k
609
12.1k
  if (!EverMadeChange)
610
11.9k
    return true;
611
167
612
167
  // Compute basic block addresses.
613
167
  if (IsPIC) {
614
83
    uint64_t Address = 0;
615
83
616
332
    for (I = MBBInfos.begin(); I != E; 
Address += I->Size, ++I249
)
617
249
      I->Address = Address;
618
83
  }
619
167
620
167
  // Do the expansion.
621
669
  for (I = MBBInfos.begin(); I != E; 
++I502
)
622
502
    if (I->HasLongBranch)
623
167
      expandToLongBranch(*I);
624
167
625
167
  MF->RenumberBlocks();
626
167
627
167
  return true;
628
167
}
629
630
/// createMipsLongBranchPass - Returns a pass that converts branches to long
631
/// branches.
632
1.86k
FunctionPass *llvm::createMipsLongBranchPass() { return new MipsLongBranch(); }