Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
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//===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsRegisterInfo.h"
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "Mips.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "mips-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "MipsGenRegisterInfo.inc"
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11.3k
MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
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0
unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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const TargetRegisterClass *
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MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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140k
                                     unsigned Kind) const {
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140k
  MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
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140k
  MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
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140k
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140k
  switch (PtrClassKind) {
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140k
  case MipsPtrClass::Default:
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136k
    return ABI.ArePtrs64bit() ? 
&Mips::GPR64RegClass42.6k
:
&Mips::GPR32RegClass93.9k
;
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140k
  case MipsPtrClass::GPR16MM:
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3.59k
    return &Mips::GPRMM16RegClass;
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140k
  case MipsPtrClass::StackPointer:
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156
    return ABI.ArePtrs64bit() ? 
&Mips::SP64RegClass0
: &Mips::SP32RegClass;
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140k
  case MipsPtrClass::GlobalPointer:
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0
    return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
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0
  }
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0
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0
  llvm_unreachable("Unknown pointer kind");
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0
}
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unsigned
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MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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978k
                                      MachineFunction &MF) const {
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978k
  switch (RC->getID()) {
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978k
  default:
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894k
    return 0;
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978k
  case Mips::GPR32RegClassID:
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41.9k
  case Mips::GPR64RegClassID:
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41.9k
  case Mips::DSPRRegClassID: {
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41.9k
    const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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41.9k
    return 28 - TFI->hasFP(MF);
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41.9k
  }
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41.9k
  case Mips::FGR32RegClassID:
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13.9k
    return 32;
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41.9k
  case Mips::AFGR64RegClassID:
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13.9k
    return 16;
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41.9k
  case Mips::FGR64RegClassID:
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13.9k
    return 32;
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978k
  }
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978k
}
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//===----------------------------------------------------------------------===//
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// Callee Saved Registers methods
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//===----------------------------------------------------------------------===//
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/// Mips Callee Saved Registers
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const MCPhysReg *
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135k
MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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  const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
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  const Function &F = MF->getFunction();
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  if (F.hasFnAttribute("interrupt")) {
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    if (Subtarget.hasMips64())
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7
      return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
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                                     : 
CSR_Interrupt_64_SaveList0
;
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    else
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      return Subtarget.hasMips32r6() ? 
CSR_Interrupt_32R6_SaveList0
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                                     : CSR_Interrupt_32_SaveList;
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  }
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  if (Subtarget.isSingleFloat())
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    return CSR_SingleFloatOnly_SaveList;
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135k
  if (Subtarget.isABI_N64())
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44.4k
    return CSR_N64_SaveList;
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91.2k
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91.2k
  if (Subtarget.isABI_N32())
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5.33k
    return CSR_N32_SaveList;
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85.9k
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85.9k
  if (Subtarget.isFP64bit())
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    return CSR_O32_FP64_SaveList;
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48.6k
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48.6k
  if (Subtarget.isFPXX())
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    return CSR_O32_FPXX_SaveList;
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48.4k
  return CSR_O32_SaveList;
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}
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const uint32_t *
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MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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                                       CallingConv::ID) const {
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  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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  if (Subtarget.isSingleFloat())
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    return CSR_SingleFloatOnly_RegMask;
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  if (Subtarget.isABI_N64())
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    return CSR_N64_RegMask;
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2.43k
  if (Subtarget.isABI_N32())
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    return CSR_N32_RegMask;
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2.34k
  if (Subtarget.isFP64bit())
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    return CSR_O32_FP64_RegMask;
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1.96k
  if (Subtarget.isFPXX())
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8
    return CSR_O32_FPXX_RegMask;
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1.95k
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1.95k
  return CSR_O32_RegMask;
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}
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const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
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  return CSR_Mips16RetHelper_RegMask;
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30
}
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BitVector MipsRegisterInfo::
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43.0k
getReservedRegs(const MachineFunction &MF) const {
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  static const MCPhysReg ReservedGPR32[] = {
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    Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
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43.0k
  };
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43.0k
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43.0k
  static const MCPhysReg ReservedGPR64[] = {
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    Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
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43.0k
  };
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43.0k
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  BitVector Reserved(getNumRegs());
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43.0k
  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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43.0k
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215k
  for (unsigned I = 0; I < array_lengthof(ReservedGPR32); 
++I172k
)
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    Reserved.set(ReservedGPR32[I]);
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43.0k
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43.0k
  // Reserve registers for the NaCl sandbox.
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  if (Subtarget.isTargetNaCl()) {
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    Reserved.set(Mips::T6);   // Reserved for control flow mask.
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    Reserved.set(Mips::T7);   // Reserved for memory access mask.
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    Reserved.set(Mips::T8);   // Reserved for thread pointer.
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  }
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215k
  for (unsigned I = 0; I < array_lengthof(ReservedGPR64); 
++I172k
)
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172k
    Reserved.set(ReservedGPR64[I]);
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43.0k
  // For mno-abicalls, GP is a program invariant!
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  if (!Subtarget.isABICalls()) {
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6.73k
    Reserved.set(Mips::GP);
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    Reserved.set(Mips::GP_64);
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6.73k
  }
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43.0k
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43.0k
  if (Subtarget.isFP64bit()) {
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    // Reserve all registers in AFGR64.
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26.5k
    for (MCPhysReg Reg : Mips::AFGR64RegClass)
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      Reserved.set(Reg);
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26.5k
  } else {
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    // Reserve all registers in FGR64.
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    for (MCPhysReg Reg : Mips::FGR64RegClass)
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      Reserved.set(Reg);
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  }
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43.0k
  // Reserve FP if this function should have a dedicated frame pointer register.
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43.0k
  if (Subtarget.getFrameLowering()->hasFP(MF)) {
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    if (Subtarget.inMips16Mode())
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719
      Reserved.set(Mips::S0);
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990
    else {
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      Reserved.set(Mips::FP);
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      Reserved.set(Mips::FP_64);
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990
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      // Reserve the base register if we need to both realign the stack and
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      // allocate variable-sized objects at runtime. This should test the
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      // same conditions as MipsFrameLowering::hasBP().
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      if (needsStackRealignment(MF) &&
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MF.getFrameInfo().hasVarSizedObjects()600
) {
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        Reserved.set(Mips::S7);
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        Reserved.set(Mips::S7_64);
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      }
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    }
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  }
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43.0k
  // Reserve hardware registers.
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  Reserved.set(Mips::HWR29);
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  // Reserve DSP control register.
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  Reserved.set(Mips::DSPPos);
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  Reserved.set(Mips::DSPSCount);
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  Reserved.set(Mips::DSPCarry);
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  Reserved.set(Mips::DSPEFI);
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  Reserved.set(Mips::DSPOutFlag);
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  // Reserve MSA control registers.
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  for (MCPhysReg Reg : Mips::MSACtrlRegClass)
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1.37M
    Reserved.set(Reg);
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43.0k
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43.0k
  // Reserve RA if in mips16 mode.
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  if (Subtarget.inMips16Mode()) {
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2.01k
    const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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    Reserved.set(Mips::RA);
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2.01k
    Reserved.set(Mips::RA_64);
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2.01k
    Reserved.set(Mips::T0);
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2.01k
    Reserved.set(Mips::T1);
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2.01k
    if (MF.getFunction().hasFnAttribute("saveS2") || 
MipsFI->hasSaveS2()1.71k
)
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      Reserved.set(Mips::S2);
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2.01k
  }
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43.0k
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43.0k
  // Reserve GP if small section is used.
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43.0k
  if (Subtarget.useSmallSection()) {
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45
    Reserved.set(Mips::GP);
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    Reserved.set(Mips::GP_64);
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  }
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43.0k
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43.0k
  return Reserved;
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43.0k
}
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bool
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0
MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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  return true;
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0
}
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bool
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12.3k
MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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12.3k
  return true;
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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14.9k
                    unsigned FIOperandNum, RegScavenger *RS) const {
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14.9k
  MachineInstr &MI = *II;
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14.9k
  MachineFunction &MF = *MI.getParent()->getParent();
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14.9k
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14.9k
  LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
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14.9k
             errs() << "<--------->\n"
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14.9k
                    << MI);
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14.9k
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14.9k
  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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14.9k
  uint64_t stackSize = MF.getFrameInfo().getStackSize();
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14.9k
  int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
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14.9k
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14.9k
  LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
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14.9k
                    << "spOffset   : " << spOffset << "\n"
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14.9k
                    << "stackSize  : " << stackSize << "\n"
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14.9k
                    << "alignment  : "
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14.9k
                    << MF.getFrameInfo().getObjectAlignment(FrameIndex)
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14.9k
                    << "\n");
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14.9k
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14.9k
  eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
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14.9k
}
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Register MipsRegisterInfo::
281
18.6k
getFrameRegister(const MachineFunction &MF) const {
282
18.6k
  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
283
18.6k
  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
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18.6k
  bool IsN64 =
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18.6k
      static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
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18.6k
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18.6k
  if (Subtarget.inMips16Mode())
288
380
    return TFI->hasFP(MF) ? 
Mips::S0120
:
Mips::SP260
;
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18.2k
  else
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18.2k
    return TFI->hasFP(MF) ? 
(IsN64 641
?
Mips::FP_64271
:
Mips::FP370
) :
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18.2k
                            
(IsN64 17.6k
?
Mips::SP_645.31k
:
Mips::SP12.3k
);
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18.6k
}
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4.50k
bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
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4.50k
  // Avoid realigning functions that explicitly do not want to be realigned.
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4.50k
  // Normally, we should report an error when a function should be dynamically
297
4.50k
  // realigned but also has the attribute no-realign-stack. Unfortunately,
298
4.50k
  // with this attribute, MachineFrameInfo clamps each new object's alignment
299
4.50k
  // to that of the stack's alignment as specified by the ABI. As a result,
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4.50k
  // the information of whether we have objects with larger alignment
301
4.50k
  // requirement than the stack's alignment is already lost at this point.
302
4.50k
  if (!TargetRegisterInfo::canRealignStack(MF))
303
0
    return false;
304
4.50k
305
4.50k
  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
306
4.50k
  unsigned FP = Subtarget.isGP32bit() ? 
Mips::FP3.92k
:
Mips::FP_64582
;
307
4.50k
  unsigned BP = Subtarget.isGP32bit() ? 
Mips::S73.92k
:
Mips::S7_64582
;
308
4.50k
309
4.50k
  // Support dynamic stack realignment for all targets except Mips16.
310
4.50k
  if (Subtarget.inMips16Mode())
311
0
    return false;
312
4.50k
313
4.50k
  // We can't perform dynamic stack realignment if we can't reserve the
314
4.50k
  // frame pointer register.
315
4.50k
  if (!MF.getRegInfo().canReserveReg(FP))
316
163
    return false;
317
4.34k
318
4.34k
  // We can realign the stack if we know the maximum call frame size and we
319
4.34k
  // don't have variable sized objects.
320
4.34k
  if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
321
3.97k
    return true;
322
366
323
366
  // We have to reserve the base pointer register in the presence of variable
324
366
  // sized objects.
325
366
  return MF.getRegInfo().canReserveReg(BP);
326
366
}