/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
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1 | | //===- MipsSEFrameLowering.cpp - Mips32/64 Frame Information --------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file contains the Mips32/64 implementation of TargetFrameLowering class. |
10 | | // |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #include "MipsSEFrameLowering.h" |
14 | | #include "MCTargetDesc/MipsABIInfo.h" |
15 | | #include "MipsMachineFunction.h" |
16 | | #include "MipsRegisterInfo.h" |
17 | | #include "MipsSEInstrInfo.h" |
18 | | #include "MipsSubtarget.h" |
19 | | #include "llvm/ADT/BitVector.h" |
20 | | #include "llvm/ADT/StringRef.h" |
21 | | #include "llvm/ADT/StringSwitch.h" |
22 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
23 | | #include "llvm/CodeGen/MachineFrameInfo.h" |
24 | | #include "llvm/CodeGen/MachineFunction.h" |
25 | | #include "llvm/CodeGen/MachineInstr.h" |
26 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
27 | | #include "llvm/CodeGen/MachineModuleInfo.h" |
28 | | #include "llvm/CodeGen/MachineOperand.h" |
29 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
30 | | #include "llvm/CodeGen/RegisterScavenging.h" |
31 | | #include "llvm/CodeGen/TargetInstrInfo.h" |
32 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
33 | | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
34 | | #include "llvm/IR/DebugLoc.h" |
35 | | #include "llvm/IR/Function.h" |
36 | | #include "llvm/MC/MCDwarf.h" |
37 | | #include "llvm/MC/MCRegisterInfo.h" |
38 | | #include "llvm/MC/MachineLocation.h" |
39 | | #include "llvm/Support/CodeGen.h" |
40 | | #include "llvm/Support/ErrorHandling.h" |
41 | | #include "llvm/Support/MathExtras.h" |
42 | | #include <cassert> |
43 | | #include <cstdint> |
44 | | #include <utility> |
45 | | #include <vector> |
46 | | |
47 | | using namespace llvm; |
48 | | |
49 | 3.16k | static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) { |
50 | 3.16k | if (Mips::ACC64RegClass.contains(Src)) |
51 | 1 | return std::make_pair((unsigned)Mips::PseudoMFHI, |
52 | 1 | (unsigned)Mips::PseudoMFLO); |
53 | 3.15k | |
54 | 3.15k | if (Mips::ACC64DSPRegClass.contains(Src)) |
55 | 0 | return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); |
56 | 3.15k | |
57 | 3.15k | if (Mips::ACC128RegClass.contains(Src)) |
58 | 0 | return std::make_pair((unsigned)Mips::PseudoMFHI64, |
59 | 0 | (unsigned)Mips::PseudoMFLO64); |
60 | 3.15k | |
61 | 3.15k | return std::make_pair(0, 0); |
62 | 3.15k | } |
63 | | |
64 | | namespace { |
65 | | |
66 | | /// Helper class to expand pseudos. |
67 | | class ExpandPseudo { |
68 | | public: |
69 | | ExpandPseudo(MachineFunction &MF); |
70 | | bool expand(); |
71 | | |
72 | | private: |
73 | | using Iter = MachineBasicBlock::iterator; |
74 | | |
75 | | bool expandInstr(MachineBasicBlock &MBB, Iter I); |
76 | | void expandLoadCCond(MachineBasicBlock &MBB, Iter I); |
77 | | void expandStoreCCond(MachineBasicBlock &MBB, Iter I); |
78 | | void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); |
79 | | void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, |
80 | | unsigned MFLoOpc, unsigned RegSize); |
81 | | bool expandCopy(MachineBasicBlock &MBB, Iter I); |
82 | | bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, |
83 | | unsigned MFLoOpc); |
84 | | bool expandBuildPairF64(MachineBasicBlock &MBB, |
85 | | MachineBasicBlock::iterator I, bool FP64) const; |
86 | | bool expandExtractElementF64(MachineBasicBlock &MBB, |
87 | | MachineBasicBlock::iterator I, bool FP64) const; |
88 | | |
89 | | MachineFunction &MF; |
90 | | MachineRegisterInfo &MRI; |
91 | | const MipsSubtarget &Subtarget; |
92 | | const MipsSEInstrInfo &TII; |
93 | | const MipsRegisterInfo &RegInfo; |
94 | | }; |
95 | | |
96 | | } // end anonymous namespace |
97 | | |
98 | | ExpandPseudo::ExpandPseudo(MachineFunction &MF_) |
99 | | : MF(MF_), MRI(MF.getRegInfo()), |
100 | | Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())), |
101 | | TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())), |
102 | 13.0k | RegInfo(*Subtarget.getRegisterInfo()) {} |
103 | | |
104 | 13.0k | bool ExpandPseudo::expand() { |
105 | 13.0k | bool Expanded = false; |
106 | 13.0k | |
107 | 15.0k | for (auto &MBB : MF) { |
108 | 109k | for (Iter I = MBB.begin(), End = MBB.end(); I != End;) |
109 | 94.4k | Expanded |= expandInstr(MBB, I++); |
110 | 15.0k | } |
111 | 13.0k | |
112 | 13.0k | return Expanded; |
113 | 13.0k | } |
114 | | |
115 | 94.4k | bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { |
116 | 94.4k | switch(I->getOpcode()) { |
117 | 94.4k | case Mips::LOAD_CCOND_DSP: |
118 | 1 | expandLoadCCond(MBB, I); |
119 | 1 | break; |
120 | 94.4k | case Mips::STORE_CCOND_DSP: |
121 | 1 | expandStoreCCond(MBB, I); |
122 | 1 | break; |
123 | 94.4k | case Mips::LOAD_ACC64: |
124 | 0 | case Mips::LOAD_ACC64DSP: |
125 | 0 | expandLoadACC(MBB, I, 4); |
126 | 0 | break; |
127 | 2 | case Mips::LOAD_ACC128: |
128 | 2 | expandLoadACC(MBB, I, 8); |
129 | 2 | break; |
130 | 0 | case Mips::STORE_ACC64: |
131 | 0 | expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4); |
132 | 0 | break; |
133 | 0 | case Mips::STORE_ACC64DSP: |
134 | 0 | expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4); |
135 | 0 | break; |
136 | 2 | case Mips::STORE_ACC128: |
137 | 2 | expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8); |
138 | 2 | break; |
139 | 141 | case Mips::BuildPairF64: |
140 | 141 | if (expandBuildPairF64(MBB, I, false)) |
141 | 8 | MBB.erase(I); |
142 | 141 | return false; |
143 | 61 | case Mips::BuildPairF64_64: |
144 | 61 | if (expandBuildPairF64(MBB, I, true)) |
145 | 13 | MBB.erase(I); |
146 | 61 | return false; |
147 | 140 | case Mips::ExtractElementF64: |
148 | 140 | if (expandExtractElementF64(MBB, I, false)) |
149 | 19 | MBB.erase(I); |
150 | 140 | return false; |
151 | 60 | case Mips::ExtractElementF64_64: |
152 | 60 | if (expandExtractElementF64(MBB, I, true)) |
153 | 13 | MBB.erase(I); |
154 | 60 | return false; |
155 | 3.16k | case TargetOpcode::COPY: |
156 | 3.16k | if (!expandCopy(MBB, I)) |
157 | 3.15k | return false; |
158 | 1 | break; |
159 | 90.8k | default: |
160 | 90.8k | return false; |
161 | 7 | } |
162 | 7 | |
163 | 7 | MBB.erase(I); |
164 | 7 | return true; |
165 | 7 | } |
166 | | |
167 | 1 | void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { |
168 | 1 | // load $vr, FI |
169 | 1 | // copy ccond, $vr |
170 | 1 | |
171 | 1 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
172 | 1 | |
173 | 1 | const TargetRegisterClass *RC = RegInfo.intRegClass(4); |
174 | 1 | unsigned VR = MRI.createVirtualRegister(RC); |
175 | 1 | unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
176 | 1 | |
177 | 1 | TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); |
178 | 1 | BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) |
179 | 1 | .addReg(VR, RegState::Kill); |
180 | 1 | } |
181 | | |
182 | 1 | void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { |
183 | 1 | // copy $vr, ccond |
184 | 1 | // store $vr, FI |
185 | 1 | |
186 | 1 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
187 | 1 | |
188 | 1 | const TargetRegisterClass *RC = RegInfo.intRegClass(4); |
189 | 1 | unsigned VR = MRI.createVirtualRegister(RC); |
190 | 1 | unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
191 | 1 | |
192 | 1 | BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) |
193 | 1 | .addReg(Src, getKillRegState(I->getOperand(0).isKill())); |
194 | 1 | TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); |
195 | 1 | } |
196 | | |
197 | | void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, |
198 | 2 | unsigned RegSize) { |
199 | 2 | // load $vr0, FI |
200 | 2 | // copy lo, $vr0 |
201 | 2 | // load $vr1, FI + 4 |
202 | 2 | // copy hi, $vr1 |
203 | 2 | |
204 | 2 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
205 | 2 | |
206 | 2 | const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); |
207 | 2 | unsigned VR0 = MRI.createVirtualRegister(RC); |
208 | 2 | unsigned VR1 = MRI.createVirtualRegister(RC); |
209 | 2 | unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
210 | 2 | unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); |
211 | 2 | unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); |
212 | 2 | DebugLoc DL = I->getDebugLoc(); |
213 | 2 | const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); |
214 | 2 | |
215 | 2 | TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); |
216 | 2 | BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); |
217 | 2 | TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); |
218 | 2 | BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); |
219 | 2 | } |
220 | | |
221 | | void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I, |
222 | | unsigned MFHiOpc, unsigned MFLoOpc, |
223 | 2 | unsigned RegSize) { |
224 | 2 | // mflo $vr0, src |
225 | 2 | // store $vr0, FI |
226 | 2 | // mfhi $vr1, src |
227 | 2 | // store $vr1, FI + 4 |
228 | 2 | |
229 | 2 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
230 | 2 | |
231 | 2 | const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); |
232 | 2 | unsigned VR0 = MRI.createVirtualRegister(RC); |
233 | 2 | unsigned VR1 = MRI.createVirtualRegister(RC); |
234 | 2 | unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
235 | 2 | unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); |
236 | 2 | DebugLoc DL = I->getDebugLoc(); |
237 | 2 | |
238 | 2 | BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); |
239 | 2 | TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0); |
240 | 2 | BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); |
241 | 2 | TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); |
242 | 2 | } |
243 | | |
244 | 3.16k | bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) { |
245 | 3.16k | unsigned Src = I->getOperand(1).getReg(); |
246 | 3.16k | std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src); |
247 | 3.16k | |
248 | 3.16k | if (!Opcodes.first) |
249 | 3.15k | return false; |
250 | 1 | |
251 | 1 | return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second); |
252 | 1 | } |
253 | | |
254 | | bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, |
255 | 1 | unsigned MFHiOpc, unsigned MFLoOpc) { |
256 | 1 | // mflo $vr0, src |
257 | 1 | // copy dst_lo, $vr0 |
258 | 1 | // mfhi $vr1, src |
259 | 1 | // copy dst_hi, $vr1 |
260 | 1 | |
261 | 1 | unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); |
262 | 1 | const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst); |
263 | 1 | unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16; |
264 | 1 | const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); |
265 | 1 | unsigned VR0 = MRI.createVirtualRegister(RC); |
266 | 1 | unsigned VR1 = MRI.createVirtualRegister(RC); |
267 | 1 | unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); |
268 | 1 | unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); |
269 | 1 | unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); |
270 | 1 | DebugLoc DL = I->getDebugLoc(); |
271 | 1 | |
272 | 1 | BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); |
273 | 1 | BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) |
274 | 1 | .addReg(VR0, RegState::Kill); |
275 | 1 | BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); |
276 | 1 | BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) |
277 | 1 | .addReg(VR1, RegState::Kill); |
278 | 1 | return true; |
279 | 1 | } |
280 | | |
281 | | /// This method expands the same instruction that MipsSEInstrInfo:: |
282 | | /// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not |
283 | | /// available and the case where the ABI is FP64A. It is implemented here |
284 | | /// because frame indexes are eliminated before MipsSEInstrInfo:: |
285 | | /// expandBuildPairF64 is called. |
286 | | bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, |
287 | | MachineBasicBlock::iterator I, |
288 | 202 | bool FP64) const { |
289 | 202 | // For fpxx and when mthc1 is not available, use: |
290 | 202 | // spill + reload via ldc1 |
291 | 202 | // |
292 | 202 | // The case where dmtc1 is available doesn't need to be handled here |
293 | 202 | // because it never creates a BuildPairF64 node. |
294 | 202 | // |
295 | 202 | // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence |
296 | 202 | // for odd-numbered double precision values (because the lower 32-bits is |
297 | 202 | // transferred with mtc1 which is redirected to the upper half of the even |
298 | 202 | // register). Unfortunately, we have to make this decision before register |
299 | 202 | // allocation so for now we use a spill/reload sequence for all |
300 | 202 | // double-precision values in regardless of being an odd/even register. |
301 | 202 | // |
302 | 202 | // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as |
303 | 202 | // implicit operand, so other passes (like ShrinkWrapping) are aware that |
304 | 202 | // stack is used. |
305 | 202 | if (I->getNumOperands() == 4 && I->getOperand(3).isReg()21 |
306 | 202 | && I->getOperand(3).getReg() == Mips::SP21 ) { |
307 | 21 | unsigned DstReg = I->getOperand(0).getReg(); |
308 | 21 | unsigned LoReg = I->getOperand(1).getReg(); |
309 | 21 | unsigned HiReg = I->getOperand(2).getReg(); |
310 | 21 | |
311 | 21 | // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are |
312 | 21 | // the cases where mthc1 is not available). 64-bit architectures and |
313 | 21 | // MIPS32r2 or later can use FGR64 though. |
314 | 21 | assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() || |
315 | 21 | !Subtarget.isFP64bit()); |
316 | 21 | |
317 | 21 | const TargetRegisterClass *RC = &Mips::GPR32RegClass; |
318 | 21 | const TargetRegisterClass *RC2 = |
319 | 21 | FP64 ? &Mips::FGR64RegClass13 : &Mips::AFGR64RegClass8 ; |
320 | 21 | |
321 | 21 | // We re-use the same spill slot each time so that the stack frame doesn't |
322 | 21 | // grow too much in functions with a large number of moves. |
323 | 21 | int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2); |
324 | 21 | if (!Subtarget.isLittle()) |
325 | 8 | std::swap(LoReg, HiReg); |
326 | 21 | TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, |
327 | 21 | &RegInfo, 0); |
328 | 21 | TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, |
329 | 21 | &RegInfo, 4); |
330 | 21 | TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0); |
331 | 21 | return true; |
332 | 21 | } |
333 | 181 | |
334 | 181 | return false; |
335 | 181 | } |
336 | | |
337 | | /// This method expands the same instruction that MipsSEInstrInfo:: |
338 | | /// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not |
339 | | /// available and the case where the ABI is FP64A. It is implemented here |
340 | | /// because frame indexes are eliminated before MipsSEInstrInfo:: |
341 | | /// expandExtractElementF64 is called. |
342 | | bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB, |
343 | | MachineBasicBlock::iterator I, |
344 | 200 | bool FP64) const { |
345 | 200 | const MachineOperand &Op1 = I->getOperand(1); |
346 | 200 | const MachineOperand &Op2 = I->getOperand(2); |
347 | 200 | |
348 | 200 | if ((Op1.isReg() && Op1.isUndef()) || (176 Op2.isReg()176 && Op2.isUndef()0 )) { |
349 | 24 | unsigned DstReg = I->getOperand(0).getReg(); |
350 | 24 | BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg); |
351 | 24 | return true; |
352 | 24 | } |
353 | 176 | |
354 | 176 | // For fpxx and when mfhc1 is not available, use: |
355 | 176 | // spill + reload via ldc1 |
356 | 176 | // |
357 | 176 | // The case where dmfc1 is available doesn't need to be handled here |
358 | 176 | // because it never creates a ExtractElementF64 node. |
359 | 176 | // |
360 | 176 | // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence |
361 | 176 | // for odd-numbered double precision values (because the lower 32-bits is |
362 | 176 | // transferred with mfc1 which is redirected to the upper half of the even |
363 | 176 | // register). Unfortunately, we have to make this decision before register |
364 | 176 | // allocation so for now we use a spill/reload sequence for all |
365 | 176 | // double-precision values in regardless of being an odd/even register. |
366 | 176 | // |
367 | 176 | // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as |
368 | 176 | // implicit operand, so other passes (like ShrinkWrapping) are aware that |
369 | 176 | // stack is used. |
370 | 176 | if (I->getNumOperands() == 4 && I->getOperand(3).isReg()8 |
371 | 176 | && I->getOperand(3).getReg() == Mips::SP8 ) { |
372 | 8 | unsigned DstReg = I->getOperand(0).getReg(); |
373 | 8 | unsigned SrcReg = Op1.getReg(); |
374 | 8 | unsigned N = Op2.getImm(); |
375 | 8 | int64_t Offset = 4 * (Subtarget.isLittle() ? N4 : (1 - N)4 ); |
376 | 8 | |
377 | 8 | // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are |
378 | 8 | // the cases where mfhc1 is not available). 64-bit architectures and |
379 | 8 | // MIPS32r2 or later can use FGR64 though. |
380 | 8 | assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() || |
381 | 8 | !Subtarget.isFP64bit()); |
382 | 8 | |
383 | 8 | const TargetRegisterClass *RC = |
384 | 8 | FP64 ? &Mips::FGR64RegClass5 : &Mips::AFGR64RegClass3 ; |
385 | 8 | const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; |
386 | 8 | |
387 | 8 | // We re-use the same spill slot each time so that the stack frame doesn't |
388 | 8 | // grow too much in functions with a large number of moves. |
389 | 8 | int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC); |
390 | 8 | TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); |
391 | 8 | TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); |
392 | 8 | return true; |
393 | 8 | } |
394 | 168 | |
395 | 168 | return false; |
396 | 168 | } |
397 | | |
398 | | MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) |
399 | 8.43k | : MipsFrameLowering(STI, STI.getStackAlignment()) {} |
400 | | |
401 | | void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, |
402 | 12.7k | MachineBasicBlock &MBB) const { |
403 | 12.7k | MachineFrameInfo &MFI = MF.getFrameInfo(); |
404 | 12.7k | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
405 | 12.7k | |
406 | 12.7k | const MipsSEInstrInfo &TII = |
407 | 12.7k | *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo()); |
408 | 12.7k | const MipsRegisterInfo &RegInfo = |
409 | 12.7k | *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo()); |
410 | 12.7k | |
411 | 12.7k | MachineBasicBlock::iterator MBBI = MBB.begin(); |
412 | 12.7k | DebugLoc dl; |
413 | 12.7k | MipsABIInfo ABI = STI.getABI(); |
414 | 12.7k | unsigned SP = ABI.GetStackPtr(); |
415 | 12.7k | unsigned FP = ABI.GetFramePtr(); |
416 | 12.7k | unsigned ZERO = ABI.GetNullPtr(); |
417 | 12.7k | unsigned MOVE = ABI.GetGPRMoveOp(); |
418 | 12.7k | unsigned ADDiu = ABI.GetPtrAddiuOp(); |
419 | 12.7k | unsigned AND = ABI.IsN64() ? Mips::AND644.16k : Mips::AND8.63k ; |
420 | 12.7k | |
421 | 12.7k | const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? |
422 | 8.63k | &Mips::GPR64RegClass4.16k : &Mips::GPR32RegClass; |
423 | 12.7k | |
424 | 12.7k | // First, compute final stack size. |
425 | 12.7k | uint64_t StackSize = MFI.getStackSize(); |
426 | 12.7k | |
427 | 12.7k | // No need to allocate space on the stack. |
428 | 12.7k | if (StackSize == 0 && !MFI.adjustsStack()10.2k ) return10.2k ; |
429 | 2.50k | |
430 | 2.50k | MachineModuleInfo &MMI = MF.getMMI(); |
431 | 2.50k | const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); |
432 | 2.50k | |
433 | 2.50k | // Adjust stack. |
434 | 2.50k | TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); |
435 | 2.50k | |
436 | 2.50k | // emit ".cfi_def_cfa_offset StackSize" |
437 | 2.50k | unsigned CFIIndex = MF.addFrameInst( |
438 | 2.50k | MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); |
439 | 2.50k | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
440 | 2.50k | .addCFIIndex(CFIIndex); |
441 | 2.50k | |
442 | 2.50k | if (MF.getFunction().hasFnAttribute("interrupt")) |
443 | 11 | emitInterruptPrologueStub(MF, MBB); |
444 | 2.50k | |
445 | 2.50k | const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); |
446 | 2.50k | |
447 | 2.50k | if (!CSI.empty()) { |
448 | 2.09k | // Find the instruction past the last instruction that saves a callee-saved |
449 | 2.09k | // register to the stack. |
450 | 5.87k | for (unsigned i = 0; i < CSI.size(); ++i3.78k ) |
451 | 3.78k | ++MBBI; |
452 | 2.09k | |
453 | 2.09k | // Iterate over list of callee-saved registers and emit .cfi_offset |
454 | 2.09k | // directives. |
455 | 2.09k | for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), |
456 | 5.87k | E = CSI.end(); I != E; ++I3.78k ) { |
457 | 3.78k | int64_t Offset = MFI.getObjectOffset(I->getFrameIdx()); |
458 | 3.78k | unsigned Reg = I->getReg(); |
459 | 3.78k | |
460 | 3.78k | // If Reg is a double precision register, emit two cfa_offsets, |
461 | 3.78k | // one for each of the paired single precision registers. |
462 | 3.78k | if (Mips::AFGR64RegClass.contains(Reg)) { |
463 | 107 | unsigned Reg0 = |
464 | 107 | MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); |
465 | 107 | unsigned Reg1 = |
466 | 107 | MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); |
467 | 107 | |
468 | 107 | if (!STI.isLittle()) |
469 | 30 | std::swap(Reg0, Reg1); |
470 | 107 | |
471 | 107 | unsigned CFIIndex = MF.addFrameInst( |
472 | 107 | MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); |
473 | 107 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
474 | 107 | .addCFIIndex(CFIIndex); |
475 | 107 | |
476 | 107 | CFIIndex = MF.addFrameInst( |
477 | 107 | MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); |
478 | 107 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
479 | 107 | .addCFIIndex(CFIIndex); |
480 | 3.67k | } else if (Mips::FGR64RegClass.contains(Reg)) { |
481 | 212 | unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); |
482 | 212 | unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; |
483 | 212 | |
484 | 212 | if (!STI.isLittle()) |
485 | 60 | std::swap(Reg0, Reg1); |
486 | 212 | |
487 | 212 | unsigned CFIIndex = MF.addFrameInst( |
488 | 212 | MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); |
489 | 212 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
490 | 212 | .addCFIIndex(CFIIndex); |
491 | 212 | |
492 | 212 | CFIIndex = MF.addFrameInst( |
493 | 212 | MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); |
494 | 212 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
495 | 212 | .addCFIIndex(CFIIndex); |
496 | 3.46k | } else { |
497 | 3.46k | // Reg is either in GPR32 or FGR32. |
498 | 3.46k | unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( |
499 | 3.46k | nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); |
500 | 3.46k | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
501 | 3.46k | .addCFIIndex(CFIIndex); |
502 | 3.46k | } |
503 | 3.78k | } |
504 | 2.09k | } |
505 | 2.50k | |
506 | 2.50k | if (MipsFI->callsEhReturn()) { |
507 | 14 | // Insert instructions that spill eh data registers. |
508 | 70 | for (int I = 0; I < 4; ++I56 ) { |
509 | 56 | if (!MBB.isLiveIn(ABI.GetEhDataReg(I))) |
510 | 28 | MBB.addLiveIn(ABI.GetEhDataReg(I)); |
511 | 56 | TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false, |
512 | 56 | MipsFI->getEhDataRegFI(I), RC, &RegInfo); |
513 | 56 | } |
514 | 14 | |
515 | 14 | // Emit .cfi_offset directives for eh data registers. |
516 | 70 | for (int I = 0; I < 4; ++I56 ) { |
517 | 56 | int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); |
518 | 56 | unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); |
519 | 56 | unsigned CFIIndex = MF.addFrameInst( |
520 | 56 | MCCFIInstruction::createOffset(nullptr, Reg, Offset)); |
521 | 56 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
522 | 56 | .addCFIIndex(CFIIndex); |
523 | 56 | } |
524 | 14 | } |
525 | 2.50k | |
526 | 2.50k | // if framepointer enabled, set it to point to the stack pointer. |
527 | 2.50k | if (hasFP(MF)) { |
528 | 329 | // Insert instruction "move $fp, $sp" at this location. |
529 | 329 | BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO) |
530 | 329 | .setMIFlag(MachineInstr::FrameSetup); |
531 | 329 | |
532 | 329 | // emit ".cfi_def_cfa_register $fp" |
533 | 329 | unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( |
534 | 329 | nullptr, MRI->getDwarfRegNum(FP, true))); |
535 | 329 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
536 | 329 | .addCFIIndex(CFIIndex); |
537 | 329 | |
538 | 329 | if (RegInfo.needsStackRealignment(MF)) { |
539 | 200 | // addiu $Reg, $zero, -MaxAlignment |
540 | 200 | // andi $sp, $sp, $Reg |
541 | 200 | unsigned VR = MF.getRegInfo().createVirtualRegister(RC); |
542 | 200 | assert(isInt<16>(MFI.getMaxAlignment()) && |
543 | 200 | "Function's alignment size requirement is not supported."); |
544 | 200 | int MaxAlign = -(int)MFI.getMaxAlignment(); |
545 | 200 | |
546 | 200 | BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign); |
547 | 200 | BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); |
548 | 200 | |
549 | 200 | if (hasBP(MF)) { |
550 | 45 | // move $s7, $sp |
551 | 45 | unsigned BP = STI.isABI_N64() ? Mips::S7_6412 : Mips::S733 ; |
552 | 45 | BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP) |
553 | 45 | .addReg(SP) |
554 | 45 | .addReg(ZERO); |
555 | 45 | } |
556 | 200 | } |
557 | 329 | } |
558 | 2.50k | } |
559 | | |
560 | | void MipsSEFrameLowering::emitInterruptPrologueStub( |
561 | 11 | MachineFunction &MF, MachineBasicBlock &MBB) const { |
562 | 11 | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
563 | 11 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
564 | 11 | DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc()0 ; |
565 | 11 | |
566 | 11 | // Report an error the target doesn't support Mips32r2 or later. |
567 | 11 | // The epilogue relies on the use of the "ehb" to clear execution |
568 | 11 | // hazards. Pre R2 Mips relies on an implementation defined number |
569 | 11 | // of "ssnop"s to clear the execution hazard. Support for ssnop hazard |
570 | 11 | // clearing is not provided so reject that configuration. |
571 | 11 | if (!STI.hasMips32r2()) |
572 | 1 | report_fatal_error( |
573 | 1 | "\"interrupt\" attribute is not supported on pre-MIPS32R2 or " |
574 | 1 | "MIPS16 targets."); |
575 | 10 | |
576 | 10 | // The GP register contains the "user" value, so we cannot perform |
577 | 10 | // any gp relative loads until we restore the "kernel" or "system" gp |
578 | 10 | // value. Until support is written we shall only accept the static |
579 | 10 | // relocation model. |
580 | 10 | if ((STI.getRelocationModel() != Reloc::Static)) |
581 | 0 | report_fatal_error("\"interrupt\" attribute is only supported for the " |
582 | 0 | "static relocation model on MIPS at the present time."); |
583 | 10 | |
584 | 10 | if (!STI.isABI_O32() || STI.hasMips64()9 ) |
585 | 1 | report_fatal_error("\"interrupt\" attribute is only supported for the " |
586 | 1 | "O32 ABI on MIPS32R2+ at the present time."); |
587 | 9 | |
588 | 9 | // Perform ISR handling like GCC |
589 | 9 | StringRef IntKind = |
590 | 9 | MF.getFunction().getFnAttribute("interrupt").getValueAsString(); |
591 | 9 | const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; |
592 | 9 | |
593 | 9 | // EIC interrupt handling needs to read the Cause register to disable |
594 | 9 | // interrupts. |
595 | 9 | if (IntKind == "eic") { |
596 | 1 | // Coprocessor registers are always live per se. |
597 | 1 | MBB.addLiveIn(Mips::COP013); |
598 | 1 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0) |
599 | 1 | .addReg(Mips::COP013) |
600 | 1 | .addImm(0) |
601 | 1 | .setMIFlag(MachineInstr::FrameSetup); |
602 | 1 | |
603 | 1 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0) |
604 | 1 | .addReg(Mips::K0) |
605 | 1 | .addImm(10) |
606 | 1 | .addImm(6) |
607 | 1 | .setMIFlag(MachineInstr::FrameSetup); |
608 | 1 | } |
609 | 9 | |
610 | 9 | // Fetch and spill EPC |
611 | 9 | MBB.addLiveIn(Mips::COP014); |
612 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) |
613 | 9 | .addReg(Mips::COP014) |
614 | 9 | .addImm(0) |
615 | 9 | .setMIFlag(MachineInstr::FrameSetup); |
616 | 9 | |
617 | 9 | STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, |
618 | 9 | MipsFI->getISRRegFI(0), PtrRC, |
619 | 9 | STI.getRegisterInfo(), 0); |
620 | 9 | |
621 | 9 | // Fetch and Spill Status |
622 | 9 | MBB.addLiveIn(Mips::COP012); |
623 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) |
624 | 9 | .addReg(Mips::COP012) |
625 | 9 | .addImm(0) |
626 | 9 | .setMIFlag(MachineInstr::FrameSetup); |
627 | 9 | |
628 | 9 | STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, |
629 | 9 | MipsFI->getISRRegFI(1), PtrRC, |
630 | 9 | STI.getRegisterInfo(), 0); |
631 | 9 | |
632 | 9 | // Build the configuration for disabling lower priority interrupts. Non EIC |
633 | 9 | // interrupts need to be masked off with zero, EIC from the Cause register. |
634 | 9 | unsigned InsPosition = 8; |
635 | 9 | unsigned InsSize = 0; |
636 | 9 | unsigned SrcReg = Mips::ZERO; |
637 | 9 | |
638 | 9 | // If the interrupt we're tied to is the EIC, switch the source for the |
639 | 9 | // masking off interrupts to the cause register. |
640 | 9 | if (IntKind == "eic") { |
641 | 1 | SrcReg = Mips::K0; |
642 | 1 | InsPosition = 10; |
643 | 1 | InsSize = 6; |
644 | 1 | } else |
645 | 8 | InsSize = StringSwitch<unsigned>(IntKind) |
646 | 8 | .Case("sw0", 1) |
647 | 8 | .Case("sw1", 2) |
648 | 8 | .Case("hw0", 3) |
649 | 8 | .Case("hw1", 4) |
650 | 8 | .Case("hw2", 5) |
651 | 8 | .Case("hw3", 6) |
652 | 8 | .Case("hw4", 7) |
653 | 8 | .Case("hw5", 8) |
654 | 8 | .Default(0); |
655 | 9 | assert(InsSize != 0 && "Unknown interrupt type!"); |
656 | 9 | |
657 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) |
658 | 9 | .addReg(SrcReg) |
659 | 9 | .addImm(InsPosition) |
660 | 9 | .addImm(InsSize) |
661 | 9 | .addReg(Mips::K1) |
662 | 9 | .setMIFlag(MachineInstr::FrameSetup); |
663 | 9 | |
664 | 9 | // Mask off KSU, ERL, EXL |
665 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) |
666 | 9 | .addReg(Mips::ZERO) |
667 | 9 | .addImm(1) |
668 | 9 | .addImm(4) |
669 | 9 | .addReg(Mips::K1) |
670 | 9 | .setMIFlag(MachineInstr::FrameSetup); |
671 | 9 | |
672 | 9 | // Disable the FPU as we are not spilling those register sets. |
673 | 9 | if (!STI.useSoftFloat()) |
674 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) |
675 | 9 | .addReg(Mips::ZERO) |
676 | 9 | .addImm(29) |
677 | 9 | .addImm(1) |
678 | 9 | .addReg(Mips::K1) |
679 | 9 | .setMIFlag(MachineInstr::FrameSetup); |
680 | 9 | |
681 | 9 | // Set the new status |
682 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) |
683 | 9 | .addReg(Mips::K1) |
684 | 9 | .addImm(0) |
685 | 9 | .setMIFlag(MachineInstr::FrameSetup); |
686 | 9 | } |
687 | | |
688 | | void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, |
689 | 12.9k | MachineBasicBlock &MBB) const { |
690 | 12.9k | MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); |
691 | 12.9k | MachineFrameInfo &MFI = MF.getFrameInfo(); |
692 | 12.9k | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
693 | 12.9k | |
694 | 12.9k | const MipsSEInstrInfo &TII = |
695 | 12.9k | *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo()); |
696 | 12.9k | const MipsRegisterInfo &RegInfo = |
697 | 12.9k | *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo()); |
698 | 12.9k | |
699 | 12.9k | DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc()12.8k : DebugLoc()68 ; |
700 | 12.9k | MipsABIInfo ABI = STI.getABI(); |
701 | 12.9k | unsigned SP = ABI.GetStackPtr(); |
702 | 12.9k | unsigned FP = ABI.GetFramePtr(); |
703 | 12.9k | unsigned ZERO = ABI.GetNullPtr(); |
704 | 12.9k | unsigned MOVE = ABI.GetGPRMoveOp(); |
705 | 12.9k | |
706 | 12.9k | // if framepointer enabled, restore the stack pointer. |
707 | 12.9k | if (hasFP(MF)) { |
708 | 328 | // Find the first instruction that restores a callee-saved register. |
709 | 328 | MachineBasicBlock::iterator I = MBBI; |
710 | 328 | |
711 | 871 | for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i543 ) |
712 | 543 | --I; |
713 | 328 | |
714 | 328 | // Insert instruction "move $sp, $fp" at this location. |
715 | 328 | BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO); |
716 | 328 | } |
717 | 12.9k | |
718 | 12.9k | if (MipsFI->callsEhReturn()) { |
719 | 14 | const TargetRegisterClass *RC = |
720 | 14 | ABI.ArePtrs64bit() ? &Mips::GPR64RegClass8 : &Mips::GPR32RegClass6 ; |
721 | 14 | |
722 | 14 | // Find first instruction that restores a callee-saved register. |
723 | 14 | MachineBasicBlock::iterator I = MBBI; |
724 | 39 | for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i25 ) |
725 | 25 | --I; |
726 | 14 | |
727 | 14 | // Insert instructions that restore eh data registers. |
728 | 70 | for (int J = 0; J < 4; ++J56 ) { |
729 | 56 | TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J), |
730 | 56 | MipsFI->getEhDataRegFI(J), RC, &RegInfo); |
731 | 56 | } |
732 | 14 | } |
733 | 12.9k | |
734 | 12.9k | if (MF.getFunction().hasFnAttribute("interrupt")) |
735 | 9 | emitInterruptEpilogueStub(MF, MBB); |
736 | 12.9k | |
737 | 12.9k | // Get the number of bytes from FrameInfo |
738 | 12.9k | uint64_t StackSize = MFI.getStackSize(); |
739 | 12.9k | |
740 | 12.9k | if (!StackSize) |
741 | 10.3k | return; |
742 | 2.55k | |
743 | 2.55k | // Adjust stack. |
744 | 2.55k | TII.adjustStackPtr(SP, StackSize, MBB, MBBI); |
745 | 2.55k | } |
746 | | |
747 | | void MipsSEFrameLowering::emitInterruptEpilogueStub( |
748 | 9 | MachineFunction &MF, MachineBasicBlock &MBB) const { |
749 | 9 | MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); |
750 | 9 | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
751 | 9 | DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc()0 ; |
752 | 9 | |
753 | 9 | // Perform ISR handling like GCC |
754 | 9 | const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; |
755 | 9 | |
756 | 9 | // Disable Interrupts. |
757 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO); |
758 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB)); |
759 | 9 | |
760 | 9 | // Restore EPC |
761 | 9 | STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1, |
762 | 9 | MipsFI->getISRRegFI(0), PtrRC, |
763 | 9 | STI.getRegisterInfo()); |
764 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014) |
765 | 9 | .addReg(Mips::K1) |
766 | 9 | .addImm(0); |
767 | 9 | |
768 | 9 | // Restore Status |
769 | 9 | STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1, |
770 | 9 | MipsFI->getISRRegFI(1), PtrRC, |
771 | 9 | STI.getRegisterInfo()); |
772 | 9 | BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) |
773 | 9 | .addReg(Mips::K1) |
774 | 9 | .addImm(0); |
775 | 9 | } |
776 | | |
777 | | int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, |
778 | | int FI, |
779 | 11 | unsigned &FrameReg) const { |
780 | 11 | const MachineFrameInfo &MFI = MF.getFrameInfo(); |
781 | 11 | MipsABIInfo ABI = STI.getABI(); |
782 | 11 | |
783 | 11 | if (MFI.isFixedObjectIndex(FI)) |
784 | 2 | FrameReg = hasFP(MF) ? ABI.GetFramePtr()1 : ABI.GetStackPtr()1 ; |
785 | 9 | else |
786 | 9 | FrameReg = hasBP(MF) ? ABI.GetBasePtr()4 : ABI.GetStackPtr()5 ; |
787 | 11 | |
788 | 11 | return MFI.getObjectOffset(FI) + MFI.getStackSize() - |
789 | 11 | getOffsetOfLocalArea() + MFI.getOffsetAdjustment(); |
790 | 11 | } |
791 | | |
792 | | bool MipsSEFrameLowering:: |
793 | | spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
794 | | MachineBasicBlock::iterator MI, |
795 | | const std::vector<CalleeSavedInfo> &CSI, |
796 | 2.09k | const TargetRegisterInfo *TRI) const { |
797 | 2.09k | MachineFunction *MF = MBB.getParent(); |
798 | 2.09k | const TargetInstrInfo &TII = *STI.getInstrInfo(); |
799 | 2.09k | |
800 | 5.87k | for (unsigned i = 0, e = CSI.size(); i != e; ++i3.78k ) { |
801 | 3.78k | // Add the callee-saved register as live-in. Do not add if the register is |
802 | 3.78k | // RA and return address is taken, because it has already been added in |
803 | 3.78k | // method MipsTargetLowering::lowerRETURNADDR. |
804 | 3.78k | // It's killed at the spill, unless the register is RA and return address |
805 | 3.78k | // is taken. |
806 | 3.78k | unsigned Reg = CSI[i].getReg(); |
807 | 3.78k | bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_642.77k ) |
808 | 3.78k | && MF->getFrameInfo().isReturnAddressTaken()1.79k ; |
809 | 3.78k | if (!IsRAAndRetAddrIsTaken) |
810 | 3.77k | MBB.addLiveIn(Reg); |
811 | 3.78k | |
812 | 3.78k | // ISRs require HI/LO to be spilled into kernel registers to be then |
813 | 3.78k | // spilled to the stack frame. |
814 | 3.78k | bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_643.77k || |
815 | 3.78k | Reg == Mips::HI03.77k || Reg == Mips::HI0_643.77k ); |
816 | 3.78k | const Function &Func = MBB.getParent()->getFunction(); |
817 | 3.78k | if (IsLOHI && Func.hasFnAttribute("interrupt")2 ) { |
818 | 2 | DebugLoc DL = MI->getDebugLoc(); |
819 | 2 | |
820 | 2 | unsigned Op = 0; |
821 | 2 | if (!STI.getABI().ArePtrs64bit()) { |
822 | 2 | Op = (Reg == Mips::HI0) ? Mips::MFHI1 : Mips::MFLO1 ; |
823 | 2 | Reg = Mips::K0; |
824 | 2 | } else { |
825 | 0 | Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; |
826 | 0 | Reg = Mips::K0_64; |
827 | 0 | } |
828 | 2 | BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0) |
829 | 2 | .setMIFlag(MachineInstr::FrameSetup); |
830 | 2 | } |
831 | 3.78k | |
832 | 3.78k | // Insert the spill to the stack frame. |
833 | 3.78k | bool IsKill = !IsRAAndRetAddrIsTaken; |
834 | 3.78k | const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); |
835 | 3.78k | TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, |
836 | 3.78k | CSI[i].getFrameIdx(), RC, TRI); |
837 | 3.78k | } |
838 | 2.09k | |
839 | 2.09k | return true; |
840 | 2.09k | } |
841 | | |
842 | | bool |
843 | 16.4k | MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { |
844 | 16.4k | const MachineFrameInfo &MFI = MF.getFrameInfo(); |
845 | 16.4k | // Reserve call frame if the size of the maximum call frame fits into 16-bit |
846 | 16.4k | // immediate field and there are no variable sized objects on the stack. |
847 | 16.4k | // Make sure the second register scavenger spill slot can be accessed with one |
848 | 16.4k | // instruction. |
849 | 16.4k | return isInt<16>(MFI.getMaxCallFrameSize() + getStackAlignment()) && |
850 | 16.4k | !MFI.hasVarSizedObjects()16.4k ; |
851 | 16.4k | } |
852 | | |
853 | | /// Mark \p Reg and all registers aliasing it in the bitset. |
854 | | static void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs, |
855 | 383 | unsigned Reg) { |
856 | 383 | const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); |
857 | 1.14k | for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI766 ) |
858 | 766 | SavedRegs.set(*AI); |
859 | 383 | } |
860 | | |
861 | | void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, |
862 | | BitVector &SavedRegs, |
863 | 13.0k | RegScavenger *RS) const { |
864 | 13.0k | TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); |
865 | 13.0k | const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); |
866 | 13.0k | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
867 | 13.0k | MipsABIInfo ABI = STI.getABI(); |
868 | 13.0k | unsigned FP = ABI.GetFramePtr(); |
869 | 13.0k | unsigned BP = ABI.IsN64() ? Mips::S7_644.23k : Mips::S78.79k ; |
870 | 13.0k | |
871 | 13.0k | // Mark $fp as used if function has dedicated frame pointer. |
872 | 13.0k | if (hasFP(MF)) |
873 | 337 | setAliasRegs(MF, SavedRegs, FP); |
874 | 13.0k | // Mark $s7 as used if function has dedicated base pointer. |
875 | 13.0k | if (hasBP(MF)) |
876 | 46 | setAliasRegs(MF, SavedRegs, BP); |
877 | 13.0k | |
878 | 13.0k | // Create spill slots for eh data registers if function calls eh_return. |
879 | 13.0k | if (MipsFI->callsEhReturn()) |
880 | 14 | MipsFI->createEhDataRegsFI(); |
881 | 13.0k | |
882 | 13.0k | // Create spill slots for Coprocessor 0 registers if function is an ISR. |
883 | 13.0k | if (MipsFI->isISR()) |
884 | 11 | MipsFI->createISRRegFI(); |
885 | 13.0k | |
886 | 13.0k | // Expand pseudo instructions which load, store or copy accumulators. |
887 | 13.0k | // Add an emergency spill slot if a pseudo was expanded. |
888 | 13.0k | if (ExpandPseudo(MF).expand()) { |
889 | 3 | // The spill slot should be half the size of the accumulator. If target have |
890 | 3 | // general-purpose registers 64 bits wide, it should be 64-bit, otherwise |
891 | 3 | // it should be 32-bit. |
892 | 3 | const TargetRegisterClass &RC = STI.isGP64bit() ? |
893 | 2 | Mips::GPR64RegClass1 : Mips::GPR32RegClass; |
894 | 3 | int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), |
895 | 3 | TRI->getSpillAlignment(RC), |
896 | 3 | false); |
897 | 3 | RS->addScavengingFrameIndex(FI); |
898 | 3 | } |
899 | 13.0k | |
900 | 13.0k | // Set scavenging frame index if necessary. |
901 | 13.0k | uint64_t MaxSPOffset = estimateStackSize(MF); |
902 | 13.0k | |
903 | 13.0k | // MSA has a minimum offset of 10 bits signed. If there is a variable |
904 | 13.0k | // sized object on the stack, the estimation cannot account for it. |
905 | 13.0k | if (isIntN(STI.hasMSA() ? 103.47k : 169.56k , MaxSPOffset) && |
906 | 13.0k | !MF.getFrameInfo().hasVarSizedObjects()12.9k ) |
907 | 12.9k | return; |
908 | 110 | |
909 | 110 | const TargetRegisterClass &RC = |
910 | 110 | ABI.ArePtrs64bit() ? Mips::GPR64RegClass24 : Mips::GPR32RegClass86 ; |
911 | 110 | int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), |
912 | 110 | TRI->getSpillAlignment(RC), |
913 | 110 | false); |
914 | 110 | RS->addScavengingFrameIndex(FI); |
915 | 110 | } |
916 | | |
917 | | const MipsFrameLowering * |
918 | 8.43k | llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) { |
919 | 8.43k | return new MipsSEFrameLowering(ST); |
920 | 8.43k | } |