Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// Subclass of MipsDAGToDAGISel specialized for mips32/64.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MipsSEISelDAGToDAG.h"
14
#include "MCTargetDesc/MipsBaseInfo.h"
15
#include "Mips.h"
16
#include "MipsAnalyzeImmediate.h"
17
#include "MipsMachineFunction.h"
18
#include "MipsRegisterInfo.h"
19
#include "llvm/CodeGen/MachineConstantPool.h"
20
#include "llvm/CodeGen/MachineFrameInfo.h"
21
#include "llvm/CodeGen/MachineFunction.h"
22
#include "llvm/CodeGen/MachineInstrBuilder.h"
23
#include "llvm/CodeGen/MachineRegisterInfo.h"
24
#include "llvm/CodeGen/SelectionDAGNodes.h"
25
#include "llvm/IR/CFG.h"
26
#include "llvm/IR/Dominators.h"
27
#include "llvm/IR/GlobalValue.h"
28
#include "llvm/IR/Instructions.h"
29
#include "llvm/IR/Intrinsics.h"
30
#include "llvm/IR/Type.h"
31
#include "llvm/Support/Debug.h"
32
#include "llvm/Support/ErrorHandling.h"
33
#include "llvm/Support/raw_ostream.h"
34
#include "llvm/Target/TargetMachine.h"
35
using namespace llvm;
36
37
#define DEBUG_TYPE "mips-isel"
38
39
12.8k
bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40
12.8k
  Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41
12.8k
  if (Subtarget->inMips16Mode())
42
380
    return false;
43
12.5k
  return MipsDAGToDAGISel::runOnMachineFunction(MF);
44
12.5k
}
45
46
1.97k
void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
47
1.97k
  AU.addRequired<DominatorTreeWrapperPass>();
48
1.97k
  SelectionDAGISel::getAnalysisUsage(AU);
49
1.97k
}
50
51
void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
52
18
                                               MachineFunction &MF) {
53
18
  MachineInstrBuilder MIB(MF, &MI);
54
18
  unsigned Mask = MI.getOperand(1).getImm();
55
18
  unsigned Flag =
56
18
      IsDef ? 
RegState::ImplicitDefine7
:
RegState::Implicit | RegState::Undef11
;
57
18
58
18
  if (Mask & 1)
59
16
    MIB.addReg(Mips::DSPPos, Flag);
60
18
61
18
  if (Mask & 2)
62
8
    MIB.addReg(Mips::DSPSCount, Flag);
63
18
64
18
  if (Mask & 4)
65
8
    MIB.addReg(Mips::DSPCarry, Flag);
66
18
67
18
  if (Mask & 8)
68
8
    MIB.addReg(Mips::DSPOutFlag, Flag);
69
18
70
18
  if (Mask & 16)
71
10
    MIB.addReg(Mips::DSPCCond, Flag);
72
18
73
18
  if (Mask & 32)
74
0
    MIB.addReg(Mips::DSPEFI, Flag);
75
18
}
76
77
36
unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
78
36
  uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
79
36
  return Mips::MSACtrlRegClass.getRegister(RegNum);
80
36
}
81
82
bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
83
128k
                                                const MachineInstr& MI) {
84
128k
  unsigned DstReg = 0, ZeroReg = 0;
85
128k
86
128k
  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
87
128k
  if ((MI.getOpcode() == Mips::ADDiu) &&
88
128k
      
(MI.getOperand(1).getReg() == Mips::ZERO)6.13k
&&
89
128k
      
(MI.getOperand(2).isImm())2.82k
&&
90
128k
      
(MI.getOperand(2).getImm() == 0)2.82k
) {
91
1.12k
    DstReg = MI.getOperand(0).getReg();
92
1.12k
    ZeroReg = Mips::ZERO;
93
127k
  } else if ((MI.getOpcode() == Mips::DADDiu) &&
94
127k
             
(MI.getOperand(1).getReg() == Mips::ZERO_64)2.77k
&&
95
127k
             
(MI.getOperand(2).isImm())426
&&
96
127k
             
(MI.getOperand(2).getImm() == 0)422
) {
97
142
    DstReg = MI.getOperand(0).getReg();
98
142
    ZeroReg = Mips::ZERO_64;
99
142
  }
100
128k
101
128k
  if (!DstReg)
102
127k
    return false;
103
1.27k
104
1.27k
  // Replace uses with ZeroReg.
105
1.27k
  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106
3.71k
       E = MRI->use_end(); U != E;) {
107
2.44k
    MachineOperand &MO = *U;
108
2.44k
    unsigned OpNo = U.getOperandNo();
109
2.44k
    MachineInstr *MI = MO.getParent();
110
2.44k
    ++U;
111
2.44k
112
2.44k
    // Do not replace if it is a phi's operand or is tied to def operand.
113
2.44k
    if (MI->isPHI() || 
MI->isRegTiedToDefOperand(OpNo)2.42k
||
MI->isPseudo()2.39k
)
114
1.83k
      continue;
115
610
116
610
    // Also, we have to check that the register class of the operand
117
610
    // contains the zero register.
118
610
    if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
119
0
      continue;
120
610
121
610
    MO.setReg(ZeroReg);
122
610
  }
123
1.27k
124
1.27k
  return true;
125
1.27k
}
126
127
12.5k
void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
128
12.5k
  MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg();
129
12.5k
130
12.5k
  MachineRegisterInfo *MRI = &MF.getRegInfo();
131
12.5k
132
13.9k
  for (auto &MBB: MF) {
133
128k
    for (auto &MI: MBB) {
134
128k
      switch (MI.getOpcode()) {
135
128k
      case Mips::RDDSP:
136
11
        addDSPCtrlRegOperands(false, MI, MF);
137
11
        break;
138
128k
      case Mips::WRDSP:
139
7
        addDSPCtrlRegOperands(true, MI, MF);
140
7
        break;
141
128k
      case Mips::BuildPairF64_64:
142
120
      case Mips::ExtractElementF64_64:
143
120
        if (!Subtarget->useOddSPReg()) {
144
22
          MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
145
22
          break;
146
22
        }
147
98
        LLVM_FALLTHROUGH;
148
381
      case Mips::BuildPairF64:
149
381
      case Mips::ExtractElementF64:
150
381
        if (Subtarget->isABI_FPXX() && 
!Subtarget->hasMTHC1()22
)
151
11
          MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
152
381
        break;
153
128k
      default:
154
128k
        replaceUsesWithZeroReg(MRI, MI);
155
128k
      }
156
128k
    }
157
13.9k
  }
158
12.5k
}
159
160
10
void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
161
10
  SDValue InFlag = Node->getOperand(2);
162
10
  unsigned Opc = InFlag.getOpcode();
163
10
  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
164
10
  EVT VT = LHS.getValueType();
165
10
166
10
  // In the base case, we can rely on the carry bit from the addsc
167
10
  // instruction.
168
10
  if (Opc == ISD::ADDC) {
169
6
    SDValue Ops[3] = {LHS, RHS, InFlag};
170
6
    CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
171
6
    return;
172
6
  }
173
4
174
4
  assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
175
4
176
4
  // The more complex case is when there is a chain of ISD::ADDE nodes like:
177
4
  // (adde (adde (adde (addc a b) c) d) e).
178
4
  //
179
4
  // The addwc instruction does not write to the carry bit, instead it writes
180
4
  // to bit 20 of the dsp control register. To match this series of nodes, each
181
4
  // intermediate adde node must be expanded to write the carry bit before the
182
4
  // addition.
183
4
184
4
  // Start by reading the overflow field for addsc and moving the value to the
185
4
  // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
186
4
  // corresponds to reading/writing the entire control register to/from a GPR.
187
4
188
4
  SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
189
4
190
4
  SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
191
4
192
4
  SDNode *DSPCtrlField =
193
4
      CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
194
4
195
4
  SDNode *Carry = CurDAG->getMachineNode(
196
4
      Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
197
4
198
4
  SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
199
4
                    CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
200
4
                    SDValue(Carry, 0)};
201
4
  SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
202
4
203
4
  // My reading of the MIPS DSP 3.01 specification isn't as clear as I
204
4
  // would like about whether bit 20 always gets overwritten by addwc.
205
4
  // Hence take an extremely conservative view and presume it's sticky. We
206
4
  // therefore need to clear it.
207
4
208
4
  SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
209
4
210
4
  SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
211
4
  SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
212
4
213
4
  SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
214
4
                                         SDValue(DSPCtrlFinal, 0), CstOne);
215
4
216
4
  SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
217
4
  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
218
4
}
219
220
/// Match frameindex
221
bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
222
25.5k
                                              SDValue &Offset) const {
223
25.5k
  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
224
4.23k
    EVT ValTy = Addr.getValueType();
225
4.23k
226
4.23k
    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
227
4.23k
    Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
228
4.23k
    return true;
229
4.23k
  }
230
21.3k
  return false;
231
21.3k
}
232
233
/// Match frameindex+offset and frameindex|offset
234
bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
235
    SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
236
16.3k
    unsigned ShiftAmount = 0) const {
237
16.3k
  if (CurDAG->isBaseWithConstantOffset(Addr)) {
238
4.13k
    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
239
4.13k
    if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
240
4.08k
      EVT ValTy = Addr.getValueType();
241
4.08k
242
4.08k
      // If the first operand is a FI, get the TargetFI Node
243
4.08k
      if (FrameIndexSDNode *FIN =
244
1.11k
              dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
245
1.11k
        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
246
2.96k
      else {
247
2.96k
        Base = Addr.getOperand(0);
248
2.96k
        // If base is a FI, additional offset calculation is done in
249
2.96k
        // eliminateFrameIndex, otherwise we need to check the alignment
250
2.96k
        if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0)
251
12
          return false;
252
4.07k
      }
253
4.07k
254
4.07k
      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
255
4.07k
                                         ValTy);
256
4.07k
      return true;
257
4.07k
    }
258
4.13k
  }
259
12.2k
  return false;
260
12.2k
}
261
262
/// ComplexPattern used on MipsInstrInfo
263
/// Used on Mips Load/Store instructions
264
bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
265
17.0k
                                          SDValue &Offset) const {
266
17.0k
  // if Address is FI, get the TargetFrameIndex.
267
17.0k
  if (selectAddrFrameIndex(Addr, Base, Offset))
268
4.03k
    return true;
269
12.9k
270
12.9k
  // on PIC code Load GA
271
12.9k
  if (Addr.getOpcode() == MipsISD::Wrapper) {
272
5.82k
    Base   = Addr.getOperand(0);
273
5.82k
    Offset = Addr.getOperand(1);
274
5.82k
    return true;
275
5.82k
  }
276
7.16k
277
7.16k
  if (!TM.isPositionIndependent()) {
278
3.89k
    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
279
3.89k
        Addr.getOpcode() == ISD::TargetGlobalAddress))
280
0
      return false;
281
7.16k
  }
282
7.16k
283
7.16k
  // Addresses of the form FI+const or FI|const
284
7.16k
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
285
3.52k
    return true;
286
3.64k
287
3.64k
  // Operand is a result from an ADD.
288
3.64k
  if (Addr.getOpcode() == ISD::ADD) {
289
1.32k
    // When loading from constant pools, load the lower address part in
290
1.32k
    // the instruction itself. Example, instead of:
291
1.32k
    //  lui $2, %hi($CPI1_0)
292
1.32k
    //  addiu $2, $2, %lo($CPI1_0)
293
1.32k
    //  lwc1 $f0, 0($2)
294
1.32k
    // Generate:
295
1.32k
    //  lui $2, %hi($CPI1_0)
296
1.32k
    //  lwc1 $f0, %lo($CPI1_0)($2)
297
1.32k
    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
298
1.32k
        
Addr.getOperand(1).getOpcode() == MipsISD::GPRel148
) {
299
1.18k
      SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
300
1.18k
      if (isa<ConstantPoolSDNode>(Opnd0) || 
isa<GlobalAddressSDNode>(Opnd0)857
||
301
1.18k
          
isa<JumpTableSDNode>(Opnd0)22
) {
302
1.18k
        Base = Addr.getOperand(0);
303
1.18k
        Offset = Opnd0;
304
1.18k
        return true;
305
1.18k
      }
306
2.45k
    }
307
1.32k
  }
308
2.45k
309
2.45k
  return false;
310
2.45k
}
311
312
/// ComplexPattern used on MipsInstrInfo
313
/// Used on Mips Load/Store instructions
314
bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
315
10.3k
                                           SDValue &Offset) const {
316
10.3k
  Base = Addr;
317
10.3k
  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
318
10.3k
  return true;
319
10.3k
}
320
321
bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
322
8.60k
                                       SDValue &Offset) const {
323
8.60k
  return selectAddrRegImm(Addr, Base, Offset) ||
324
8.60k
    
selectAddrDefault(Addr, Base, Offset)1.30k
;
325
8.60k
}
326
327
bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
328
17
                                           SDValue &Offset) const {
329
17
  if (selectAddrFrameIndex(Addr, Base, Offset))
330
0
    return true;
331
17
332
17
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
333
9
    return true;
334
8
335
8
  return false;
336
8
}
337
338
/// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
339
bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
340
0
                                            SDValue &Offset) const {
341
0
  if (selectAddrFrameIndex(Addr, Base, Offset))
342
0
    return true;
343
0
344
0
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
345
0
    return true;
346
0
347
0
  return false;
348
0
}
349
350
/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
351
bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
352
13
                                            SDValue &Offset) const {
353
13
  if (selectAddrFrameIndex(Addr, Base, Offset))
354
0
    return true;
355
13
356
13
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
357
7
    return true;
358
6
359
6
  return false;
360
6
}
361
362
bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
363
39
                                            SDValue &Offset) const {
364
39
  if (selectAddrFrameIndex(Addr, Base, Offset))
365
4
    return true;
366
35
367
35
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
368
23
    return true;
369
12
370
12
  return false;
371
12
}
372
373
bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
374
0
                                         SDValue &Offset) const {
375
0
  return selectAddrRegImm11(Addr, Base, Offset) ||
376
0
    selectAddrDefault(Addr, Base, Offset);
377
0
}
378
379
bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
380
4
                                         SDValue &Offset) const {
381
4
  return selectAddrRegImm12(Addr, Base, Offset) ||
382
4
    
selectAddrDefault(Addr, Base, Offset)2
;
383
4
}
384
385
bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
386
6
                                         SDValue &Offset) const {
387
6
  return selectAddrRegImm16(Addr, Base, Offset) ||
388
6
    selectAddrDefault(Addr, Base, Offset);
389
6
}
390
391
bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
392
848
                                             SDValue &Offset) const {
393
848
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
394
184
    if (isa<FrameIndexSDNode>(Base))
395
5
      return false;
396
179
397
179
    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
398
179
      unsigned CnstOff = CN->getZExtValue();
399
179
      return (CnstOff == (CnstOff & 0x3c));
400
179
    }
401
0
402
0
    return false;
403
0
  }
404
664
405
664
  // For all other cases where "lw" would be selected, don't select "lw16"
406
664
  // because it would result in additional instructions to prepare operands.
407
664
  if (selectAddrRegImm(Addr, Base, Offset))
408
508
    return false;
409
156
410
156
  return selectAddrDefault(Addr, Base, Offset);
411
156
}
412
413
bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
414
2.18k
                                             SDValue &Offset) const {
415
2.18k
416
2.18k
  if (selectAddrFrameIndex(Addr, Base, Offset))
417
26
    return true;
418
2.16k
419
2.16k
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
420
78
    return true;
421
2.08k
422
2.08k
  return selectAddrDefault(Addr, Base, Offset);
423
2.08k
}
424
425
bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
426
1.60k
                                                 SDValue &Offset) const {
427
1.60k
  if (selectAddrFrameIndex(Addr, Base, Offset))
428
42
    return true;
429
1.56k
430
1.56k
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
431
82
    return true;
432
1.48k
433
1.48k
  return selectAddrDefault(Addr, Base, Offset);
434
1.48k
}
435
436
bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
437
2.46k
                                                 SDValue &Offset) const {
438
2.46k
  if (selectAddrFrameIndex(Addr, Base, Offset))
439
54
    return true;
440
2.40k
441
2.40k
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
442
82
    return true;
443
2.32k
444
2.32k
  return selectAddrDefault(Addr, Base, Offset);
445
2.32k
}
446
447
bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
448
2.22k
                                                 SDValue &Offset) const {
449
2.22k
  if (selectAddrFrameIndex(Addr, Base, Offset))
450
74
    return true;
451
2.15k
452
2.15k
  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
453
82
    return true;
454
2.07k
455
2.07k
  return selectAddrDefault(Addr, Base, Offset);
456
2.07k
}
457
458
// Select constant vector splats.
459
//
460
// Returns true and sets Imm if:
461
// * MSA is enabled
462
// * N is a ISD::BUILD_VECTOR representing a constant splat
463
bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
464
3.60k
                                      unsigned MinSizeInBits) const {
465
3.60k
  if (!Subtarget->hasMSA())
466
0
    return false;
467
3.60k
468
3.60k
  BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
469
3.60k
470
3.60k
  if (!Node)
471
2.55k
    return false;
472
1.05k
473
1.05k
  APInt SplatValue, SplatUndef;
474
1.05k
  unsigned SplatBitSize;
475
1.05k
  bool HasAnyUndefs;
476
1.05k
477
1.05k
  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
478
1.05k
                             MinSizeInBits, !Subtarget->isLittle()))
479
8
    return false;
480
1.04k
481
1.04k
  Imm = SplatValue;
482
1.04k
483
1.04k
  return true;
484
1.04k
}
485
486
// Select constant vector splats.
487
//
488
// In addition to the requirements of selectVSplat(), this function returns
489
// true and sets Imm if:
490
// * The splat value is the same width as the elements of the vector
491
// * The splat value fits in an integer with the specified signed-ness and
492
//   width.
493
//
494
// This function looks through ISD::BITCAST nodes.
495
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
496
//       sometimes a shuffle in big-endian mode.
497
//
498
// It's worth noting that this function is not used as part of the selection
499
// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
500
// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
501
// MipsSEDAGToDAGISel::selectNode.
502
bool MipsSEDAGToDAGISel::
503
selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
504
2.87k
                   unsigned ImmBitSize) const {
505
2.87k
  APInt ImmValue;
506
2.87k
  EVT EltTy = N->getValueType(0).getVectorElementType();
507
2.87k
508
2.87k
  if (N->getOpcode() == ISD::BITCAST)
509
210
    N = N->getOperand(0);
510
2.87k
511
2.87k
  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
512
2.87k
      
ImmValue.getBitWidth() == EltTy.getSizeInBits()610
) {
513
610
514
610
    if (( Signed && 
ImmValue.isSignedIntN(ImmBitSize)184
) ||
515
610
        
(426
!Signed426
&&
ImmValue.isIntN(ImmBitSize)426
)) {
516
608
      Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
517
608
      return true;
518
608
    }
519
2.26k
  }
520
2.26k
521
2.26k
  return false;
522
2.26k
}
523
524
// Select constant vector splats.
525
bool MipsSEDAGToDAGISel::
526
38
selectVSplatUimm1(SDValue N, SDValue &Imm) const {
527
38
  return selectVSplatCommon(N, Imm, false, 1);
528
38
}
529
530
bool MipsSEDAGToDAGISel::
531
13
selectVSplatUimm2(SDValue N, SDValue &Imm) const {
532
13
  return selectVSplatCommon(N, Imm, false, 2);
533
13
}
534
535
bool MipsSEDAGToDAGISel::
536
50
selectVSplatUimm3(SDValue N, SDValue &Imm) const {
537
50
  return selectVSplatCommon(N, Imm, false, 3);
538
50
}
539
540
// Select constant vector splats.
541
bool MipsSEDAGToDAGISel::
542
50
selectVSplatUimm4(SDValue N, SDValue &Imm) const {
543
50
  return selectVSplatCommon(N, Imm, false, 4);
544
50
}
545
546
// Select constant vector splats.
547
bool MipsSEDAGToDAGISel::
548
2.09k
selectVSplatUimm5(SDValue N, SDValue &Imm) const {
549
2.09k
  return selectVSplatCommon(N, Imm, false, 5);
550
2.09k
}
551
552
// Select constant vector splats.
553
bool MipsSEDAGToDAGISel::
554
57
selectVSplatUimm6(SDValue N, SDValue &Imm) const {
555
57
  return selectVSplatCommon(N, Imm, false, 6);
556
57
}
557
558
// Select constant vector splats.
559
bool MipsSEDAGToDAGISel::
560
220
selectVSplatUimm8(SDValue N, SDValue &Imm) const {
561
220
  return selectVSplatCommon(N, Imm, false, 8);
562
220
}
563
564
// Select constant vector splats.
565
bool MipsSEDAGToDAGISel::
566
354
selectVSplatSimm5(SDValue N, SDValue &Imm) const {
567
354
  return selectVSplatCommon(N, Imm, true, 5);
568
354
}
569
570
// Select constant vector splats whose value is a power of 2.
571
//
572
// In addition to the requirements of selectVSplat(), this function returns
573
// true and sets Imm if:
574
// * The splat value is the same width as the elements of the vector
575
// * The splat value is a power of two.
576
//
577
// This function looks through ISD::BITCAST nodes.
578
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
579
//       sometimes a shuffle in big-endian mode.
580
201
bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
581
201
  APInt ImmValue;
582
201
  EVT EltTy = N->getValueType(0).getVectorElementType();
583
201
584
201
  if (N->getOpcode() == ISD::BITCAST)
585
20
    N = N->getOperand(0);
586
201
587
201
  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
588
201
      
ImmValue.getBitWidth() == EltTy.getSizeInBits()87
) {
589
87
    int32_t Log2 = ImmValue.exactLogBase2();
590
87
591
87
    if (Log2 != -1) {
592
56
      Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
593
56
      return true;
594
56
    }
595
145
  }
596
145
597
145
  return false;
598
145
}
599
600
// Select constant vector splats whose value only has a consecutive sequence
601
// of left-most bits set (e.g. 0b11...1100...00).
602
//
603
// In addition to the requirements of selectVSplat(), this function returns
604
// true and sets Imm if:
605
// * The splat value is the same width as the elements of the vector
606
// * The splat value is a consecutive sequence of left-most bits.
607
//
608
// This function looks through ISD::BITCAST nodes.
609
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
610
//       sometimes a shuffle in big-endian mode.
611
143
bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
612
143
  APInt ImmValue;
613
143
  EVT EltTy = N->getValueType(0).getVectorElementType();
614
143
615
143
  if (N->getOpcode() == ISD::BITCAST)
616
12
    N = N->getOperand(0);
617
143
618
143
  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
619
143
      
ImmValue.getBitWidth() == EltTy.getSizeInBits()78
) {
620
78
    // Extract the run of set bits starting with bit zero from the bitwise
621
78
    // inverse of ImmValue, and test that the inverse of this is the same
622
78
    // as the original value.
623
78
    if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
624
30
625
30
      Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
626
30
                                      EltTy);
627
30
      return true;
628
30
    }
629
113
  }
630
113
631
113
  return false;
632
113
}
633
634
// Select constant vector splats whose value only has a consecutive sequence
635
// of right-most bits set (e.g. 0b00...0011...11).
636
//
637
// In addition to the requirements of selectVSplat(), this function returns
638
// true and sets Imm if:
639
// * The splat value is the same width as the elements of the vector
640
// * The splat value is a consecutive sequence of right-most bits.
641
//
642
// This function looks through ISD::BITCAST nodes.
643
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
644
//       sometimes a shuffle in big-endian mode.
645
113
bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
646
113
  APInt ImmValue;
647
113
  EVT EltTy = N->getValueType(0).getVectorElementType();
648
113
649
113
  if (N->getOpcode() == ISD::BITCAST)
650
7
    N = N->getOperand(0);
651
113
652
113
  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
653
113
      
ImmValue.getBitWidth() == EltTy.getSizeInBits()48
) {
654
48
    // Extract the run of set bits starting with bit zero, and test that the
655
48
    // result is the same as the original value
656
48
    if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
657
30
      Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
658
30
                                      EltTy);
659
30
      return true;
660
30
    }
661
83
  }
662
83
663
83
  return false;
664
83
}
665
666
bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
667
85
                                                 SDValue &Imm) const {
668
85
  APInt ImmValue;
669
85
  EVT EltTy = N->getValueType(0).getVectorElementType();
670
85
671
85
  if (N->getOpcode() == ISD::BITCAST)
672
7
    N = N->getOperand(0);
673
85
674
85
  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
675
85
      
ImmValue.getBitWidth() == EltTy.getSizeInBits()29
) {
676
29
    int32_t Log2 = (~ImmValue).exactLogBase2();
677
29
678
29
    if (Log2 != -1) {
679
21
      Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
680
21
      return true;
681
21
    }
682
64
  }
683
64
684
64
  return false;
685
64
}
686
687
199k
bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
688
199k
  unsigned Opcode = Node->getOpcode();
689
199k
  SDLoc DL(Node);
690
199k
691
199k
  ///
692
199k
  // Instruction Selection not handled by the auto-generated
693
199k
  // tablegen selection should be handled here.
694
199k
  ///
695
199k
  switch(Opcode) {
696
199k
  
default: break194k
;
697
199k
698
199k
  case Mips::PseudoD_SELECT_I:
699
11
  case Mips::PseudoD_SELECT_I64: {
700
11
    MVT VT = Subtarget->isGP64bit() ? 
MVT::i642
:
MVT::i329
;
701
11
    SDValue cond = Node->getOperand(0);
702
11
    SDValue Hi1 = Node->getOperand(1);
703
11
    SDValue Lo1 = Node->getOperand(2);
704
11
    SDValue Hi2 = Node->getOperand(3);
705
11
    SDValue Lo2 = Node->getOperand(4);
706
11
707
11
    SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
708
11
    EVT NodeTys[] = {VT, VT};
709
11
    ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->isGP64bit()
710
11
                                                 ? 
Mips::PseudoD_SELECT_I642
711
11
                                                 : 
Mips::PseudoD_SELECT_I9
,
712
11
                                             DL, NodeTys, ops));
713
11
    return true;
714
11
  }
715
11
716
11
  case ISD::ADDE: {
717
10
    selectAddE(Node, DL);
718
10
    return true;
719
11
  }
720
11
721
230
  case ISD::ConstantFP: {
722
230
    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
723
230
    if (Node->getValueType(0) == MVT::f64 && 
CN->isExactlyValue(+0.0)128
) {
724
128
      if (Subtarget->isGP64bit()) {
725
60
        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
726
60
                                              Mips::ZERO_64, MVT::i64);
727
60
        ReplaceNode(Node,
728
60
                    CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
729
68
      } else if (Subtarget->isFP64bit()) {
730
19
        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
731
19
                                              Mips::ZERO, MVT::i32);
732
19
        ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
733
19
                                                 MVT::f64, Zero, Zero));
734
49
      } else {
735
49
        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
736
49
                                              Mips::ZERO, MVT::i32);
737
49
        ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
738
49
                                                 MVT::f64, Zero, Zero));
739
49
      }
740
128
      return true;
741
128
    }
742
102
    break;
743
102
  }
744
102
745
3.97k
  case ISD::Constant: {
746
3.97k
    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
747
3.97k
    int64_t Imm = CN->getSExtValue();
748
3.97k
    unsigned Size = CN->getValueSizeInBits(0);
749
3.97k
750
3.97k
    if (isInt<32>(Imm))
751
3.82k
      break;
752
152
753
152
    MipsAnalyzeImmediate AnalyzeImm;
754
152
755
152
    const MipsAnalyzeImmediate::InstSeq &Seq =
756
152
      AnalyzeImm.Analyze(Imm, Size, false);
757
152
758
152
    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
759
152
    SDLoc DL(CN);
760
152
    SDNode *RegOpnd;
761
152
    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
762
152
                                                DL, MVT::i64);
763
152
764
152
    // The first instruction can be a LUi which is different from other
765
152
    // instructions (ADDiu, ORI and SLL) in that it does not have a register
766
152
    // operand.
767
152
    if (Inst->Opc == Mips::LUi64)
768
62
      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
769
90
    else
770
90
      RegOpnd =
771
90
        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
772
90
                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
773
90
                               ImmOpnd);
774
152
775
152
    // The remaining instructions in the sequence are handled here.
776
621
    for (++Inst; Inst != Seq.end(); 
++Inst469
) {
777
469
      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
778
469
                                          MVT::i64);
779
469
      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
780
469
                                       SDValue(RegOpnd, 0), ImmOpnd);
781
469
    }
782
152
783
152
    ReplaceNode(Node, RegOpnd);
784
152
    return true;
785
152
  }
786
152
787
152
  case ISD::INTRINSIC_W_CHAIN: {
788
69
    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
789
69
    default:
790
51
      break;
791
69
792
69
    case Intrinsic::mips_cfcmsa: {
793
18
      SDValue ChainIn = Node->getOperand(0);
794
18
      SDValue RegIdx = Node->getOperand(2);
795
18
      SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
796
18
                                           getMSACtrlReg(RegIdx), MVT::i32);
797
18
      ReplaceNode(Node, Reg.getNode());
798
18
      return true;
799
51
    }
800
51
    }
801
51
    break;
802
51
  }
803
51
804
496
  case ISD::INTRINSIC_WO_CHAIN: {
805
496
    switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
806
496
    default:
807
494
      break;
808
496
809
496
    case Intrinsic::mips_move_v:
810
2
      // Like an assignment but will always produce a move.v even if
811
2
      // unnecessary.
812
2
      ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
813
2
                                               Node->getValueType(0),
814
2
                                               Node->getOperand(1)));
815
2
      return true;
816
494
    }
817
494
    break;
818
494
  }
819
494
820
494
  case ISD::INTRINSIC_VOID: {
821
27
    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
822
27
    default:
823
9
      break;
824
27
825
27
    case Intrinsic::mips_ctcmsa: {
826
18
      SDValue ChainIn = Node->getOperand(0);
827
18
      SDValue RegIdx  = Node->getOperand(2);
828
18
      SDValue Value   = Node->getOperand(3);
829
18
      SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
830
18
                                              getMSACtrlReg(RegIdx), Value);
831
18
      ReplaceNode(Node, ChainOut.getNode());
832
18
      return true;
833
9
    }
834
9
    }
835
9
    break;
836
9
  }
837
9
838
9
  // Manually match MipsISD::Ins nodes to get the correct instruction. It has
839
9
  // to be done in this fashion so that we respect the differences between
840
9
  // dins and dinsm, as the difference is that the size operand has the range
841
9
  // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
842
9
  // means SelectionDAGISel would have to test all the operands at once to
843
9
  // match the instruction.
844
42
  case MipsISD::Ins: {
845
42
846
42
    // Sanity checking for the node operands.
847
42
    if (Node->getValueType(0) != MVT::i32 && 
Node->getValueType(0) != MVT::i6417
)
848
0
      return false;
849
42
850
42
    if (Node->getNumOperands() != 4)
851
0
      return false;
852
42
853
42
    if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
854
42
        Node->getOperand(2)->getOpcode() != ISD::Constant)
855
0
      return false;
856
42
857
42
    MVT ResTy = Node->getSimpleValueType(0);
858
42
    uint64_t Pos = Node->getConstantOperandVal(1);
859
42
    uint64_t Size = Node->getConstantOperandVal(2);
860
42
861
42
    // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
862
42
    if (!Size)
863
0
      return false;
864
42
865
42
    if (Pos + Size > 64)
866
0
      return false;
867
42
868
42
    if (ResTy != MVT::i32 && 
ResTy != MVT::i6417
)
869
0
      return false;
870
42
871
42
    unsigned Opcode = 0;
872
42
    if (ResTy == MVT::i32) {
873
25
      if (Pos + Size <= 32)
874
25
        Opcode = Mips::INS;
875
25
    } else {
876
17
      if (Pos + Size <= 32)
877
1
        Opcode = Mips::DINS;
878
16
      else if (Pos < 32 && 
1 < Size5
)
879
5
        Opcode = Mips::DINSM;
880
11
      else
881
11
        Opcode = Mips::DINSU;
882
17
    }
883
42
884
42
    if (Opcode) {
885
42
      SDValue Ops[4] = {
886
42
          Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
887
42
          CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
888
42
889
42
      ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
890
42
      return true;
891
42
    }
892
0
893
0
    return false;
894
0
  }
895
0
896
30
  case MipsISD::ThreadPointer: {
897
30
    EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
898
30
    unsigned RdhwrOpc, DestReg;
899
30
900
30
    if (PtrVT == MVT::i32) {
901
22
      RdhwrOpc = Mips::RDHWR;
902
22
      DestReg = Mips::V1;
903
22
    } else {
904
8
      RdhwrOpc = Mips::RDHWR64;
905
8
      DestReg = Mips::V1_64;
906
8
    }
907
30
908
30
    SDNode *Rdhwr =
909
30
        CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
910
30
                               CurDAG->getRegister(Mips::HWR29, MVT::i32),
911
30
                               CurDAG->getTargetConstant(0, DL, MVT::i32));
912
30
    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
913
30
                                         SDValue(Rdhwr, 0));
914
30
    SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
915
30
    ReplaceNode(Node, ResNode.getNode());
916
30
    return true;
917
0
  }
918
0
919
481
  case ISD::BUILD_VECTOR: {
920
481
    // Select appropriate ldi.[bhwd] instructions for constant splats of
921
481
    // 128-bit when MSA is enabled. Fixup any register class mismatches that
922
481
    // occur as a result.
923
481
    //
924
481
    // This allows the compiler to use a wider range of immediates than would
925
481
    // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
926
481
    // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
927
481
    // 0x01010101 } without using a constant pool. This would be sub-optimal
928
481
    // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
929
481
    // same set/ of registers. Similarly, ldi.h isn't capable of producing {
930
481
    // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
931
481
932
481
    const MipsABIInfo &ABI =
933
481
        static_cast<const MipsTargetMachine &>(TM).getABI();
934
481
935
481
    BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
936
481
    APInt SplatValue, SplatUndef;
937
481
    unsigned SplatBitSize;
938
481
    bool HasAnyUndefs;
939
481
    unsigned LdiOp;
940
481
    EVT ResVecTy = BVN->getValueType(0);
941
481
    EVT ViaVecTy;
942
481
943
481
    if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
944
0
      return false;
945
481
946
481
    if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
947
481
                              HasAnyUndefs, 8,
948
481
                              !Subtarget->isLittle()))
949
34
      return false;
950
447
951
447
    switch (SplatBitSize) {
952
447
    default:
953
0
      return false;
954
447
    case 8:
955
267
      LdiOp = Mips::LDI_B;
956
267
      ViaVecTy = MVT::v16i8;
957
267
      break;
958
447
    case 16:
959
55
      LdiOp = Mips::LDI_H;
960
55
      ViaVecTy = MVT::v8i16;
961
55
      break;
962
447
    case 32:
963
70
      LdiOp = Mips::LDI_W;
964
70
      ViaVecTy = MVT::v4i32;
965
70
      break;
966
447
    case 64:
967
55
      LdiOp = Mips::LDI_D;
968
55
      ViaVecTy = MVT::v2i64;
969
55
      break;
970
447
    }
971
447
972
447
    SDNode *Res;
973
447
974
447
    // If we have a signed 10 bit integer, we can splat it directly.
975
447
    //
976
447
    // If we have something bigger we can synthesize the value into a GPR and
977
447
    // splat from there.
978
447
    if (SplatValue.isSignedIntN(10)) {
979
399
      SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
980
399
                                              ViaVecTy.getVectorElementType());
981
399
982
399
      Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
983
399
    } else 
if (48
SplatValue.isSignedIntN(16)48
&&
984
48
               
(0
(0
ABI.IsO32()0
&&
SplatBitSize < 640
) ||
985
0
                (ABI.IsN32() || ABI.IsN64()))) {
986
0
      // Only handle signed 16 bit values when the element size is GPR width.
987
0
      // MIPS64 can handle all the cases but MIPS32 would need to handle
988
0
      // negative cases specifically here. Instead, handle those cases as
989
0
      // 64bit values.
990
0
991
0
      bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
992
0
      const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
993
0
      const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
994
0
      SDValue ZeroVal = CurDAG->getRegister(
995
0
          Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
996
0
997
0
      const unsigned FILLOp =
998
0
          SplatBitSize == 16
999
0
              ? Mips::FILL_H
1000
0
              : (SplatBitSize == 32 ? Mips::FILL_W
1001
0
                                    : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1002
0
1003
0
      assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1004
0
      assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1005
0
             "Attempting to use fill.d on MIPS32!");
1006
0
1007
0
      const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1008
0
      SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1009
0
1010
0
      Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1011
0
      Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1012
0
1013
48
    } else if (SplatValue.isSignedIntN(32) && 
SplatBitSize == 3224
) {
1014
24
      // Only handle the cases where the splat size agrees with the size
1015
24
      // of the SplatValue here.
1016
24
      const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1017
24
      const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1018
24
      SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1019
24
1020
24
      SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1021
24
      SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1022
24
1023
24
      if (Hi)
1024
24
        Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1025
24
1026
24
      if (Lo)
1027
18
        Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1028
18
                                     Hi ? SDValue(Res, 0) : 
ZeroVal0
, LoVal);
1029
24
1030
24
      assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1031
24
      Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1032
24
1033
24
    } else if (SplatValue.isSignedIntN(32) && 
SplatBitSize == 640
&&
1034
24
               
(0
ABI.IsN32()0
||
ABI.IsN64()0
)) {
1035
0
      // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1036
0
      // integers due to having 64bit registers. lui will cause the necessary
1037
0
      // zero/sign extension.
1038
0
      const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1039
0
      const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1040
0
      SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1041
0
1042
0
      SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1043
0
      SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1044
0
1045
0
      if (Hi)
1046
0
        Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1047
0
1048
0
      if (Lo)
1049
0
        Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1050
0
                                     Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1051
0
1052
0
      Res = CurDAG->getMachineNode(
1053
0
              Mips::SUBREG_TO_REG, DL, MVT::i64,
1054
0
              CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1055
0
              SDValue(Res, 0),
1056
0
              CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1057
0
1058
0
      Res =
1059
0
          CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1060
0
1061
24
    } else if (SplatValue.isSignedIntN(64)) {
1062
24
      // If we have a 64 bit Splat value, we perform a similar sequence to the
1063
24
      // above:
1064
24
      //
1065
24
      // MIPS32:                            MIPS64:
1066
24
      //   lui $res, %highest(val)            lui $res, %highest(val)
1067
24
      //   ori $res, $res, %higher(val)       ori $res, $res, %higher(val)
1068
24
      //   lui $res2, %hi(val)                lui $res2, %hi(val)
1069
24
      //   ori $res2, %res2, %lo(val)         ori $res2, %res2, %lo(val)
1070
24
      //   $res3 = fill $res2                 dinsu $res, $res2, 0, 32
1071
24
      //   $res4 = insert.w $res3[1], $res    fill.d $res
1072
24
      //   splat.d $res4, 0
1073
24
      //
1074
24
      // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1075
24
      // having to materialize the value by shifts and ors.
1076
24
      //
1077
24
      // FIXME: Implement the preferred sequence for MIPS64R6:
1078
24
      //
1079
24
      // MIPS64R6:
1080
24
      //   ori $res, $zero, %lo(val)
1081
24
      //   daui $res, $res, %hi(val)
1082
24
      //   dahi $res, $res, %higher(val)
1083
24
      //   dati $res, $res, %highest(cal)
1084
24
      //   fill.d $res
1085
24
      //
1086
24
1087
24
      const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1088
24
      const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1089
24
      const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1090
24
      const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1091
24
1092
24
      SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1093
24
      SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1094
24
      SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1095
24
      SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1096
24
      SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1097
24
1098
24
      // Independent of whether we're targeting MIPS64 or not, the basic
1099
24
      // operations are the same. Also, directly use the $zero register if
1100
24
      // the 16 bit chunk is zero.
1101
24
      //
1102
24
      // For optimization purposes we always synthesize the splat value as
1103
24
      // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1104
24
      // just before combining the values with dinsu to produce an i64. This
1105
24
      // enables SelectionDAG to aggressively share components of splat values
1106
24
      // where possible.
1107
24
      //
1108
24
      // FIXME: This is the general constant synthesis problem. This code
1109
24
      //        should be factored out into a class shared between all the
1110
24
      //        classes that need it. Specifically, for a splat size of 64
1111
24
      //        bits that's a negative number we can do better than LUi/ORi
1112
24
      //        for the upper 32bits.
1113
24
1114
24
      if (Hi)
1115
18
        Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1116
24
1117
24
      if (Lo)
1118
24
        Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1119
24
                                     Hi ? 
SDValue(Res, 0)18
:
ZeroVal6
, LoVal);
1120
24
1121
24
      SDNode *HiRes;
1122
24
      if (Highest)
1123
16
        HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1124
24
1125
24
      if (Higher)
1126
22
        HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1127
22
                                       Highest ? 
SDValue(HiRes, 0)16
:
ZeroVal6
,
1128
22
                                       HigherVal);
1129
24
1130
24
1131
24
      if (ABI.IsO32()) {
1132
10
        Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1133
10
                                     (Hi || 
Lo2
) ? SDValue(Res, 0) :
ZeroVal0
);
1134
10
1135
10
        Res = CurDAG->getMachineNode(
1136
10
            Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1137
10
            (Highest || 
Higher4
) ?
SDValue(HiRes, 0)8
:
ZeroVal2
,
1138
10
            CurDAG->getTargetConstant(1, DL, MVT::i32));
1139
10
1140
10
        const TargetLowering *TLI = getTargetLowering();
1141
10
        const TargetRegisterClass *RC =
1142
10
            TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1143
10
1144
10
        Res = CurDAG->getMachineNode(
1145
10
            Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1146
10
            CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1147
10
1148
10
        Res = CurDAG->getMachineNode(
1149
10
            Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1150
10
            CurDAG->getTargetConstant(0, DL, MVT::i32));
1151
14
      } else if (ABI.IsN64() || 
ABI.IsN32()6
) {
1152
14
1153
14
        SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1154
14
        const bool HiResNonZero = Highest || 
Higher4
;
1155
14
        const bool ResNonZero = Hi || 
Lo4
;
1156
14
1157
14
        if (HiResNonZero)
1158
14
          HiRes = CurDAG->getMachineNode(
1159
14
              Mips::SUBREG_TO_REG, DL, MVT::i64,
1160
14
              CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1161
14
              SDValue(HiRes, 0),
1162
14
              CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1163
14
1164
14
        if (ResNonZero)
1165
14
          Res = CurDAG->getMachineNode(
1166
14
              Mips::SUBREG_TO_REG, DL, MVT::i64,
1167
14
              CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1168
14
              SDValue(Res, 0),
1169
14
              CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1170
14
1171
14
        // We have 3 cases:
1172
14
        //   The HiRes is nonzero but Res is $zero  => dsll32 HiRes, 0
1173
14
        //   The Res is nonzero but HiRes is $zero  => dinsu Res, $zero, 32, 32
1174
14
        //   Both are non zero                      => dinsu Res, HiRes, 32, 32
1175
14
        //
1176
14
        // The obvious "missing" case is when both are zero, but that case is
1177
14
        // handled by the ldi case.
1178
14
        if (ResNonZero) {
1179
14
          IntegerType *Int32Ty =
1180
14
              IntegerType::get(MF->getFunction().getContext(), 32);
1181
14
          const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1182
14
          SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : 
Zero64Val0
,
1183
14
                            CurDAG->getConstant(*Const32, DL, MVT::i32),
1184
14
                            CurDAG->getConstant(*Const32, DL, MVT::i32),
1185
14
                            SDValue(Res, 0)};
1186
14
1187
14
          Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1188
14
        } else 
if (0
HiResNonZero0
) {
1189
0
          Res = CurDAG->getMachineNode(
1190
0
              Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1191
0
              CurDAG->getTargetConstant(0, DL, MVT::i32));
1192
0
        } else
1193
0
          llvm_unreachable(
1194
14
              "Zero splat value handled by non-zero 64bit splat synthesis!");
1195
14
1196
14
        Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1197
14
      } else
1198
14
        
llvm_unreachable0
("Unknown ABI in MipsISelDAGToDAG!");
1199
24
1200
24
    } else
1201
0
      return false;
1202
447
1203
447
    if (ResVecTy != ViaVecTy) {
1204
297
      // If LdiOp is writing to a different register class to ResVecTy, then
1205
297
      // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1206
297
      // since the source and destination register sets contain the same
1207
297
      // registers.
1208
297
      const TargetLowering *TLI = getTargetLowering();
1209
297
      MVT ResVecTySimple = ResVecTy.getSimpleVT();
1210
297
      const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1211
297
      Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1212
297
                                   ResVecTy, SDValue(Res, 0),
1213
297
                                   CurDAG->getTargetConstant(RC->getID(), DL,
1214
297
                                                             MVT::i32));
1215
297
    }
1216
447
1217
447
    ReplaceNode(Node, Res);
1218
447
    return true;
1219
447
  }
1220
198k
1221
198k
  }
1222
198k
1223
198k
  return false;
1224
198k
}
1225
1226
bool MipsSEDAGToDAGISel::
1227
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1228
59
                             std::vector<SDValue> &OutOps) {
1229
59
  SDValue Base, Offset;
1230
59
1231
59
  switch(ConstraintID) {
1232
59
  default:
1233
0
    llvm_unreachable("Unexpected asm memory constraint");
1234
59
  // All memory constraints can at least accept raw pointers.
1235
59
  case InlineAsm::Constraint_i:
1236
0
    OutOps.push_back(Op);
1237
0
    OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1238
0
    return false;
1239
59
  case InlineAsm::Constraint_m:
1240
20
  case InlineAsm::Constraint_o:
1241
20
    if (selectAddrRegImm16(Op, Base, Offset)) {
1242
16
      OutOps.push_back(Base);
1243
16
      OutOps.push_back(Offset);
1244
16
      return false;
1245
16
    }
1246
4
    OutOps.push_back(Op);
1247
4
    OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1248
4
    return false;
1249
4
  case InlineAsm::Constraint_R:
1250
4
    // The 'R' constraint is supposed to be much more complicated than this.
1251
4
    // However, it's becoming less useful due to architectural changes and
1252
4
    // ought to be replaced by other constraints such as 'ZC'.
1253
4
    // For now, support 9-bit signed offsets which is supportable by all
1254
4
    // subtargets for all instructions.
1255
4
    if (selectAddrRegImm9(Op, Base, Offset)) {
1256
2
      OutOps.push_back(Base);
1257
2
      OutOps.push_back(Offset);
1258
2
      return false;
1259
2
    }
1260
2
    OutOps.push_back(Op);
1261
2
    OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1262
2
    return false;
1263
35
  case InlineAsm::Constraint_ZC:
1264
35
    // ZC matches whatever the pref, ll, and sc instructions can handle for the
1265
35
    // given subtarget.
1266
35
    if (Subtarget->inMicroMipsMode()) {
1267
9
      // On microMIPS, they can handle 12-bit offsets.
1268
9
      if (selectAddrRegImm12(Op, Base, Offset)) {
1269
5
        OutOps.push_back(Base);
1270
5
        OutOps.push_back(Offset);
1271
5
        return false;
1272
5
      }
1273
26
    } else if (Subtarget->hasMips32r6()) {
1274
13
      // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1275
13
      if (selectAddrRegImm9(Op, Base, Offset)) {
1276
7
        OutOps.push_back(Base);
1277
7
        OutOps.push_back(Offset);
1278
7
        return false;
1279
7
      }
1280
13
    } else if (selectAddrRegImm16(Op, Base, Offset)) {
1281
11
      // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1282
11
      OutOps.push_back(Base);
1283
11
      OutOps.push_back(Offset);
1284
11
      return false;
1285
11
    }
1286
12
    // In all cases, 0-bit offsets are acceptable.
1287
12
    OutOps.push_back(Op);
1288
12
    OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1289
12
    return false;
1290
0
  }
1291
0
  return true;
1292
0
}
1293
1294
FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
1295
2.03k
                                        CodeGenOpt::Level OptLevel) {
1296
2.03k
  return new MipsSEDAGToDAGISel(TM, OptLevel);
1297
2.03k
}