Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MipsSEInstrInfo.h"
14
#include "MCTargetDesc/MipsInstPrinter.h"
15
#include "MipsAnalyzeImmediate.h"
16
#include "MipsMachineFunction.h"
17
#include "MipsTargetMachine.h"
18
#include "llvm/ADT/STLExtras.h"
19
#include "llvm/CodeGen/MachineInstrBuilder.h"
20
#include "llvm/CodeGen/MachineRegisterInfo.h"
21
#include "llvm/Support/ErrorHandling.h"
22
#include "llvm/Support/MathExtras.h"
23
#include "llvm/Support/TargetRegistry.h"
24
25
using namespace llvm;
26
27
8.43k
static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
28
8.43k
  if (STI.inMicroMipsMode())
29
815
    return STI.isPositionIndependent() ? 
Mips::B_MM348
:
Mips::J_MM467
;
30
7.61k
  return STI.isPositionIndependent() ? 
Mips::B2.70k
:
Mips::J4.91k
;
31
7.61k
}
32
33
MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
34
8.43k
    : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
35
36
1.89M
const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
37
1.89M
  return RI;
38
1.89M
}
39
40
/// isLoadFromStackSlot - If the specified machine instruction is a direct
41
/// load from a stack slot, return the virtual or physical register number of
42
/// the destination along with the FrameIndex of the loaded stack slot.  If
43
/// not, return 0.  This predicate must return 0 if the instruction has
44
/// any side effects other than loading from the stack slot.
45
unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
46
12.8k
                                              int &FrameIndex) const {
47
12.8k
  unsigned Opc = MI.getOpcode();
48
12.8k
49
12.8k
  if ((Opc == Mips::LW)   || 
(Opc == Mips::LD)12.7k
||
50
12.8k
      
(Opc == Mips::LWC1)12.7k
||
(Opc == Mips::LDC1)12.6k
||
(Opc == Mips::LDC164)12.6k
) {
51
135
    if ((MI.getOperand(1).isFI()) &&  // is a stack slot
52
135
        
(MI.getOperand(2).isImm())47
&& // the imm is zero
53
135
        
(isZeroImm(MI.getOperand(2)))47
) {
54
43
      FrameIndex = MI.getOperand(1).getIndex();
55
43
      return MI.getOperand(0).getReg();
56
43
    }
57
12.7k
  }
58
12.7k
59
12.7k
  return 0;
60
12.7k
}
61
62
/// isStoreToStackSlot - If the specified machine instruction is a direct
63
/// store to a stack slot, return the virtual or physical register number of
64
/// the source reg along with the FrameIndex of the loaded stack slot.  If
65
/// not, return 0.  This predicate must return 0 if the instruction has
66
/// any side effects other than storing to the stack slot.
67
unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
68
1.65k
                                             int &FrameIndex) const {
69
1.65k
  unsigned Opc = MI.getOpcode();
70
1.65k
71
1.65k
  if ((Opc == Mips::SW)   || 
(Opc == Mips::SD)1.50k
||
72
1.65k
      
(Opc == Mips::SWC1)1.50k
||
(Opc == Mips::SDC1)1.50k
||
(Opc == Mips::SDC164)1.50k
) {
73
160
    if ((MI.getOperand(1).isFI()) &&  // is a stack slot
74
160
        
(MI.getOperand(2).isImm())74
&& // the imm is zero
75
160
        
(isZeroImm(MI.getOperand(2)))74
) {
76
42
      FrameIndex = MI.getOperand(1).getIndex();
77
42
      return MI.getOperand(0).getReg();
78
42
    }
79
1.61k
  }
80
1.61k
  return 0;
81
1.61k
}
82
83
void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
84
                                  MachineBasicBlock::iterator I,
85
                                  const DebugLoc &DL, unsigned DestReg,
86
3.02k
                                  unsigned SrcReg, bool KillSrc) const {
87
3.02k
  unsigned Opc = 0, ZeroReg = 0;
88
3.02k
  bool isMicroMips = Subtarget.inMicroMipsMode();
89
3.02k
90
3.02k
  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
91
2.11k
    if (Mips::GPR32RegClass.contains(SrcReg)) {
92
1.86k
      if (isMicroMips)
93
451
        Opc = Mips::MOVE16_MM;
94
1.41k
      else
95
1.41k
        Opc = Mips::OR, ZeroReg = Mips::ZERO;
96
1.86k
    } else 
if (245
Mips::CCRRegClass.contains(SrcReg)245
)
97
0
      Opc = Mips::CFC1;
98
245
    else if (Mips::FGR32RegClass.contains(SrcReg))
99
218
      Opc = Mips::MFC1;
100
27
    else if (Mips::HI32RegClass.contains(SrcReg)) {
101
2
      Opc = isMicroMips ? 
Mips::MFHI16_MM0
: Mips::MFHI;
102
2
      SrcReg = 0;
103
25
    } else if (Mips::LO32RegClass.contains(SrcReg)) {
104
6
      Opc = isMicroMips ? 
Mips::MFLO16_MM0
: Mips::MFLO;
105
6
      SrcReg = 0;
106
19
    } else if (Mips::HI32DSPRegClass.contains(SrcReg))
107
0
      Opc = Mips::MFHI_DSP;
108
19
    else if (Mips::LO32DSPRegClass.contains(SrcReg))
109
0
      Opc = Mips::MFLO_DSP;
110
19
    else if (Mips::DSPCCRegClass.contains(SrcReg)) {
111
1
      BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
112
1
        .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
113
1
      return;
114
1
    }
115
18
    else if (Mips::MSACtrlRegClass.contains(SrcReg))
116
18
      Opc = Mips::CFCMSA;
117
2.11k
  }
118
910
  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
119
33
    if (Mips::CCRRegClass.contains(DestReg))
120
0
      Opc = Mips::CTC1;
121
33
    else if (Mips::FGR32RegClass.contains(DestReg))
122
12
      Opc = Mips::MTC1;
123
21
    else if (Mips::HI32RegClass.contains(DestReg))
124
0
      Opc = Mips::MTHI, DestReg = 0;
125
21
    else if (Mips::LO32RegClass.contains(DestReg))
126
0
      Opc = Mips::MTLO, DestReg = 0;
127
21
    else if (Mips::HI32DSPRegClass.contains(DestReg))
128
1
      Opc = Mips::MTHI_DSP;
129
20
    else if (Mips::LO32DSPRegClass.contains(DestReg))
130
1
      Opc = Mips::MTLO_DSP;
131
19
    else if (Mips::DSPCCRegClass.contains(DestReg)) {
132
1
      BuildMI(MBB, I, DL, get(Mips::WRDSP))
133
1
        .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
134
1
        .addReg(DestReg, RegState::ImplicitDefine);
135
1
      return;
136
18
    } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
137
18
      BuildMI(MBB, I, DL, get(Mips::CTCMSA))
138
18
          .addReg(DestReg)
139
18
          .addReg(SrcReg, getKillRegState(KillSrc));
140
18
      return;
141
18
    }
142
877
  }
143
877
  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
144
201
    Opc = Mips::FMOV_S;
145
676
  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
146
87
    Opc = Mips::FMOV_D32;
147
589
  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
148
98
    Opc = Mips::FMOV_D64;
149
491
  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
150
426
    if (Mips::GPR64RegClass.contains(SrcReg))
151
418
      Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
152
8
    else if (Mips::HI64RegClass.contains(SrcReg))
153
0
      Opc = Mips::MFHI64, SrcReg = 0;
154
8
    else if (Mips::LO64RegClass.contains(SrcReg))
155
0
      Opc = Mips::MFLO64, SrcReg = 0;
156
8
    else if (Mips::FGR64RegClass.contains(SrcReg))
157
8
      Opc = Mips::DMFC1;
158
426
  }
159
65
  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
160
4
    if (Mips::HI64RegClass.contains(DestReg))
161
2
      Opc = Mips::MTHI64, DestReg = 0;
162
2
    else if (Mips::LO64RegClass.contains(DestReg))
163
2
      Opc = Mips::MTLO64, DestReg = 0;
164
0
    else if (Mips::FGR64RegClass.contains(DestReg))
165
0
      Opc = Mips::DMTC1;
166
4
  }
167
61
  else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
168
61
    if (Mips::MSA128BRegClass.contains(SrcReg))
169
61
      Opc = Mips::MOVE_V;
170
61
  }
171
3.02k
172
3.02k
  assert(Opc && "Cannot copy registers");
173
3.00k
174
3.00k
  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
175
3.00k
176
3.00k
  if (DestReg)
177
2.99k
    MIB.addReg(DestReg, RegState::Define);
178
3.00k
179
3.00k
  if (SrcReg)
180
2.99k
    MIB.addReg(SrcReg, getKillRegState(KillSrc));
181
3.00k
182
3.00k
  if (ZeroReg)
183
1.83k
    MIB.addReg(ZeroReg);
184
3.00k
}
185
186
50
static bool isORCopyInst(const MachineInstr &MI) {
187
50
  switch (MI.getOpcode()) {
188
50
  default:
189
47
    break;
190
50
  case Mips::OR_MM:
191
2
  case Mips::OR:
192
2
    if (MI.getOperand(2).getReg() == Mips::ZERO)
193
2
      return true;
194
0
    break;
195
1
  case Mips::OR64:
196
1
    if (MI.getOperand(2).getReg() == Mips::ZERO_64)
197
1
      return true;
198
0
    break;
199
47
  }
200
47
  return false;
201
47
}
202
203
/// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
204
/// if it is WRDSP instruction.
205
54
static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
206
54
  switch (MI.getOpcode()) {
207
54
  default:
208
54
   return false;
209
54
  case Mips::WRDSP:
210
0
  case Mips::WRDSP_MM:
211
0
    isWrite = true;
212
0
    break;
213
0
  case Mips::RDDSP:
214
0
  case Mips::RDDSP_MM:
215
0
    isWrite = false;
216
0
    break;
217
0
  }
218
0
  return true;
219
0
}
220
221
/// We check for the common case of 'or', as it's MIPS' preferred instruction
222
/// for GPRs but we have to check the operands to ensure that is the case.
223
/// Other move instructions for MIPS are directly identifiable.
224
bool MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
225
                                      const MachineOperand *&Src,
226
54
                                      const MachineOperand *&Dest) const {
227
54
  bool isDSPControlWrite = false;
228
54
  // Condition is made to match the creation of WRDSP/RDDSP copy instruction
229
54
  // from copyPhysReg function.
230
54
  if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
231
0
    if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
232
0
      return false;
233
0
    else if (isDSPControlWrite) {
234
0
      Src = &MI.getOperand(0);
235
0
      Dest = &MI.getOperand(2);
236
0
    } else {
237
0
      Dest = &MI.getOperand(0);
238
0
      Src = &MI.getOperand(2);
239
0
    }
240
0
    return true;
241
54
  } else if (MI.isMoveReg() || 
isORCopyInst(MI)50
) {
242
7
    Dest = &MI.getOperand(0);
243
7
    Src = &MI.getOperand(1);
244
7
    return true;
245
7
  }
246
47
  return false;
247
47
}
248
249
void MipsSEInstrInfo::
250
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
251
                unsigned SrcReg, bool isKill, int FI,
252
                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
253
4.31k
                int64_t Offset) const {
254
4.31k
  DebugLoc DL;
255
4.31k
  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
256
4.31k
257
4.31k
  unsigned Opc = 0;
258
4.31k
259
4.31k
  if (Mips::GPR32RegClass.hasSubClassEq(RC))
260
2.16k
    Opc = Mips::SW;
261
2.14k
  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
262
1.72k
    Opc = Mips::SD;
263
426
  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
264
0
    Opc = Mips::STORE_ACC64;
265
426
  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
266
0
    Opc = Mips::STORE_ACC64DSP;
267
426
  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
268
2
    Opc = Mips::STORE_ACC128;
269
424
  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
270
1
    Opc = Mips::STORE_CCOND_DSP;
271
423
  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
272
27
    Opc = Mips::SWC1;
273
396
  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
274
148
    Opc = Mips::SDC1;
275
248
  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
276
217
    Opc = Mips::SDC164;
277
31
  else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
278
6
    Opc = Mips::ST_B;
279
25
  else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
280
25
           
TRI->isTypeLegalForClass(*RC, MVT::v8f16)19
)
281
6
    Opc = Mips::ST_H;
282
19
  else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
283
19
           
TRI->isTypeLegalForClass(*RC, MVT::v4f32)12
)
284
7
    Opc = Mips::ST_W;
285
12
  else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
286
12
           
TRI->isTypeLegalForClass(*RC, MVT::v2f64)6
)
287
6
    Opc = Mips::ST_D;
288
6
  else if (Mips::LO32RegClass.hasSubClassEq(RC))
289
0
    Opc = Mips::SW;
290
6
  else if (Mips::LO64RegClass.hasSubClassEq(RC))
291
0
    Opc = Mips::SD;
292
6
  else if (Mips::HI32RegClass.hasSubClassEq(RC))
293
0
    Opc = Mips::SW;
294
6
  else if (Mips::HI64RegClass.hasSubClassEq(RC))
295
0
    Opc = Mips::SD;
296
6
  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
297
6
    Opc = Mips::SWDSP;
298
4.31k
299
4.31k
  // Hi, Lo are normally caller save but they are callee save
300
4.31k
  // for interrupt handling.
301
4.31k
  const Function &Func = MBB.getParent()->getFunction();
302
4.31k
  if (Func.hasFnAttribute("interrupt")) {
303
39
    if (Mips::HI32RegClass.hasSubClassEq(RC)) {
304
0
      BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
305
0
      SrcReg = Mips::K0;
306
39
    } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
307
0
      BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
308
0
      SrcReg = Mips::K0_64;
309
39
    } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
310
0
      BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
311
0
      SrcReg = Mips::K0;
312
39
    } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
313
0
      BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
314
0
      SrcReg = Mips::K0_64;
315
0
    }
316
39
  }
317
4.31k
318
4.31k
  assert(Opc && "Register class not handled!");
319
4.31k
  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
320
4.31k
    .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
321
4.31k
}
322
323
void MipsSEInstrInfo::
324
loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
325
                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
326
4.33k
                 const TargetRegisterInfo *TRI, int64_t Offset) const {
327
4.33k
  DebugLoc DL;
328
4.33k
  if (I != MBB.end()) 
DL = I->getDebugLoc()4.29k
;
329
4.33k
  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
330
4.33k
  unsigned Opc = 0;
331
4.33k
332
4.33k
  const Function &Func = MBB.getParent()->getFunction();
333
4.33k
  bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
334
4.33k
                         
(39
DestReg == Mips::LO039
||
DestReg == Mips::LO0_6438
||
335
39
                          
DestReg == Mips::HI038
||
DestReg == Mips::HI0_6437
);
336
4.33k
337
4.33k
  if (Mips::GPR32RegClass.hasSubClassEq(RC))
338
2.17k
    Opc = Mips::LW;
339
2.15k
  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
340
1.73k
    Opc = Mips::LD;
341
422
  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
342
0
    Opc = Mips::LOAD_ACC64;
343
422
  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
344
0
    Opc = Mips::LOAD_ACC64DSP;
345
422
  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
346
2
    Opc = Mips::LOAD_ACC128;
347
420
  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
348
1
    Opc = Mips::LOAD_CCOND_DSP;
349
419
  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
350
21
    Opc = Mips::LWC1;
351
398
  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
352
140
    Opc = Mips::LDC1;
353
258
  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
354
225
    Opc = Mips::LDC164;
355
33
  else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
356
6
    Opc = Mips::LD_B;
357
27
  else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
358
27
           
TRI->isTypeLegalForClass(*RC, MVT::v8f16)21
)
359
6
    Opc = Mips::LD_H;
360
21
  else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
361
21
           
TRI->isTypeLegalForClass(*RC, MVT::v4f32)14
)
362
7
    Opc = Mips::LD_W;
363
14
  else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
364
14
           
TRI->isTypeLegalForClass(*RC, MVT::v2f64)8
)
365
6
    Opc = Mips::LD_D;
366
8
  else if (Mips::HI32RegClass.hasSubClassEq(RC))
367
1
    Opc = Mips::LW;
368
7
  else if (Mips::HI64RegClass.hasSubClassEq(RC))
369
0
    Opc = Mips::LD;
370
7
  else if (Mips::LO32RegClass.hasSubClassEq(RC))
371
1
    Opc = Mips::LW;
372
6
  else if (Mips::LO64RegClass.hasSubClassEq(RC))
373
0
    Opc = Mips::LD;
374
6
  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
375
6
    Opc = Mips::LWDSP;
376
4.33k
377
4.33k
  assert(Opc && "Register class not handled!");
378
4.33k
379
4.33k
  if (!ReqIndirectLoad)
380
4.32k
    BuildMI(MBB, I, DL, get(Opc), DestReg)
381
4.32k
        .addFrameIndex(FI)
382
4.32k
        .addImm(Offset)
383
4.32k
        .addMemOperand(MMO);
384
2
  else {
385
2
    // Load HI/LO through K0. Notably the DestReg is encoded into the
386
2
    // instruction itself.
387
2
    unsigned Reg = Mips::K0;
388
2
    unsigned LdOp = Mips::MTLO;
389
2
    if (DestReg == Mips::HI0)
390
1
      LdOp = Mips::MTHI;
391
2
392
2
    if (Subtarget.getABI().ArePtrs64bit()) {
393
0
      Reg = Mips::K0_64;
394
0
      if (DestReg == Mips::HI0_64)
395
0
        LdOp = Mips::MTHI64;
396
0
      else
397
0
        LdOp = Mips::MTLO64;
398
0
    }
399
2
400
2
    BuildMI(MBB, I, DL, get(Opc), Reg)
401
2
        .addFrameIndex(FI)
402
2
        .addImm(Offset)
403
2
        .addMemOperand(MMO);
404
2
    BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
405
2
  }
406
4.33k
}
407
408
26.7k
bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
409
26.7k
  MachineBasicBlock &MBB = *MI.getParent();
410
26.7k
  bool isMicroMips = Subtarget.inMicroMipsMode();
411
26.7k
  unsigned Opc;
412
26.7k
413
26.7k
  switch (MI.getDesc().getOpcode()) {
414
26.7k
  default:
415
13.1k
    return false;
416
26.7k
  case Mips::RetRA:
417
12.7k
    expandRetRA(MBB, MI);
418
12.7k
    break;
419
26.7k
  case Mips::ERet:
420
9
    expandERet(MBB, MI);
421
9
    break;
422
26.7k
  case Mips::PseudoMFHI:
423
134
    expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
424
134
    break;
425
26.7k
  case Mips::PseudoMFHI_MM:
426
8
    expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
427
8
    break;
428
26.7k
  case Mips::PseudoMFLO:
429
150
    expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
430
150
    break;
431
26.7k
  case Mips::PseudoMFLO_MM:
432
8
    expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
433
8
    break;
434
26.7k
  case Mips::PseudoMFHI64:
435
50
    expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
436
50
    break;
437
26.7k
  case Mips::PseudoMFLO64:
438
101
    expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
439
101
    break;
440
26.7k
  case Mips::PseudoMTLOHI:
441
12
    expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
442
12
    break;
443
26.7k
  case Mips::PseudoMTLOHI64:
444
0
    expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
445
0
    break;
446
26.7k
  case Mips::PseudoMTLOHI_DSP:
447
49
    expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
448
49
    break;
449
26.7k
  case Mips::PseudoMTLOHI_MM:
450
1
    expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
451
1
    break;
452
26.7k
  case Mips::PseudoCVT_S_W:
453
18
    expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
454
18
    break;
455
26.7k
  case Mips::PseudoCVT_D32_W:
456
12
    Opc = isMicroMips ? 
Mips::CVT_D32_W_MM1
:
Mips::CVT_D32_W11
;
457
12
    expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
458
12
    break;
459
26.7k
  case Mips::PseudoCVT_S_L:
460
2
    expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
461
2
    break;
462
26.7k
  case Mips::PseudoCVT_D64_W:
463
8
    Opc = isMicroMips ? 
Mips::CVT_D64_W_MM2
:
Mips::CVT_D64_W6
;
464
8
    expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
465
8
    break;
466
26.7k
  case Mips::PseudoCVT_D64_L:
467
2
    expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
468
2
    break;
469
26.7k
  case Mips::BuildPairF64:
470
132
    expandBuildPairF64(MBB, MI, isMicroMips, false);
471
132
    break;
472
26.7k
  case Mips::BuildPairF64_64:
473
47
    expandBuildPairF64(MBB, MI, isMicroMips, true);
474
47
    break;
475
26.7k
  case Mips::ExtractElementF64:
476
120
    expandExtractElementF64(MBB, MI, isMicroMips, false);
477
120
    break;
478
26.7k
  case Mips::ExtractElementF64_64:
479
46
    expandExtractElementF64(MBB, MI, isMicroMips, true);
480
46
    break;
481
26.7k
  case Mips::MIPSeh_return32:
482
14
  case Mips::MIPSeh_return64:
483
14
    expandEhReturn(MBB, MI);
484
14
    break;
485
13.6k
  }
486
13.6k
487
13.6k
  MBB.erase(MI);
488
13.6k
  return true;
489
13.6k
}
490
491
/// getOppositeBranchOpc - Return the inverse of the specified
492
/// opcode, e.g. turning BEQ to BNE.
493
413
unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
494
413
  switch (Opc) {
495
413
  
default: 0
llvm_unreachable0
("Illegal opcode!");
496
413
  
case Mips::BEQ: return Mips::BNE58
;
497
413
  
case Mips::BEQ_MM: return Mips::BNE_MM3
;
498
413
  
case Mips::BNE: return Mips::BEQ93
;
499
413
  
case Mips::BNE_MM: return Mips::BEQ_MM2
;
500
413
  
case Mips::BGTZ: return Mips::BLEZ6
;
501
413
  
case Mips::BGEZ: return Mips::BLTZ12
;
502
413
  
case Mips::BLTZ: return Mips::BGEZ2
;
503
413
  
case Mips::BLEZ: return Mips::BGTZ8
;
504
413
  
case Mips::BGTZ_MM: return Mips::BLEZ_MM2
;
505
413
  
case Mips::BGEZ_MM: return Mips::BLTZ_MM2
;
506
413
  
case Mips::BLTZ_MM: return Mips::BGEZ_MM2
;
507
413
  
case Mips::BLEZ_MM: return Mips::BGTZ_MM3
;
508
413
  
case Mips::BEQ64: return Mips::BNE6413
;
509
413
  
case Mips::BNE64: return Mips::BEQ6411
;
510
413
  
case Mips::BGTZ64: return Mips::BLEZ642
;
511
413
  
case Mips::BGEZ64: return Mips::BLTZ642
;
512
413
  
case Mips::BLTZ64: return Mips::BGEZ642
;
513
413
  
case Mips::BLEZ64: return Mips::BGTZ643
;
514
413
  
case Mips::BC1T: return Mips::BC1F17
;
515
413
  
case Mips::BC1F: return Mips::BC1T28
;
516
413
  
case Mips::BC1T_MM: return Mips::BC1F_MM2
;
517
413
  
case Mips::BC1F_MM: return Mips::BC1T_MM0
;
518
413
  
case Mips::BEQZ16_MM: return Mips::BNEZ16_MM2
;
519
413
  
case Mips::BNEZ16_MM: return Mips::BEQZ16_MM2
;
520
413
  
case Mips::BEQZC_MM: return Mips::BNEZC_MM3
;
521
413
  
case Mips::BNEZC_MM: return Mips::BEQZC_MM2
;
522
413
  
case Mips::BEQZC: return Mips::BNEZC5
;
523
413
  
case Mips::BNEZC: return Mips::BEQZC14
;
524
413
  
case Mips::BLEZC: return Mips::BGTZC3
;
525
413
  
case Mips::BGEZC: return Mips::BLTZC2
;
526
413
  
case Mips::BGEC: return Mips::BLTC2
;
527
413
  
case Mips::BGTZC: return Mips::BLEZC3
;
528
413
  
case Mips::BLTZC: return Mips::BGEZC4
;
529
413
  
case Mips::BLTC: return Mips::BGEC2
;
530
413
  
case Mips::BGEUC: return Mips::BLTUC2
;
531
413
  
case Mips::BLTUC: return Mips::BGEUC2
;
532
413
  
case Mips::BEQC: return Mips::BNEC2
;
533
413
  
case Mips::BNEC: return Mips::BEQC2
;
534
413
  
case Mips::BC1EQZ: return Mips::BC1NEZ2
;
535
413
  
case Mips::BC1NEZ: return Mips::BC1EQZ2
;
536
413
  
case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR66
;
537
413
  
case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR66
;
538
413
  
case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR62
;
539
413
  
case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR62
;
540
413
  
case Mips::BGEC_MMR6: return Mips::BLTC_MMR62
;
541
413
  
case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR62
;
542
413
  
case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR62
;
543
413
  
case Mips::BLTC_MMR6: return Mips::BGEC_MMR62
;
544
413
  
case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR62
;
545
413
  
case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR62
;
546
413
  
case Mips::BEQC_MMR6: return Mips::BNEC_MMR62
;
547
413
  
case Mips::BNEC_MMR6: return Mips::BEQC_MMR62
;
548
413
  
case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR62
;
549
413
  
case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR62
;
550
413
  
case Mips::BEQZC64: return Mips::BNEZC640
;
551
413
  
case Mips::BNEZC64: return Mips::BEQZC640
;
552
413
  
case Mips::BEQC64: return Mips::BNEC642
;
553
413
  
case Mips::BNEC64: return Mips::BEQC642
;
554
413
  
case Mips::BGEC64: return Mips::BLTC642
;
555
413
  
case Mips::BGEUC64: return Mips::BLTUC642
;
556
413
  
case Mips::BLTC64: return Mips::BGEC642
;
557
413
  
case Mips::BLTUC64: return Mips::BGEUC642
;
558
413
  
case Mips::BGTZC64: return Mips::BLEZC642
;
559
413
  
case Mips::BGEZC64: return Mips::BLTZC642
;
560
413
  
case Mips::BLTZC64: return Mips::BGEZC642
;
561
413
  
case Mips::BLEZC64: return Mips::BGTZC642
;
562
413
  
case Mips::BBIT0: return Mips::BBIT12
;
563
413
  
case Mips::BBIT1: return Mips::BBIT02
;
564
413
  
case Mips::BBIT032: return Mips::BBIT1322
;
565
413
  
case Mips::BBIT132: return Mips::BBIT0322
;
566
413
  
case Mips::BZ_B: return Mips::BNZ_B2
;
567
413
  
case Mips::BZ_H: return Mips::BNZ_H2
;
568
413
  
case Mips::BZ_W: return Mips::BNZ_W2
;
569
413
  
case Mips::BZ_D: return Mips::BNZ_D2
;
570
413
  
case Mips::BZ_V: return Mips::BNZ_V2
;
571
413
  
case Mips::BNZ_B: return Mips::BZ_B2
;
572
413
  
case Mips::BNZ_H: return Mips::BZ_H2
;
573
413
  
case Mips::BNZ_W: return Mips::BZ_W2
;
574
413
  
case Mips::BNZ_D: return Mips::BZ_D2
;
575
413
  
case Mips::BNZ_V: return Mips::BZ_V2
;
576
413
  }
577
413
}
578
579
/// Adjust SP by Amount bytes.
580
void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
581
                                     MachineBasicBlock &MBB,
582
5.27k
                                     MachineBasicBlock::iterator I) const {
583
5.27k
  MipsABIInfo ABI = Subtarget.getABI();
584
5.27k
  DebugLoc DL;
585
5.27k
  unsigned ADDiu = ABI.GetPtrAddiuOp();
586
5.27k
587
5.27k
  if (Amount == 0)
588
156
    return;
589
5.12k
590
5.12k
  if (isInt<16>(Amount)) {
591
5.06k
    // addi sp, sp, amount
592
5.06k
    BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
593
5.06k
  } else {
594
60
    // For numbers which are not 16bit integers we synthesize Amount inline
595
60
    // then add or subtract it from sp.
596
60
    unsigned Opc = ABI.GetPtrAdduOp();
597
60
    if (Amount < 0) {
598
30
      Opc = ABI.GetPtrSubuOp();
599
30
      Amount = -Amount;
600
30
    }
601
60
    unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
602
60
    BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
603
60
  }
604
5.12k
}
605
606
/// This function generates the sequence of instructions needed to get the
607
/// result of adding register REG and immediate IMM.
608
unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
609
                                        MachineBasicBlock::iterator II,
610
                                        const DebugLoc &DL,
611
156
                                        unsigned *NewImm) const {
612
156
  MipsAnalyzeImmediate AnalyzeImm;
613
156
  const MipsSubtarget &STI = Subtarget;
614
156
  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
615
156
  unsigned Size = STI.isABI_N64() ? 
6432
:
32124
;
616
156
  unsigned LUi = STI.isABI_N64() ? 
Mips::LUi6432
:
Mips::LUi124
;
617
156
  unsigned ZEROReg = STI.isABI_N64() ? 
Mips::ZERO_6432
:
Mips::ZERO124
;
618
156
  const TargetRegisterClass *RC = STI.isABI_N64() ?
619
124
    
&Mips::GPR64RegClass32
: &Mips::GPR32RegClass;
620
156
  bool LastInstrIsADDiu = NewImm;
621
156
622
156
  const MipsAnalyzeImmediate::InstSeq &Seq =
623
156
    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
624
156
  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
625
156
626
156
  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
627
156
628
156
  // The first instruction can be a LUi, which is different from other
629
156
  // instructions (ADDiu, ORI and SLL) in that it does not have a register
630
156
  // operand.
631
156
  unsigned Reg = RegInfo.createVirtualRegister(RC);
632
156
633
156
  if (Inst->Opc == LUi)
634
88
    BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
635
68
  else
636
68
    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
637
68
      .addImm(SignExtend64<16>(Inst->ImmOpnd));
638
156
639
156
  // Build the remaining instructions in Seq.
640
178
  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; 
++Inst22
)
641
22
    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
642
22
      .addImm(SignExtend64<16>(Inst->ImmOpnd));
643
156
644
156
  if (LastInstrIsADDiu)
645
64
    *NewImm = Inst->ImmOpnd;
646
156
647
156
  return Reg;
648
156
}
649
650
129k
unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
651
129k
  return (Opc == Mips::BEQ    || 
Opc == Mips::BEQ_MM125k
||
Opc == Mips::BNE125k
||
652
129k
          
Opc == Mips::BNE_MM117k
||
Opc == Mips::BGTZ117k
||
Opc == Mips::BGEZ117k
||
653
129k
          
Opc == Mips::BLTZ117k
||
Opc == Mips::BLEZ117k
||
Opc == Mips::BEQ64116k
||
654
129k
          
Opc == Mips::BNE64116k
||
Opc == Mips::BGTZ64116k
||
Opc == Mips::BGEZ64116k
||
655
129k
          
Opc == Mips::BLTZ64116k
||
Opc == Mips::BLEZ64116k
||
Opc == Mips::BC1T116k
||
656
129k
          
Opc == Mips::BC1F115k
||
Opc == Mips::B114k
||
Opc == Mips::J111k
||
657
129k
          
Opc == Mips::J_MM106k
||
Opc == Mips::B_MM106k
||
Opc == Mips::BEQZC_MM106k
||
658
129k
          
Opc == Mips::BNEZC_MM106k
||
Opc == Mips::BEQC106k
||
Opc == Mips::BNEC106k
||
659
129k
          
Opc == Mips::BLTC106k
||
Opc == Mips::BGEC106k
||
Opc == Mips::BLTUC106k
||
660
129k
          
Opc == Mips::BGEUC106k
||
Opc == Mips::BGTZC106k
||
Opc == Mips::BLEZC106k
||
661
129k
          
Opc == Mips::BGEZC106k
||
Opc == Mips::BLTZC106k
||
Opc == Mips::BEQZC106k
||
662
129k
          
Opc == Mips::BNEZC105k
||
Opc == Mips::BEQZC64105k
||
Opc == Mips::BNEZC64105k
||
663
129k
          
Opc == Mips::BEQC64105k
||
Opc == Mips::BNEC64105k
||
Opc == Mips::BGEC64105k
||
664
129k
          
Opc == Mips::BGEUC64105k
||
Opc == Mips::BLTC64105k
||
Opc == Mips::BLTUC64105k
||
665
129k
          
Opc == Mips::BGTZC64105k
||
Opc == Mips::BGEZC64105k
||
666
129k
          
Opc == Mips::BLTZC64105k
||
Opc == Mips::BLEZC64105k
||
Opc == Mips::BC105k
||
667
129k
          
Opc == Mips::BBIT0105k
||
Opc == Mips::BBIT1105k
||
Opc == Mips::BBIT032105k
||
668
129k
          
Opc == Mips::BBIT132105k
||
Opc == Mips::BC_MMR6105k
||
669
129k
          
Opc == Mips::BEQC_MMR6105k
||
Opc == Mips::BNEC_MMR6105k
||
670
129k
          
Opc == Mips::BLTC_MMR6105k
||
Opc == Mips::BGEC_MMR6105k
||
671
129k
          
Opc == Mips::BLTUC_MMR6105k
||
Opc == Mips::BGEUC_MMR6105k
||
672
129k
          
Opc == Mips::BGTZC_MMR6105k
||
Opc == Mips::BLEZC_MMR6105k
||
673
129k
          
Opc == Mips::BGEZC_MMR6105k
||
Opc == Mips::BLTZC_MMR6105k
||
674
129k
          
Opc == Mips::BEQZC_MMR6105k
||
Opc == Mips::BNEZC_MMR6105k
) ?
Opc23.9k
:
0105k
;
675
129k
}
676
677
void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
678
12.7k
                                  MachineBasicBlock::iterator I) const {
679
12.7k
680
12.7k
  MachineInstrBuilder MIB;
681
12.7k
  if (Subtarget.isGP64bit())
682
4.60k
    MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
683
4.60k
              .addReg(Mips::RA_64, RegState::Undef);
684
8.14k
  else
685
8.14k
    MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
686
8.14k
              .addReg(Mips::RA, RegState::Undef);
687
12.7k
688
12.7k
  // Retain any imp-use flags.
689
12.7k
  for (auto & MO : I->operands()) {
690
9.76k
    if (MO.isImplicit())
691
9.73k
      MIB.add(MO);
692
9.76k
  }
693
12.7k
}
694
695
void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
696
9
                                 MachineBasicBlock::iterator I) const {
697
9
  BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
698
9
}
699
700
std::pair<bool, bool>
701
MipsSEInstrInfo::compareOpndSize(unsigned Opc,
702
42
                                 const MachineFunction &MF) const {
703
42
  const MCInstrDesc &Desc = get(Opc);
704
42
  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
705
42
  const MipsRegisterInfo *RI = &getRegisterInfo();
706
42
  unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
707
42
  unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
708
42
709
42
  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
710
42
}
711
712
void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
713
                                         MachineBasicBlock::iterator I,
714
451
                                         unsigned NewOpc) const {
715
451
  BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
716
451
}
717
718
void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
719
                                         MachineBasicBlock::iterator I,
720
                                         unsigned LoOpc,
721
                                         unsigned HiOpc,
722
62
                                         bool HasExplicitDef) const {
723
62
  // Expand
724
62
  //  lo_hi pseudomtlohi $gpr0, $gpr1
725
62
  // to these two instructions:
726
62
  //  mtlo $gpr0
727
62
  //  mthi $gpr1
728
62
729
62
  DebugLoc DL = I->getDebugLoc();
730
62
  const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
731
62
  MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
732
62
  MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
733
62
734
62
  // Add lo/hi registers if the mtlo/hi instructions created have explicit
735
62
  // def registers.
736
62
  if (HasExplicitDef) {
737
49
    unsigned DstReg = I->getOperand(0).getReg();
738
49
    unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
739
49
    unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
740
49
    LoInst.addReg(DstLo, RegState::Define);
741
49
    HiInst.addReg(DstHi, RegState::Define);
742
49
  }
743
62
744
62
  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
745
62
  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
746
62
}
747
748
void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
749
                                     MachineBasicBlock::iterator I,
750
                                     unsigned CvtOpc, unsigned MovOpc,
751
42
                                     bool IsI64) const {
752
42
  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
753
42
  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
754
42
  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
755
42
  unsigned KillSrc =  getKillRegState(Src.isKill());
756
42
  DebugLoc DL = I->getDebugLoc();
757
42
  bool DstIsLarger, SrcIsLarger;
758
42
759
42
  std::tie(DstIsLarger, SrcIsLarger) =
760
42
      compareOpndSize(CvtOpc, *MBB.getParent());
761
42
762
42
  if (DstIsLarger)
763
20
    TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
764
42
765
42
  if (SrcIsLarger)
766
2
    DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
767
42
768
42
  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
769
42
  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
770
42
}
771
772
void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
773
                                              MachineBasicBlock::iterator I,
774
                                              bool isMicroMips,
775
166
                                              bool FP64) const {
776
166
  unsigned DstReg = I->getOperand(0).getReg();
777
166
  unsigned SrcReg = I->getOperand(1).getReg();
778
166
  unsigned N = I->getOperand(2).getImm();
779
166
  DebugLoc dl = I->getDebugLoc();
780
166
781
166
  assert(N < 2 && "Invalid immediate");
782
166
  unsigned SubIdx = N ? 
Mips::sub_hi84
:
Mips::sub_lo82
;
783
166
  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
784
166
785
166
  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
786
166
  // in MipsSEFrameLowering.cpp.
787
166
  assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
788
166
789
166
  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
790
166
  // in MipsSEFrameLowering.cpp.
791
166
  assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
792
166
793
166
  if (SubIdx == Mips::sub_hi && 
Subtarget.hasMTHC1()84
) {
794
50
    // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
795
50
    //        claim to read the whole 64-bits as part of a white lie used to
796
50
    //        temporarily work around a widespread bug in the -mfp64 support.
797
50
    //        The problem is that none of the 32-bit fpu ops mention the fact
798
50
    //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
799
50
    //        requires a major overhaul of the FPU implementation which can't
800
50
    //        be done right now due to time constraints.
801
50
    //        MFHC1 is one of two instructions that are affected since they are
802
50
    //        the only instructions that don't read the lower 32-bits.
803
50
    //        We therefore pretend that it reads the bottom 32-bits to
804
50
    //        artificially create a dependency and prevent the scheduler
805
50
    //        changing the behaviour of the code.
806
50
    BuildMI(MBB, I, dl,
807
50
            get(isMicroMips ? 
(FP64 13
?
Mips::MFHC1_D64_MM6
:
Mips::MFHC1_D32_MM7
)
808
50
                            : 
(FP64 37
?
Mips::MFHC1_D6417
:
Mips::MFHC1_D3220
)),
809
50
            DstReg)
810
50
        .addReg(SrcReg);
811
50
  } else
812
116
    BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
813
166
}
814
815
void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
816
                                         MachineBasicBlock::iterator I,
817
179
                                         bool isMicroMips, bool FP64) const {
818
179
  unsigned DstReg = I->getOperand(0).getReg();
819
179
  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
820
179
  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
821
179
  DebugLoc dl = I->getDebugLoc();
822
179
  const TargetRegisterInfo &TRI = getRegisterInfo();
823
179
824
179
  // When mthc1 is available, use:
825
179
  //   mtc1 Lo, $fp
826
179
  //   mthc1 Hi, $fp
827
179
  //
828
179
  // Otherwise, for O32 FPXX ABI:
829
179
  //   spill + reload via ldc1
830
179
  // This case is handled by the frame lowering code.
831
179
  //
832
179
  // Otherwise, for FP32:
833
179
  //   mtc1 Lo, $fp
834
179
  //   mtc1 Hi, $fp + 1
835
179
  //
836
179
  // The case where dmtc1 is available doesn't need to be handled here
837
179
  // because it never creates a BuildPairF64 node.
838
179
839
179
  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
840
179
  // in MipsSEFrameLowering.cpp.
841
179
  assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
842
179
843
179
  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
844
179
  // in MipsSEFrameLowering.cpp.
845
179
  assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
846
179
847
179
  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
848
179
    .addReg(LoReg);
849
179
850
179
  if (Subtarget.hasMTHC1()) {
851
114
    // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
852
114
    //        around a widespread bug in the -mfp64 support.
853
114
    //        The problem is that none of the 32-bit fpu ops mention the fact
854
114
    //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
855
114
    //        requires a major overhaul of the FPU implementation which can't
856
114
    //        be done right now due to time constraints.
857
114
    //        MTHC1 is one of two instructions that are affected since they are
858
114
    //        the only instructions that don't read the lower 32-bits.
859
114
    //        We therefore pretend that it reads the bottom 32-bits to
860
114
    //        artificially create a dependency and prevent the scheduler
861
114
    //        changing the behaviour of the code.
862
114
    BuildMI(MBB, I, dl,
863
114
            get(isMicroMips ? 
(FP64 17
?
Mips::MTHC1_D64_MM8
:
Mips::MTHC1_D32_MM9
)
864
114
                            : 
(FP64 97
?
Mips::MTHC1_D6439
:
Mips::MTHC1_D3258
)),
865
114
            DstReg)
866
114
        .addReg(DstReg)
867
114
        .addReg(HiReg);
868
114
  } else 
if (65
Subtarget.isABI_FPXX()65
)
869
65
    
llvm_unreachable0
("BuildPairF64 not expanded in frame lowering code!");
870
65
  else
871
65
    BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
872
65
      .addReg(HiReg);
873
179
}
874
875
void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
876
14
                                     MachineBasicBlock::iterator I) const {
877
14
  // This pseudo instruction is generated as part of the lowering of
878
14
  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
879
14
  // indirect jump to TargetReg
880
14
  MipsABIInfo ABI = Subtarget.getABI();
881
14
  unsigned ADDU = ABI.GetPtrAdduOp();
882
14
  unsigned SP = Subtarget.isGP64bit() ? 
Mips::SP_648
:
Mips::SP6
;
883
14
  unsigned RA = Subtarget.isGP64bit() ? 
Mips::RA_648
:
Mips::RA6
;
884
14
  unsigned T9 = Subtarget.isGP64bit() ? 
Mips::T9_648
:
Mips::T96
;
885
14
  unsigned ZERO = Subtarget.isGP64bit() ? 
Mips::ZERO_648
:
Mips::ZERO6
;
886
14
  unsigned OffsetReg = I->getOperand(0).getReg();
887
14
  unsigned TargetReg = I->getOperand(1).getReg();
888
14
889
14
  // addu $ra, $v0, $zero
890
14
  // addu $sp, $sp, $v1
891
14
  // jr   $ra (via RetRA)
892
14
  const TargetMachine &TM = MBB.getParent()->getTarget();
893
14
  if (TM.isPositionIndependent())
894
14
    BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
895
14
        .addReg(TargetReg)
896
14
        .addReg(ZERO);
897
14
  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
898
14
      .addReg(TargetReg)
899
14
      .addReg(ZERO);
900
14
  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
901
14
  expandRetRA(MBB, I);
902
14
}
903
904
8.43k
const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
905
8.43k
  return new MipsSEInstrInfo(STI);
906
8.43k
}