Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/MipsSubtarget.cpp
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//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSubtarget.h"
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#include "Mips.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsCallLowering.h"
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#include "MipsLegalizerInfo.h"
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#include "MipsRegisterBankInfo.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MipsGenSubtargetInfo.inc"
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// FIXME: Maybe this should be on by default when Mips16 is specified
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//
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static cl::opt<bool>
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    Mixed16_32("mips-mixed-16-32", cl::init(false),
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               cl::desc("Allow for a mixture of Mips16 "
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                        "and Mips32 code in a single output file"),
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               cl::Hidden);
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static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
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                               cl::desc("Compile all functions that don't use "
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                                        "floating point as Mips 16"),
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                               cl::Hidden);
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static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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                                     cl::desc("Enable mips16 hard float."),
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                                     cl::init(false));
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static cl::opt<bool>
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    Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
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                          cl::desc("Enable mips16 constant islands."),
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                          cl::init(true));
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static cl::opt<bool>
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    GPOpt("mgpopt", cl::Hidden,
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          cl::desc("Enable gp-relative addressing of mips small data items"));
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bool MipsSubtarget::DspWarningPrinted = false;
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bool MipsSubtarget::MSAWarningPrinted = false;
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bool MipsSubtarget::VirtWarningPrinted = false;
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bool MipsSubtarget::CRCWarningPrinted = false;
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bool MipsSubtarget::GINVWarningPrinted = false;
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0
void MipsSubtarget::anchor() {}
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MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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                             bool little, const MipsTargetMachine &TM,
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                             unsigned StackAlignOverride)
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    : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
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      IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
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      NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true),
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      IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
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      HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
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      HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
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      InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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      HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
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      Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
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      HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
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      HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
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      StackAlignOverride(StackAlignOverride),
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      TM(TM), TargetTriple(TT), TSInfo(),
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      InstrInfo(
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          MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
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      FrameLowering(MipsFrameLowering::create(*this)),
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      TLInfo(MipsTargetLowering::create(TM, *this)) {
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  if (MipsArchVersion == MipsDefault)
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    MipsArchVersion = Mips32;
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  // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
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  // been tested and currently exist for the integrated assembler only.
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  if (MipsArchVersion == Mips1)
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    report_fatal_error("Code generation for MIPS-I is not implemented", false);
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  if (MipsArchVersion == Mips5)
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    report_fatal_error("Code generation for MIPS-V is not implemented", false);
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  // Check if Architecture and ABI are compatible.
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  assert(((!isGP64bit() && isABI_O32()) ||
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          (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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         "Invalid  Arch & ABI pair.");
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11.3k
  if (hasMSA() && 
!isFP64bit()958
)
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    report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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                       "See -mattr=+fp64.",
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                       false);
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11.3k
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11.3k
  if (isFP64bit() && 
!hasMips64()5.79k
&&
hasMips32()2.53k
&&
!hasMips32r2()2.03k
)
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    report_fatal_error(
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        "FPU with 64-bit registers is not available on MIPS32 pre revision 2. "
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        "Use -mcpu=mips32r2 or greater.");
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  if (!isABI_O32() && 
!useOddSPReg()3.76k
)
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    report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
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11.3k
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11.3k
  if (IsFPXX && 
(70
isABI_N32()70
||
isABI_N64()70
))
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    report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
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11.3k
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11.3k
  if (hasMips64r6() && 
InMicroMipsMode542
)
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    report_fatal_error("microMIPS64R6 is not supported", false);
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11.3k
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  if (!isABI_O32() && 
InMicroMipsMode3.75k
)
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    report_fatal_error("microMIPS64 is not supported.", false);
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  if (UseIndirectJumpsHazard) {
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    if (InMicroMipsMode)
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      report_fatal_error(
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          "cannot combine indirect jumps with hazard barriers and microMIPS");
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    if (!hasMips32r2())
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      report_fatal_error(
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          "indirect jumps with hazard barriers requires MIPS32R2 or later");
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  }
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  if (inAbs2008Mode() && 
hasMips32()1.51k
&&
!hasMips32r2()1.51k
) {
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    report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given "
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                       "architecture.",
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                       false);
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  }
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  if (hasMips32r6()) {
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    StringRef ISA = hasMips64r6() ? 
"MIPS64r6"541
:
"MIPS32r6"916
;
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    assert(isFP64bit());
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    assert(isNaN2008());
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    assert(inAbs2008Mode());
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    if (hasDSP())
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      report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
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  }
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  if (NoABICalls && 
TM.isPositionIndependent()119
)
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    report_fatal_error("position-independent code requires '-mabicalls'");
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  if (isABI_N64() && 
!TM.isPositionIndependent()3.23k
&&
!hasSym32()1.95k
)
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    NoABICalls = true;
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  // Set UseSmallSection.
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  UseSmallSection = GPOpt;
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  if (!NoABICalls && 
GPOpt9.30k
) {
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    errs() << "warning: cannot use small-data accesses for '-mabicalls'"
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           << "\n";
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    UseSmallSection = false;
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  }
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  if (hasDSPR2() && 
!DspWarningPrinted26
) {
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    if (hasMips64() && 
!hasMips64r2()5
) {
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      errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
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             << "greater\n";
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      DspWarningPrinted = true;
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    } else if (hasMips32() && !hasMips32r2()) {
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      errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
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             << "greater\n";
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      DspWarningPrinted = true;
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    }
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  } else if (hasDSP() && 
!DspWarningPrinted91
) {
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    if (hasMips64() && 
!hasMips64r2()5
) {
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      errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
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             << "greater\n";
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      DspWarningPrinted = true;
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    } else if (hasMips32() && !hasMips32r2()) {
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      errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
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             << "greater\n";
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      DspWarningPrinted = true;
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    }
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  }
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  StringRef ArchName = hasMips64() ? 
"MIPS64"3.25k
:
"MIPS32"8.07k
;
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  if (!hasMips32r5() && 
hasMSA()9.50k
&&
!MSAWarningPrinted801
) {
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    errs() << "warning: the 'msa' ASE requires " << ArchName
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           << " revision 5 or greater\n";
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    MSAWarningPrinted = true;
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  }
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11.3k
  if (!hasMips32r5() && 
hasVirt()9.50k
&&
!VirtWarningPrinted8
) {
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    errs() << "warning: the 'virt' ASE requires " << ArchName
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           << " revision 5 or greater\n";
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    VirtWarningPrinted = true;
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  }
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11.3k
  if (!hasMips32r6() && 
hasCRC()9.87k
&&
!CRCWarningPrinted8
) {
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    errs() << "warning: the 'crc' ASE requires " << ArchName
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           << " revision 6 or greater\n";
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    CRCWarningPrinted = true;
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  }
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11.3k
  if (!hasMips32r6() && 
hasGINV()9.87k
&&
!GINVWarningPrinted8
) {
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    errs() << "warning: the 'ginv' ASE requires " << ArchName
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2
           << " revision 6 or greater\n";
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    GINVWarningPrinted = true;
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  }
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11.3k
  CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering()));
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  Legalizer.reset(new MipsLegalizerInfo(*this));
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11.3k
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11.3k
  auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
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  RegBankInfo.reset(RBI);
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  InstSelector.reset(createMipsInstructionSelector(
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11.3k
      *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI));
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}
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8.43k
bool MipsSubtarget::isPositionIndependent() const {
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8.43k
  return TM.isPositionIndependent();
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8.43k
}
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/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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bool MipsSubtarget::enablePostRAScheduler() const { return true; }
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void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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12.3k
  CriticalPathRCs.clear();
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12.3k
  CriticalPathRCs.push_back(isGP64bit() ? 
&Mips::GPR64RegClass4.51k
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12.3k
                                        : 
&Mips::GPR32RegClass7.85k
);
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}
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12.3k
CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
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12.3k
  return CodeGenOpt::Aggressive;
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}
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MipsSubtarget &
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MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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11.3k
                                               const TargetMachine &TM) {
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  std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
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11.3k
  // Parse features string.
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  ParseSubtargetFeatures(CPUName, FS);
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  // Initialize scheduling itinerary for the specified CPU.
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11.3k
  InstrItins = getInstrItineraryForCPU(CPUName);
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11.3k
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11.3k
  if (InMips16Mode && 
!IsSoftFloat2.91k
)
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2.73k
    InMips16HardFloat = true;
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11.3k
250
11.3k
  if (StackAlignOverride)
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8
    stackAlignment = StackAlignOverride;
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11.3k
  else if (isABI_N32() || 
isABI_N64()10.8k
)
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3.75k
    stackAlignment = 16;
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7.58k
  else {
255
7.58k
    assert(isABI_O32() && "Unknown ABI for stack alignment!");
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7.58k
    stackAlignment = 8;
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7.58k
  }
258
11.3k
259
11.3k
  return *this;
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11.3k
}
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262
760
bool MipsSubtarget::useConstantIslands() {
263
760
  LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands
264
760
                    << "\n");
265
760
  return Mips16ConstantIslands;
266
760
}
267
268
10
Reloc::Model MipsSubtarget::getRelocationModel() const {
269
10
  return TM.getRelocationModel();
270
10
}
271
272
212k
bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
273
139k
bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
274
72.6k
bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
275
618k
const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
276
277
460
const CallLowering *MipsSubtarget::getCallLowering() const {
278
460
  return CallLoweringInfo.get();
279
460
}
280
281
704
const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const {
282
704
  return Legalizer.get();
283
704
}
284
285
766
const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
286
766
  return RegBankInfo.get();
287
766
}
288
289
542
const InstructionSelector *MipsSubtarget::getInstructionSelector() const {
290
542
  return InstSelector.get();
291
542
}