Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
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//===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the NVPTX target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
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#include "NVPTX.h"
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#include "NVPTXISelLowering.h"
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#include "NVPTXRegisterInfo.h"
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#include "NVPTXTargetMachine.h"
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#include "MCTargetDesc/NVPTXBaseInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Compiler.h"
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namespace llvm {
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class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
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  const NVPTXTargetMachine &TM;
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  // If true, generate mul.wide from sext and mul
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  bool doMulWide;
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  int getDivF32Level() const;
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  bool usePrecSqrtF32() const;
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  bool useF32FTZ() const;
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  bool allowFMA() const;
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  bool allowUnsafeFPMath() const;
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  bool useShortPointers() const;
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public:
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  explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
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                             CodeGenOpt::Level   OptLevel);
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  // Pass Name
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  StringRef getPassName() const override {
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    return "NVPTX DAG->DAG Pattern Instruction Selection";
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  }
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  bool runOnMachineFunction(MachineFunction &MF) override;
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  const NVPTXSubtarget *Subtarget;
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  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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                                    unsigned ConstraintID,
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                                    std::vector<SDValue> &OutOps) override;
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private:
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// Include the pieces autogenerated from the target description.
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#include "NVPTXGenDAGISel.inc"
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  void Select(SDNode *N) override;
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  bool tryIntrinsicNoChain(SDNode *N);
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  bool tryIntrinsicChain(SDNode *N);
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  void SelectTexSurfHandle(SDNode *N);
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  bool tryLoad(SDNode *N);
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  bool tryLoadVector(SDNode *N);
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  bool tryLDGLDU(SDNode *N);
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  bool tryStore(SDNode *N);
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  bool tryStoreVector(SDNode *N);
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  bool tryLoadParam(SDNode *N);
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  bool tryStoreRetval(SDNode *N);
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  bool tryStoreParam(SDNode *N);
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  void SelectAddrSpaceCast(SDNode *N);
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  bool tryTextureIntrinsic(SDNode *N);
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  bool trySurfaceIntrinsic(SDNode *N);
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  bool tryBFE(SDNode *N);
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  bool tryConstantFP16(SDNode *N);
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  bool SelectSETP_F16X2(SDNode *N);
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  bool tryEXTRACT_VECTOR_ELEMENT(SDNode *N);
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  inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
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    return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
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  }
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  // Match direct address complex pattern.
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  bool SelectDirectAddr(SDValue N, SDValue &Address);
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  bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
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                        SDValue &Offset, MVT mvt);
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  bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
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                    SDValue &Offset);
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  bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
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                      SDValue &Offset);
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  bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
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                        SDValue &Offset, MVT mvt);
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  bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
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                    SDValue &Offset);
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  bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
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                      SDValue &Offset);
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  bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
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  static unsigned GetConvertOpcode(MVT DestTy, MVT SrcTy, bool IsSigned);
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};
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} // end namespace llvm
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#endif