Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the NVPTX implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "NVPTXInstrInfo.h"
14
#include "NVPTX.h"
15
#include "NVPTXTargetMachine.h"
16
#include "llvm/ADT/STLExtras.h"
17
#include "llvm/CodeGen/MachineFunction.h"
18
#include "llvm/CodeGen/MachineInstrBuilder.h"
19
#include "llvm/CodeGen/MachineRegisterInfo.h"
20
#include "llvm/IR/Function.h"
21
22
using namespace llvm;
23
24
#define GET_INSTRINFO_CTOR_DTOR
25
#include "NVPTXGenInstrInfo.inc"
26
27
// Pin the vtable to this file.
28
0
void NVPTXInstrInfo::anchor() {}
29
30
455
NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
31
32
void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
33
                                 MachineBasicBlock::iterator I,
34
                                 const DebugLoc &DL, unsigned DestReg,
35
42
                                 unsigned SrcReg, bool KillSrc) const {
36
42
  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
37
42
  const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38
42
  const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
39
42
40
42
  if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
41
0
    report_fatal_error("Copy one register into another with a different width");
42
42
43
42
  unsigned Op;
44
42
  if (DestRC == &NVPTX::Int1RegsRegClass) {
45
0
    Op = NVPTX::IMOV1rr;
46
42
  } else if (DestRC == &NVPTX::Int16RegsRegClass) {
47
0
    Op = NVPTX::IMOV16rr;
48
42
  } else if (DestRC == &NVPTX::Int32RegsRegClass) {
49
1
    Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
50
1
                                             : 
NVPTX::BITCONVERT_32_F2I0
);
51
41
  } else if (DestRC == &NVPTX::Int64RegsRegClass) {
52
26
    Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
53
26
                                             : 
NVPTX::BITCONVERT_64_F2I0
);
54
26
  } else 
if (15
DestRC == &NVPTX::Float16RegsRegClass15
) {
55
12
    Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr
56
12
                                               : 
NVPTX::BITCONVERT_16_I2F0
);
57
12
  } else 
if (3
DestRC == &NVPTX::Float16x2RegsRegClass3
) {
58
0
    Op = NVPTX::IMOV32rr;
59
3
  } else if (DestRC == &NVPTX::Float32RegsRegClass) {
60
3
    Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
61
3
                                               : 
NVPTX::BITCONVERT_32_I2F0
);
62
3
  } else 
if (0
DestRC == &NVPTX::Float64RegsRegClass0
) {
63
0
    Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
64
0
                                               : NVPTX::BITCONVERT_64_I2F);
65
0
  } else {
66
0
    llvm_unreachable("Bad register copy");
67
0
  }
68
42
  BuildMI(MBB, I, DL, get(Op), DestReg)
69
42
      .addReg(SrcReg, getKillRegState(KillSrc));
70
42
}
71
72
/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
73
/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
74
/// implemented for a target).  Upon success, this returns false and returns
75
/// with the following information in various cases:
76
///
77
/// 1. If this block ends with no branches (it just falls through to its succ)
78
///    just return false, leaving TBB/FBB null.
79
/// 2. If this block ends with only an unconditional branch, it sets TBB to be
80
///    the destination block.
81
/// 3. If this block ends with an conditional branch and it falls through to
82
///    an successor block, it sets TBB to be the branch destination block and a
83
///    list of operands that evaluate the condition. These
84
///    operands can be passed to other TargetInstrInfo methods to create new
85
///    branches.
86
/// 4. If this block ends with an conditional branch and an unconditional
87
///    block, it returns the 'true' destination in TBB, the 'false' destination
88
///    in FBB, and a list of operands that evaluate the condition. These
89
///    operands can be passed to other TargetInstrInfo methods to create new
90
///    branches.
91
///
92
/// Note that removeBranch and insertBranch must be implemented to support
93
/// cases where this method returns success.
94
///
95
bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
96
                                   MachineBasicBlock *&TBB,
97
                                   MachineBasicBlock *&FBB,
98
                                   SmallVectorImpl<MachineOperand> &Cond,
99
8.08k
                                   bool AllowModify) const {
100
8.08k
  // If the block has no terminators, it just falls into the block after it.
101
8.08k
  MachineBasicBlock::iterator I = MBB.end();
102
8.08k
  if (I == MBB.begin() || 
!isUnpredicatedTerminator(*--I)8.06k
)
103
694
    return false;
104
7.38k
105
7.38k
  // Get the last instruction in the block.
106
7.38k
  MachineInstr &LastInst = *I;
107
7.38k
108
7.38k
  // If there is only one terminator instruction, process it.
109
7.38k
  if (I == MBB.begin() || 
!isUnpredicatedTerminator(*--I)7.18k
) {
110
6.99k
    if (LastInst.getOpcode() == NVPTX::GOTO) {
111
229
      TBB = LastInst.getOperand(0).getMBB();
112
229
      return false;
113
6.76k
    } else if (LastInst.getOpcode() == NVPTX::CBranch) {
114
503
      // Block ends with fall-through condbranch.
115
503
      TBB = LastInst.getOperand(1).getMBB();
116
503
      Cond.push_back(LastInst.getOperand(0));
117
503
      return false;
118
503
    }
119
6.26k
    // Otherwise, don't know what this is.
120
6.26k
    return true;
121
6.26k
  }
122
393
123
393
  // Get the instruction before it if it's a terminator.
124
393
  MachineInstr &SecondLastInst = *I;
125
393
126
393
  // If there are three terminators, we don't know what sort of block this is.
127
393
  if (I != MBB.begin() && 
isUnpredicatedTerminator(*--I)380
)
128
0
    return true;
129
393
130
393
  // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
131
393
  if (SecondLastInst.getOpcode() == NVPTX::CBranch &&
132
393
      
LastInst.getOpcode() == NVPTX::GOTO306
) {
133
306
    TBB = SecondLastInst.getOperand(1).getMBB();
134
306
    Cond.push_back(SecondLastInst.getOperand(0));
135
306
    FBB = LastInst.getOperand(0).getMBB();
136
306
    return false;
137
306
  }
138
87
139
87
  // If the block ends with two NVPTX:GOTOs, handle it.  The second one is not
140
87
  // executed, so remove it.
141
87
  if (SecondLastInst.getOpcode() == NVPTX::GOTO &&
142
87
      
LastInst.getOpcode() == NVPTX::GOTO0
) {
143
0
    TBB = SecondLastInst.getOperand(0).getMBB();
144
0
    I = LastInst;
145
0
    if (AllowModify)
146
0
      I->eraseFromParent();
147
0
    return false;
148
0
  }
149
87
150
87
  // Otherwise, can't handle this.
151
87
  return true;
152
87
}
153
154
unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
155
61
                                      int *BytesRemoved) const {
156
61
  assert(!BytesRemoved && "code size not handled");
157
61
  MachineBasicBlock::iterator I = MBB.end();
158
61
  if (I == MBB.begin())
159
0
    return 0;
160
61
  --I;
161
61
  if (I->getOpcode() != NVPTX::GOTO && 
I->getOpcode() != NVPTX::CBranch0
)
162
0
    return 0;
163
61
164
61
  // Remove the branch.
165
61
  I->eraseFromParent();
166
61
167
61
  I = MBB.end();
168
61
169
61
  if (I == MBB.begin())
170
0
    return 1;
171
61
  --I;
172
61
  if (I->getOpcode() != NVPTX::CBranch)
173
14
    return 1;
174
47
175
47
  // Remove the branch.
176
47
  I->eraseFromParent();
177
47
  return 2;
178
47
}
179
180
unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
181
                                      MachineBasicBlock *TBB,
182
                                      MachineBasicBlock *FBB,
183
                                      ArrayRef<MachineOperand> Cond,
184
                                      const DebugLoc &DL,
185
71
                                      int *BytesAdded) const {
186
71
  assert(!BytesAdded && "code size not handled");
187
71
188
71
  // Shouldn't be a fall through.
189
71
  assert(TBB && "insertBranch must not be told to insert a fallthrough");
190
71
  assert((Cond.size() == 1 || Cond.size() == 0) &&
191
71
         "NVPTX branch conditions have two components!");
192
71
193
71
  // One-way branch.
194
71
  if (!FBB) {
195
70
    if (Cond.empty()) // Unconditional branch
196
25
      BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
197
45
    else // Conditional branch
198
45
      BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
199
45
          .addMBB(TBB);
200
70
    return 1;
201
70
  }
202
1
203
1
  // Two-way Conditional Branch.
204
1
  BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
205
1
  BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
206
1
  return 2;
207
1
}