Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
Line
Count
Source (jump to first uncovered line)
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//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "MCTargetDesc/PPCMCExpr.h"
10
#include "MCTargetDesc/PPCMCTargetDesc.h"
11
#include "PPCTargetStreamer.h"
12
#include "TargetInfo/PowerPCTargetInfo.h"
13
#include "llvm/ADT/STLExtras.h"
14
#include "llvm/ADT/StringSwitch.h"
15
#include "llvm/ADT/Twine.h"
16
#include "llvm/MC/MCContext.h"
17
#include "llvm/MC/MCExpr.h"
18
#include "llvm/MC/MCInst.h"
19
#include "llvm/MC/MCInstrInfo.h"
20
#include "llvm/MC/MCParser/MCAsmLexer.h"
21
#include "llvm/MC/MCParser/MCAsmParser.h"
22
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
24
#include "llvm/MC/MCStreamer.h"
25
#include "llvm/MC/MCSubtargetInfo.h"
26
#include "llvm/MC/MCSymbolELF.h"
27
#include "llvm/Support/SourceMgr.h"
28
#include "llvm/Support/TargetRegistry.h"
29
#include "llvm/Support/raw_ostream.h"
30
31
using namespace llvm;
32
33
DEFINE_PPC_REGCLASSES;
34
35
// Evaluate an expression containing condition register
36
// or condition register field symbols.  Returns positive
37
// value on success, or -1 on error.
38
static int64_t
39
2.51k
EvaluateCRExpr(const MCExpr *E) {
40
2.51k
  switch (E->getKind()) {
41
2.51k
  case MCExpr::Target:
42
366
    return -1;
43
2.51k
44
2.51k
  case MCExpr::Constant: {
45
95
    int64_t Res = cast<MCConstantExpr>(E)->getValue();
46
95
    return Res < 0 ? 
-10
: Res;
47
2.51k
  }
48
2.51k
49
2.51k
  case MCExpr::SymbolRef: {
50
1.87k
    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
51
1.87k
    StringRef Name = SRE->getSymbol().getName();
52
1.87k
53
1.87k
    if (Name == "lt") 
return 016
;
54
1.85k
    if (Name == "gt") 
return 116
;
55
1.84k
    if (Name == "eq") 
return 216
;
56
1.82k
    if (Name == "so") 
return 316
;
57
1.80k
    if (Name == "un") 
return 316
;
58
1.79k
59
1.79k
    if (Name == "cr0") 
return 012
;
60
1.78k
    if (Name == "cr1") 
return 112
;
61
1.76k
    if (Name == "cr2") 
return 212
;
62
1.75k
    if (Name == "cr3") 
return 312
;
63
1.74k
    if (Name == "cr4") 
return 412
;
64
1.73k
    if (Name == "cr5") 
return 512
;
65
1.72k
    if (Name == "cr6") 
return 612
;
66
1.70k
    if (Name == "cr7") 
return 712
;
67
1.69k
68
1.69k
    return -1;
69
1.69k
  }
70
1.69k
71
1.69k
  case MCExpr::Unary:
72
0
    return -1;
73
1.69k
74
1.69k
  case MCExpr::Binary: {
75
184
    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
76
184
    int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
77
184
    int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
78
184
    int64_t Res;
79
184
80
184
    if (LHSVal < 0 || 
RHSVal < 0160
)
81
24
      return -1;
82
160
83
160
    switch (BE->getOpcode()) {
84
160
    
default: return -10
;
85
160
    
case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break80
;
86
160
    
case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break80
;
87
160
    }
88
160
89
160
    return Res < 0 ? 
-10
: Res;
90
160
  }
91
0
  }
92
0
93
0
  llvm_unreachable("Invalid expression kind!");
94
0
}
95
96
namespace {
97
98
struct PPCOperand;
99
100
class PPCAsmParser : public MCTargetAsmParser {
101
  bool IsPPC64;
102
  bool IsDarwin;
103
104
0
  void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
105
106
26.8k
  bool isPPC64() const { return IsPPC64; }
107
31.6k
  bool isDarwin() const { return IsDarwin; }
108
109
  bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
110
111
  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
112
113
  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
114
                                        PPCMCExpr::VariantKind &Variant);
115
  const MCExpr *FixupVariantKind(const MCExpr *E);
116
  bool ParseExpression(const MCExpr *&EVal);
117
  bool ParseDarwinExpression(const MCExpr *&EVal);
118
119
  bool ParseOperand(OperandVector &Operands);
120
121
  bool ParseDirectiveWord(unsigned Size, AsmToken ID);
122
  bool ParseDirectiveTC(unsigned Size, AsmToken ID);
123
  bool ParseDirectiveMachine(SMLoc L);
124
  bool ParseDarwinDirectiveMachine(SMLoc L);
125
  bool ParseDirectiveAbiVersion(SMLoc L);
126
  bool ParseDirectiveLocalEntry(SMLoc L);
127
128
  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
129
                               OperandVector &Operands, MCStreamer &Out,
130
                               uint64_t &ErrorInfo,
131
                               bool MatchingInlineAsm) override;
132
133
  void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
134
135
  /// @name Auto-generated Match Functions
136
  /// {
137
138
#define GET_ASSEMBLER_HEADER
139
#include "PPCGenAsmMatcher.inc"
140
141
  /// }
142
143
144
public:
145
  PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
146
               const MCInstrInfo &MII, const MCTargetOptions &Options)
147
506
    : MCTargetAsmParser(Options, STI, MII) {
148
506
    // Check for 64-bit vs. 32-bit pointer mode.
149
506
    const Triple &TheTriple = STI.getTargetTriple();
150
506
    IsPPC64 = TheTriple.isPPC64();
151
506
    IsDarwin = TheTriple.isMacOSX();
152
506
    // Initialize the set of available features.
153
506
    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
154
506
  }
155
156
  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
157
                        SMLoc NameLoc, OperandVector &Operands) override;
158
159
  bool ParseDirective(AsmToken DirectiveID) override;
160
161
  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
162
                                      unsigned Kind) override;
163
164
  const MCExpr *applyModifierToExpr(const MCExpr *E,
165
                                    MCSymbolRefExpr::VariantKind,
166
                                    MCContext &Ctx) override;
167
};
168
169
/// PPCOperand - Instances of this class represent a parsed PowerPC machine
170
/// instruction.
171
struct PPCOperand : public MCParsedAsmOperand {
172
  enum KindTy {
173
    Token,
174
    Immediate,
175
    ContextImmediate,
176
    Expression,
177
    TLSRegister
178
  } Kind;
179
180
  SMLoc StartLoc, EndLoc;
181
  bool IsPPC64;
182
183
  struct TokOp {
184
    const char *Data;
185
    unsigned Length;
186
  };
187
188
  struct ImmOp {
189
    int64_t Val;
190
  };
191
192
  struct ExprOp {
193
    const MCExpr *Val;
194
    int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
195
  };
196
197
  struct TLSRegOp {
198
    const MCSymbolRefExpr *Sym;
199
  };
200
201
  union {
202
    struct TokOp Tok;
203
    struct ImmOp Imm;
204
    struct ExprOp Expr;
205
    struct TLSRegOp TLSReg;
206
  };
207
208
25.0k
  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
209
public:
210
0
  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
211
0
    Kind = o.Kind;
212
0
    StartLoc = o.StartLoc;
213
0
    EndLoc = o.EndLoc;
214
0
    IsPPC64 = o.IsPPC64;
215
0
    switch (Kind) {
216
0
    case Token:
217
0
      Tok = o.Tok;
218
0
      break;
219
0
    case Immediate:
220
0
    case ContextImmediate:
221
0
      Imm = o.Imm;
222
0
      break;
223
0
    case Expression:
224
0
      Expr = o.Expr;
225
0
      break;
226
0
    case TLSRegister:
227
0
      TLSReg = o.TLSReg;
228
0
      break;
229
0
    }
230
0
  }
231
232
  // Disable use of sized deallocation due to overallocation of PPCOperand
233
  // objects in CreateTokenWithStringCopy.
234
25.0k
  void operator delete(void *p) { ::operator delete(p); }
235
236
  /// getStartLoc - Get the location of the first token of this operand.
237
32
  SMLoc getStartLoc() const override { return StartLoc; }
238
239
  /// getEndLoc - Get the location of the last token of this operand.
240
0
  SMLoc getEndLoc() const override { return EndLoc; }
241
242
  /// getLocRange - Get the range between the first and last token of this
243
  /// operand.
244
4
  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
245
246
  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
247
1.53k
  bool isPPC64() const { return IsPPC64; }
248
249
17.3k
  int64_t getImm() const {
250
17.3k
    assert(Kind == Immediate && "Invalid access!");
251
17.3k
    return Imm.Val;
252
17.3k
  }
253
471
  int64_t getImmS16Context() const {
254
471
    assert((Kind == Immediate || Kind == ContextImmediate) &&
255
471
           "Invalid access!");
256
471
    if (Kind == Immediate)
257
449
      return Imm.Val;
258
22
    return static_cast<int16_t>(Imm.Val);
259
22
  }
260
57
  int64_t getImmU16Context() const {
261
57
    assert((Kind == Immediate || Kind == ContextImmediate) &&
262
57
           "Invalid access!");
263
57
    return Imm.Val;
264
57
  }
265
266
2.05k
  const MCExpr *getExpr() const {
267
2.05k
    assert(Kind == Expression && "Invalid access!");
268
2.05k
    return Expr.Val;
269
2.05k
  }
270
271
96
  int64_t getExprCRVal() const {
272
96
    assert(Kind == Expression && "Invalid access!");
273
96
    return Expr.CRVal;
274
96
  }
275
276
40
  const MCExpr *getTLSReg() const {
277
40
    assert(Kind == TLSRegister && "Invalid access!");
278
40
    return TLSReg.Sym;
279
40
  }
280
281
10.6k
  unsigned getReg() const override {
282
10.6k
    assert(isRegNumber() && "Invalid access!");
283
10.6k
    return (unsigned) Imm.Val;
284
10.6k
  }
285
286
1.08k
  unsigned getVSReg() const {
287
1.08k
    assert(isVSRegNumber() && "Invalid access!");
288
1.08k
    return (unsigned) Imm.Val;
289
1.08k
  }
290
291
773
  unsigned getCCReg() const {
292
773
    assert(isCCRegNumber() && "Invalid access!");
293
773
    return (unsigned) (Kind == Immediate ? 
Imm.Val757
:
Expr.CRVal16
);
294
773
  }
295
296
383
  unsigned getCRBit() const {
297
383
    assert(isCRBitNumber() && "Invalid access!");
298
383
    return (unsigned) (Kind == Immediate ? 
Imm.Val303
:
Expr.CRVal80
);
299
383
  }
300
301
4
  unsigned getCRBitMask() const {
302
4
    assert(isCRBitMask() && "Invalid access!");
303
4
    return 7 - countTrailingZeros<uint64_t>(Imm.Val);
304
4
  }
305
306
18.7k
  bool isToken() const override { return Kind == Token; }
307
534
  bool isImm() const override {
308
534
    return Kind == Immediate || 
Kind == Expression44
;
309
534
  }
310
46
  bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
311
16
  bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
312
2
  bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
313
36
  bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
314
299
  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
315
10
  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
316
128
  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
317
14
  bool isU6ImmX2() const { return Kind == Immediate &&
318
14
                                  isUInt<6>(getImm()) &&
319
14
                                  (getImm() & 1) == 0; }
320
16
  bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
321
54
  bool isU7ImmX4() const { return Kind == Immediate &&
322
54
                                  isUInt<7>(getImm()) &&
323
54
                                  (getImm() & 3) == 0; }
324
2
  bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
325
36
  bool isU8ImmX8() const { return Kind == Immediate &&
326
36
                                  isUInt<8>(getImm()) &&
327
36
                                  (getImm() & 7) == 0; }
328
329
2
  bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
330
1
  bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
331
112
  bool isU16Imm() const {
332
112
    switch (Kind) {
333
112
      case Expression:
334
59
        return true;
335
112
      case Immediate:
336
53
      case ContextImmediate:
337
53
        return isUInt<16>(getImmU16Context());
338
53
      default:
339
0
        return false;
340
112
    }
341
112
  }
342
803
  bool isS16Imm() const {
343
803
    switch (Kind) {
344
803
      case Expression:
345
371
        return true;
346
803
      case Immediate:
347
432
      case ContextImmediate:
348
432
        return isInt<16>(getImmS16Context());
349
432
      default:
350
0
        return false;
351
803
    }
352
803
  }
353
494
  bool isS16ImmX4() const { return Kind == Expression ||
354
494
                                   
(336
Kind == Immediate336
&&
isInt<16>(getImm())336
&&
355
336
                                    
(getImm() & 3) == 0332
); }
356
18
  bool isS16ImmX16() const { return Kind == Expression ||
357
18
                                    
(8
Kind == Immediate8
&&
isInt<16>(getImm())8
&&
358
8
                                     (getImm() & 15) == 0); }
359
452
  bool isS17Imm() const {
360
452
    switch (Kind) {
361
452
      case Expression:
362
424
        return true;
363
452
      case Immediate:
364
28
      case ContextImmediate:
365
28
        return isInt<17>(getImmS16Context());
366
28
      default:
367
0
        return false;
368
452
    }
369
452
  }
370
118
  bool isTLSReg() const { return Kind == TLSRegister; }
371
262
  bool isDirectBr() const {
372
262
    if (Kind == Expression)
373
257
      return true;
374
5
    if (Kind != Immediate)
375
0
      return false;
376
5
    // Operand must be 64-bit aligned, signed 27-bit immediate.
377
5
    if ((getImm() & 3) != 0)
378
0
      return false;
379
5
    if (isInt<26>(getImm()))
380
4
      return true;
381
1
    if (!IsPPC64) {
382
1
      // In 32-bit mode, large 32-bit quantities wrap around.
383
1
      if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
384
1
        return true;
385
0
    }
386
0
    return false;
387
0
  }
388
1.08k
  bool isCondBr() const { return Kind == Expression ||
389
1.08k
                                 
(311
Kind == Immediate311
&&
isInt<16>(getImm())311
&&
390
311
                                  (getImm() & 3) == 0); }
391
11.5k
  bool isRegNumber() const { return Kind == Immediate && 
isUInt<5>(getImm())11.1k
; }
392
1.09k
  bool isVSRegNumber() const {
393
1.09k
    return Kind == Immediate && 
isUInt<6>(getImm())1.08k
;
394
1.09k
  }
395
791
  bool isCCRegNumber() const { return (Kind == Expression
396
791
                                       && 
isUInt<3>(getExprCRVal())16
) ||
397
791
                                      
(775
Kind == Immediate775
398
775
                                       && 
isUInt<3>(getImm())769
); }
399
379
  bool isCRBitNumber() const { return (Kind == Expression
400
379
                                       && 
isUInt<5>(getExprCRVal())80
) ||
401
379
                                      
(299
Kind == Immediate299
402
299
                                       && isUInt<5>(getImm())); }
403
4
  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
404
4
                                    isPowerOf2_32(getImm()); }
405
0
  bool isATBitsAsHint() const { return false; }
406
0
  bool isMem() const override { return false; }
407
1.15k
  bool isReg() const override { return false; }
408
409
0
  void addRegOperands(MCInst &Inst, unsigned N) const {
410
0
    llvm_unreachable("addRegOperands");
411
0
  }
412
413
3.24k
  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
414
3.24k
    assert(N == 1 && "Invalid number of operands!");
415
3.24k
    Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
416
3.24k
  }
417
418
814
  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
419
814
    assert(N == 1 && "Invalid number of operands!");
420
814
    Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
421
814
  }
422
423
1.75k
  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
424
1.75k
    assert(N == 1 && "Invalid number of operands!");
425
1.75k
    Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
426
1.75k
  }
427
428
1.10k
  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
429
1.10k
    assert(N == 1 && "Invalid number of operands!");
430
1.10k
    Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
431
1.10k
  }
432
433
375
  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
434
375
    if (isPPC64())
435
352
      addRegG8RCOperands(Inst, N);
436
23
    else
437
23
      addRegGPRCOperands(Inst, N);
438
375
  }
439
440
1.15k
  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
441
1.15k
    if (isPPC64())
442
1.10k
      addRegG8RCNoX0Operands(Inst, N);
443
55
    else
444
55
      addRegGPRCNoR0Operands(Inst, N);
445
1.15k
  }
446
447
259
  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
448
259
    assert(N == 1 && "Invalid number of operands!");
449
259
    Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
450
259
  }
451
452
311
  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
453
311
    assert(N == 1 && "Invalid number of operands!");
454
311
    Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
455
311
  }
456
457
26
  void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
458
26
    assert(N == 1 && "Invalid number of operands!");
459
26
    Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
460
26
  }
461
462
1.81k
  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
463
1.81k
    assert(N == 1 && "Invalid number of operands!");
464
1.81k
    Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
465
1.81k
  }
466
467
700
  void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
468
700
    assert(N == 1 && "Invalid number of operands!");
469
700
    Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
470
700
  }
471
472
284
  void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
473
284
    assert(N == 1 && "Invalid number of operands!");
474
284
    Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
475
284
  }
476
477
96
  void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
478
96
    assert(N == 1 && "Invalid number of operands!");
479
96
    Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
480
96
  }
481
482
180
  void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
483
180
    assert(N == 1 && "Invalid number of operands!");
484
180
    Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
485
180
  }
486
487
28
  void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
488
28
    assert(N == 1 && "Invalid number of operands!");
489
28
    Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
490
28
  }
491
492
40
  void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
493
40
    assert(N == 1 && "Invalid number of operands!");
494
40
    Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
495
40
  }
496
497
85
  void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
498
85
    assert(N == 1 && "Invalid number of operands!");
499
85
    Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
500
85
  }
501
502
985
  void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
503
985
    assert(N == 1 && "Invalid number of operands!");
504
985
    Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
505
985
  }
506
507
383
  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
508
383
    assert(N == 1 && "Invalid number of operands!");
509
383
    Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
510
383
  }
511
512
773
  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
513
773
    assert(N == 1 && "Invalid number of operands!");
514
773
    Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
515
773
  }
516
517
4
  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
518
4
    assert(N == 1 && "Invalid number of operands!");
519
4
    Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
520
4
  }
521
522
1.30k
  void addImmOperands(MCInst &Inst, unsigned N) const {
523
1.30k
    assert(N == 1 && "Invalid number of operands!");
524
1.30k
    if (Kind == Immediate)
525
1.10k
      Inst.addOperand(MCOperand::createImm(getImm()));
526
206
    else
527
206
      Inst.addOperand(MCOperand::createExpr(getExpr()));
528
1.30k
  }
529
530
1.23k
  void addS16ImmOperands(MCInst &Inst, unsigned N) const {
531
1.23k
    assert(N == 1 && "Invalid number of operands!");
532
1.23k
    switch (Kind) {
533
1.23k
      case Immediate:
534
429
        Inst.addOperand(MCOperand::createImm(getImm()));
535
429
        break;
536
1.23k
      case ContextImmediate:
537
11
        Inst.addOperand(MCOperand::createImm(getImmS16Context()));
538
11
        break;
539
1.23k
      default:
540
795
        Inst.addOperand(MCOperand::createExpr(getExpr()));
541
795
        break;
542
1.23k
    }
543
1.23k
  }
544
545
104
  void addU16ImmOperands(MCInst &Inst, unsigned N) const {
546
104
    assert(N == 1 && "Invalid number of operands!");
547
104
    switch (Kind) {
548
104
      case Immediate:
549
41
        Inst.addOperand(MCOperand::createImm(getImm()));
550
41
        break;
551
104
      case ContextImmediate:
552
4
        Inst.addOperand(MCOperand::createImm(getImmU16Context()));
553
4
        break;
554
104
      default:
555
59
        Inst.addOperand(MCOperand::createExpr(getExpr()));
556
59
        break;
557
104
    }
558
104
  }
559
560
1.00k
  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
561
1.00k
    assert(N == 1 && "Invalid number of operands!");
562
1.00k
    if (Kind == Immediate)
563
9
      Inst.addOperand(MCOperand::createImm(getImm() / 4));
564
993
    else
565
993
      Inst.addOperand(MCOperand::createExpr(getExpr()));
566
1.00k
  }
567
568
40
  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
569
40
    assert(N == 1 && "Invalid number of operands!");
570
40
    Inst.addOperand(MCOperand::createExpr(getTLSReg()));
571
40
  }
572
573
8.25k
  StringRef getToken() const {
574
8.25k
    assert(Kind == Token && "Invalid access!");
575
8.25k
    return StringRef(Tok.Data, Tok.Length);
576
8.25k
  }
577
578
  void print(raw_ostream &OS) const override;
579
580
  static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
581
7.32k
                                                 bool IsPPC64) {
582
7.32k
    auto Op = make_unique<PPCOperand>(Token);
583
7.32k
    Op->Tok.Data = Str.data();
584
7.32k
    Op->Tok.Length = Str.size();
585
7.32k
    Op->StartLoc = S;
586
7.32k
    Op->EndLoc = S;
587
7.32k
    Op->IsPPC64 = IsPPC64;
588
7.32k
    return Op;
589
7.32k
  }
590
591
  static std::unique_ptr<PPCOperand>
592
922
  CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
593
922
    // Allocate extra memory for the string and copy it.
594
922
    // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
595
922
    // deleter which will destroy them by simply using "delete", not correctly
596
922
    // calling operator delete on this extra memory after calling the dtor
597
922
    // explicitly.
598
922
    void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
599
922
    std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
600
922
    Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
601
922
    Op->Tok.Length = Str.size();
602
922
    std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
603
922
    Op->StartLoc = S;
604
922
    Op->EndLoc = S;
605
922
    Op->IsPPC64 = IsPPC64;
606
922
    return Op;
607
922
  }
608
609
  static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
610
14.5k
                                               bool IsPPC64) {
611
14.5k
    auto Op = make_unique<PPCOperand>(Immediate);
612
14.5k
    Op->Imm.Val = Val;
613
14.5k
    Op->StartLoc = S;
614
14.5k
    Op->EndLoc = E;
615
14.5k
    Op->IsPPC64 = IsPPC64;
616
14.5k
    return Op;
617
14.5k
  }
618
619
  static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
620
2.14k
                                                SMLoc E, bool IsPPC64) {
621
2.14k
    auto Op = make_unique<PPCOperand>(Expression);
622
2.14k
    Op->Expr.Val = Val;
623
2.14k
    Op->Expr.CRVal = EvaluateCRExpr(Val);
624
2.14k
    Op->StartLoc = S;
625
2.14k
    Op->EndLoc = E;
626
2.14k
    Op->IsPPC64 = IsPPC64;
627
2.14k
    return Op;
628
2.14k
  }
629
630
  static std::unique_ptr<PPCOperand>
631
44
  CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
632
44
    auto Op = make_unique<PPCOperand>(TLSRegister);
633
44
    Op->TLSReg.Sym = Sym;
634
44
    Op->StartLoc = S;
635
44
    Op->EndLoc = E;
636
44
    Op->IsPPC64 = IsPPC64;
637
44
    return Op;
638
44
  }
639
640
  static std::unique_ptr<PPCOperand>
641
15
  CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
642
15
    auto Op = make_unique<PPCOperand>(ContextImmediate);
643
15
    Op->Imm.Val = Val;
644
15
    Op->StartLoc = S;
645
15
    Op->EndLoc = E;
646
15
    Op->IsPPC64 = IsPPC64;
647
15
    return Op;
648
15
  }
649
650
  static std::unique_ptr<PPCOperand>
651
14.3k
  CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
652
14.3k
    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
653
12.1k
      return CreateImm(CE->getValue(), S, E, IsPPC64);
654
2.20k
655
2.20k
    if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
656
1.72k
      if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
657
44
        return CreateTLSReg(SRE, S, E, IsPPC64);
658
2.16k
659
2.16k
    if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
660
381
      int64_t Res;
661
381
      if (TE->evaluateAsConstant(Res))
662
15
        return CreateContextImm(Res, S, E, IsPPC64);
663
2.14k
    }
664
2.14k
665
2.14k
    return CreateExpr(Val, S, E, IsPPC64);
666
2.14k
  }
667
};
668
669
} // end anonymous namespace.
670
671
void PPCOperand::print(raw_ostream &OS) const {
672
  switch (Kind) {
673
  case Token:
674
    OS << "'" << getToken() << "'";
675
    break;
676
  case Immediate:
677
  case ContextImmediate:
678
    OS << getImm();
679
    break;
680
  case Expression:
681
    OS << *getExpr();
682
    break;
683
  case TLSRegister:
684
    OS << *getTLSReg();
685
    break;
686
  }
687
}
688
689
static void
690
34
addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
691
34
  if (Op.isImm()) {
692
28
    Inst.addOperand(MCOperand::createImm(-Op.getImm()));
693
28
    return;
694
28
  }
695
6
  const MCExpr *Expr = Op.getExpr();
696
6
  if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
697
0
    if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
698
0
      Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
699
0
      return;
700
0
    }
701
6
  } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
702
0
    if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
703
0
      const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
704
0
                                                 BinExpr->getLHS(), Ctx);
705
0
      Inst.addOperand(MCOperand::createExpr(NE));
706
0
      return;
707
0
    }
708
6
  }
709
6
  Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
710
6
}
711
712
void PPCAsmParser::ProcessInstruction(MCInst &Inst,
713
7.78k
                                      const OperandVector &Operands) {
714
7.78k
  int Opcode = Inst.getOpcode();
715
7.78k
  switch (Opcode) {
716
7.78k
  case PPC::DCBTx:
717
9
  case PPC::DCBTT:
718
9
  case PPC::DCBTSTx:
719
9
  case PPC::DCBTSTT: {
720
9
    MCInst TmpInst;
721
9
    TmpInst.setOpcode((Opcode == PPC::DCBTx || 
Opcode == PPC::DCBTT6
) ?
722
5
                      PPC::DCBT : 
PPC::DCBTST4
);
723
9
    TmpInst.addOperand(MCOperand::createImm(
724
9
      (Opcode == PPC::DCBTx || 
Opcode == PPC::DCBTSTx6
) ?
05
:
164
));
725
9
    TmpInst.addOperand(Inst.getOperand(0));
726
9
    TmpInst.addOperand(Inst.getOperand(1));
727
9
    Inst = TmpInst;
728
9
    break;
729
9
  }
730
9
  case PPC::DCBTCT:
731
4
  case PPC::DCBTDS: {
732
4
    MCInst TmpInst;
733
4
    TmpInst.setOpcode(PPC::DCBT);
734
4
    TmpInst.addOperand(Inst.getOperand(2));
735
4
    TmpInst.addOperand(Inst.getOperand(0));
736
4
    TmpInst.addOperand(Inst.getOperand(1));
737
4
    Inst = TmpInst;
738
4
    break;
739
4
  }
740
4
  case PPC::DCBTSTCT:
741
4
  case PPC::DCBTSTDS: {
742
4
    MCInst TmpInst;
743
4
    TmpInst.setOpcode(PPC::DCBTST);
744
4
    TmpInst.addOperand(Inst.getOperand(2));
745
4
    TmpInst.addOperand(Inst.getOperand(0));
746
4
    TmpInst.addOperand(Inst.getOperand(1));
747
4
    Inst = TmpInst;
748
4
    break;
749
4
  }
750
6
  case PPC::DCBFx:
751
6
  case PPC::DCBFL:
752
6
  case PPC::DCBFLP: {
753
6
    int L = 0;
754
6
    if (Opcode == PPC::DCBFL)
755
2
      L = 1;
756
4
    else if (Opcode == PPC::DCBFLP)
757
2
      L = 3;
758
6
759
6
    MCInst TmpInst;
760
6
    TmpInst.setOpcode(PPC::DCBF);
761
6
    TmpInst.addOperand(MCOperand::createImm(L));
762
6
    TmpInst.addOperand(Inst.getOperand(0));
763
6
    TmpInst.addOperand(Inst.getOperand(1));
764
6
    Inst = TmpInst;
765
6
    break;
766
6
  }
767
7
  case PPC::LAx: {
768
7
    MCInst TmpInst;
769
7
    TmpInst.setOpcode(PPC::LA);
770
7
    TmpInst.addOperand(Inst.getOperand(0));
771
7
    TmpInst.addOperand(Inst.getOperand(2));
772
7
    TmpInst.addOperand(Inst.getOperand(1));
773
7
    Inst = TmpInst;
774
7
    break;
775
6
  }
776
24
  case PPC::SUBI: {
777
24
    MCInst TmpInst;
778
24
    TmpInst.setOpcode(PPC::ADDI);
779
24
    TmpInst.addOperand(Inst.getOperand(0));
780
24
    TmpInst.addOperand(Inst.getOperand(1));
781
24
    addNegOperand(TmpInst, Inst.getOperand(2), getContext());
782
24
    Inst = TmpInst;
783
24
    break;
784
6
  }
785
6
  case PPC::SUBIS: {
786
6
    MCInst TmpInst;
787
6
    TmpInst.setOpcode(PPC::ADDIS);
788
6
    TmpInst.addOperand(Inst.getOperand(0));
789
6
    TmpInst.addOperand(Inst.getOperand(1));
790
6
    addNegOperand(TmpInst, Inst.getOperand(2), getContext());
791
6
    Inst = TmpInst;
792
6
    break;
793
6
  }
794
6
  case PPC::SUBIC: {
795
2
    MCInst TmpInst;
796
2
    TmpInst.setOpcode(PPC::ADDIC);
797
2
    TmpInst.addOperand(Inst.getOperand(0));
798
2
    TmpInst.addOperand(Inst.getOperand(1));
799
2
    addNegOperand(TmpInst, Inst.getOperand(2), getContext());
800
2
    Inst = TmpInst;
801
2
    break;
802
6
  }
803
6
  case PPC::SUBICo: {
804
2
    MCInst TmpInst;
805
2
    TmpInst.setOpcode(PPC::ADDICo);
806
2
    TmpInst.addOperand(Inst.getOperand(0));
807
2
    TmpInst.addOperand(Inst.getOperand(1));
808
2
    addNegOperand(TmpInst, Inst.getOperand(2), getContext());
809
2
    Inst = TmpInst;
810
2
    break;
811
6
  }
812
6
  case PPC::EXTLWI:
813
4
  case PPC::EXTLWIo: {
814
4
    MCInst TmpInst;
815
4
    int64_t N = Inst.getOperand(2).getImm();
816
4
    int64_t B = Inst.getOperand(3).getImm();
817
4
    TmpInst.setOpcode(Opcode == PPC::EXTLWI? 
PPC::RLWINM2
:
PPC::RLWINMo2
);
818
4
    TmpInst.addOperand(Inst.getOperand(0));
819
4
    TmpInst.addOperand(Inst.getOperand(1));
820
4
    TmpInst.addOperand(MCOperand::createImm(B));
821
4
    TmpInst.addOperand(MCOperand::createImm(0));
822
4
    TmpInst.addOperand(MCOperand::createImm(N - 1));
823
4
    Inst = TmpInst;
824
4
    break;
825
4
  }
826
4
  case PPC::EXTRWI:
827
4
  case PPC::EXTRWIo: {
828
4
    MCInst TmpInst;
829
4
    int64_t N = Inst.getOperand(2).getImm();
830
4
    int64_t B = Inst.getOperand(3).getImm();
831
4
    TmpInst.setOpcode(Opcode == PPC::EXTRWI? 
PPC::RLWINM2
:
PPC::RLWINMo2
);
832
4
    TmpInst.addOperand(Inst.getOperand(0));
833
4
    TmpInst.addOperand(Inst.getOperand(1));
834
4
    TmpInst.addOperand(MCOperand::createImm(B + N));
835
4
    TmpInst.addOperand(MCOperand::createImm(32 - N));
836
4
    TmpInst.addOperand(MCOperand::createImm(31));
837
4
    Inst = TmpInst;
838
4
    break;
839
4
  }
840
4
  case PPC::INSLWI:
841
4
  case PPC::INSLWIo: {
842
4
    MCInst TmpInst;
843
4
    int64_t N = Inst.getOperand(2).getImm();
844
4
    int64_t B = Inst.getOperand(3).getImm();
845
4
    TmpInst.setOpcode(Opcode == PPC::INSLWI? 
PPC::RLWIMI2
:
PPC::RLWIMIo2
);
846
4
    TmpInst.addOperand(Inst.getOperand(0));
847
4
    TmpInst.addOperand(Inst.getOperand(0));
848
4
    TmpInst.addOperand(Inst.getOperand(1));
849
4
    TmpInst.addOperand(MCOperand::createImm(32 - B));
850
4
    TmpInst.addOperand(MCOperand::createImm(B));
851
4
    TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
852
4
    Inst = TmpInst;
853
4
    break;
854
4
  }
855
4
  case PPC::INSRWI:
856
4
  case PPC::INSRWIo: {
857
4
    MCInst TmpInst;
858
4
    int64_t N = Inst.getOperand(2).getImm();
859
4
    int64_t B = Inst.getOperand(3).getImm();
860
4
    TmpInst.setOpcode(Opcode == PPC::INSRWI? 
PPC::RLWIMI2
:
PPC::RLWIMIo2
);
861
4
    TmpInst.addOperand(Inst.getOperand(0));
862
4
    TmpInst.addOperand(Inst.getOperand(0));
863
4
    TmpInst.addOperand(Inst.getOperand(1));
864
4
    TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
865
4
    TmpInst.addOperand(MCOperand::createImm(B));
866
4
    TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
867
4
    Inst = TmpInst;
868
4
    break;
869
4
  }
870
4
  case PPC::ROTRWI:
871
4
  case PPC::ROTRWIo: {
872
4
    MCInst TmpInst;
873
4
    int64_t N = Inst.getOperand(2).getImm();
874
4
    TmpInst.setOpcode(Opcode == PPC::ROTRWI? 
PPC::RLWINM2
:
PPC::RLWINMo2
);
875
4
    TmpInst.addOperand(Inst.getOperand(0));
876
4
    TmpInst.addOperand(Inst.getOperand(1));
877
4
    TmpInst.addOperand(MCOperand::createImm(32 - N));
878
4
    TmpInst.addOperand(MCOperand::createImm(0));
879
4
    TmpInst.addOperand(MCOperand::createImm(31));
880
4
    Inst = TmpInst;
881
4
    break;
882
4
  }
883
5
  case PPC::SLWI:
884
5
  case PPC::SLWIo: {
885
5
    MCInst TmpInst;
886
5
    int64_t N = Inst.getOperand(2).getImm();
887
5
    TmpInst.setOpcode(Opcode == PPC::SLWI? 
PPC::RLWINM3
:
PPC::RLWINMo2
);
888
5
    TmpInst.addOperand(Inst.getOperand(0));
889
5
    TmpInst.addOperand(Inst.getOperand(1));
890
5
    TmpInst.addOperand(MCOperand::createImm(N));
891
5
    TmpInst.addOperand(MCOperand::createImm(0));
892
5
    TmpInst.addOperand(MCOperand::createImm(31 - N));
893
5
    Inst = TmpInst;
894
5
    break;
895
5
  }
896
5
  case PPC::SRWI:
897
4
  case PPC::SRWIo: {
898
4
    MCInst TmpInst;
899
4
    int64_t N = Inst.getOperand(2).getImm();
900
4
    TmpInst.setOpcode(Opcode == PPC::SRWI? 
PPC::RLWINM2
:
PPC::RLWINMo2
);
901
4
    TmpInst.addOperand(Inst.getOperand(0));
902
4
    TmpInst.addOperand(Inst.getOperand(1));
903
4
    TmpInst.addOperand(MCOperand::createImm(32 - N));
904
4
    TmpInst.addOperand(MCOperand::createImm(N));
905
4
    TmpInst.addOperand(MCOperand::createImm(31));
906
4
    Inst = TmpInst;
907
4
    break;
908
4
  }
909
4
  case PPC::CLRRWI:
910
4
  case PPC::CLRRWIo: {
911
4
    MCInst TmpInst;
912
4
    int64_t N = Inst.getOperand(2).getImm();
913
4
    TmpInst.setOpcode(Opcode == PPC::CLRRWI? 
PPC::RLWINM2
:
PPC::RLWINMo2
);
914
4
    TmpInst.addOperand(Inst.getOperand(0));
915
4
    TmpInst.addOperand(Inst.getOperand(1));
916
4
    TmpInst.addOperand(MCOperand::createImm(0));
917
4
    TmpInst.addOperand(MCOperand::createImm(0));
918
4
    TmpInst.addOperand(MCOperand::createImm(31 - N));
919
4
    Inst = TmpInst;
920
4
    break;
921
4
  }
922
4
  case PPC::CLRLSLWI:
923
4
  case PPC::CLRLSLWIo: {
924
4
    MCInst TmpInst;
925
4
    int64_t B = Inst.getOperand(2).getImm();
926
4
    int64_t N = Inst.getOperand(3).getImm();
927
4
    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? 
PPC::RLWINM2
:
PPC::RLWINMo2
);
928
4
    TmpInst.addOperand(Inst.getOperand(0));
929
4
    TmpInst.addOperand(Inst.getOperand(1));
930
4
    TmpInst.addOperand(MCOperand::createImm(N));
931
4
    TmpInst.addOperand(MCOperand::createImm(B - N));
932
4
    TmpInst.addOperand(MCOperand::createImm(31 - N));
933
4
    Inst = TmpInst;
934
4
    break;
935
4
  }
936
4
  case PPC::EXTLDI:
937
4
  case PPC::EXTLDIo: {
938
4
    MCInst TmpInst;
939
4
    int64_t N = Inst.getOperand(2).getImm();
940
4
    int64_t B = Inst.getOperand(3).getImm();
941
4
    TmpInst.setOpcode(Opcode == PPC::EXTLDI? 
PPC::RLDICR2
:
PPC::RLDICRo2
);
942
4
    TmpInst.addOperand(Inst.getOperand(0));
943
4
    TmpInst.addOperand(Inst.getOperand(1));
944
4
    TmpInst.addOperand(MCOperand::createImm(B));
945
4
    TmpInst.addOperand(MCOperand::createImm(N - 1));
946
4
    Inst = TmpInst;
947
4
    break;
948
4
  }
949
4
  case PPC::EXTRDI:
950
4
  case PPC::EXTRDIo: {
951
4
    MCInst TmpInst;
952
4
    int64_t N = Inst.getOperand(2).getImm();
953
4
    int64_t B = Inst.getOperand(3).getImm();
954
4
    TmpInst.setOpcode(Opcode == PPC::EXTRDI? 
PPC::RLDICL2
:
PPC::RLDICLo2
);
955
4
    TmpInst.addOperand(Inst.getOperand(0));
956
4
    TmpInst.addOperand(Inst.getOperand(1));
957
4
    TmpInst.addOperand(MCOperand::createImm(B + N));
958
4
    TmpInst.addOperand(MCOperand::createImm(64 - N));
959
4
    Inst = TmpInst;
960
4
    break;
961
4
  }
962
4
  case PPC::INSRDI:
963
4
  case PPC::INSRDIo: {
964
4
    MCInst TmpInst;
965
4
    int64_t N = Inst.getOperand(2).getImm();
966
4
    int64_t B = Inst.getOperand(3).getImm();
967
4
    TmpInst.setOpcode(Opcode == PPC::INSRDI? 
PPC::RLDIMI2
:
PPC::RLDIMIo2
);
968
4
    TmpInst.addOperand(Inst.getOperand(0));
969
4
    TmpInst.addOperand(Inst.getOperand(0));
970
4
    TmpInst.addOperand(Inst.getOperand(1));
971
4
    TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
972
4
    TmpInst.addOperand(MCOperand::createImm(B));
973
4
    Inst = TmpInst;
974
4
    break;
975
4
  }
976
4
  case PPC::ROTRDI:
977
4
  case PPC::ROTRDIo: {
978
4
    MCInst TmpInst;
979
4
    int64_t N = Inst.getOperand(2).getImm();
980
4
    TmpInst.setOpcode(Opcode == PPC::ROTRDI? 
PPC::RLDICL2
:
PPC::RLDICLo2
);
981
4
    TmpInst.addOperand(Inst.getOperand(0));
982
4
    TmpInst.addOperand(Inst.getOperand(1));
983
4
    TmpInst.addOperand(MCOperand::createImm(64 - N));
984
4
    TmpInst.addOperand(MCOperand::createImm(0));
985
4
    Inst = TmpInst;
986
4
    break;
987
4
  }
988
20
  case PPC::SLDI:
989
20
  case PPC::SLDIo: {
990
20
    MCInst TmpInst;
991
20
    int64_t N = Inst.getOperand(2).getImm();
992
20
    TmpInst.setOpcode(Opcode == PPC::SLDI? 
PPC::RLDICR18
:
PPC::RLDICRo2
);
993
20
    TmpInst.addOperand(Inst.getOperand(0));
994
20
    TmpInst.addOperand(Inst.getOperand(1));
995
20
    TmpInst.addOperand(MCOperand::createImm(N));
996
20
    TmpInst.addOperand(MCOperand::createImm(63 - N));
997
20
    Inst = TmpInst;
998
20
    break;
999
20
  }
1000
20
  case PPC::SUBPCIS: {
1001
2
    MCInst TmpInst;
1002
2
    int64_t N = Inst.getOperand(1).getImm();
1003
2
    TmpInst.setOpcode(PPC::ADDPCIS);
1004
2
    TmpInst.addOperand(Inst.getOperand(0));
1005
2
    TmpInst.addOperand(MCOperand::createImm(-N));
1006
2
    Inst = TmpInst;
1007
2
    break;
1008
20
  }
1009
20
  case PPC::SRDI:
1010
4
  case PPC::SRDIo: {
1011
4
    MCInst TmpInst;
1012
4
    int64_t N = Inst.getOperand(2).getImm();
1013
4
    TmpInst.setOpcode(Opcode == PPC::SRDI? 
PPC::RLDICL2
:
PPC::RLDICLo2
);
1014
4
    TmpInst.addOperand(Inst.getOperand(0));
1015
4
    TmpInst.addOperand(Inst.getOperand(1));
1016
4
    TmpInst.addOperand(MCOperand::createImm(64 - N));
1017
4
    TmpInst.addOperand(MCOperand::createImm(N));
1018
4
    Inst = TmpInst;
1019
4
    break;
1020
4
  }
1021
4
  case PPC::CLRRDI:
1022
4
  case PPC::CLRRDIo: {
1023
4
    MCInst TmpInst;
1024
4
    int64_t N = Inst.getOperand(2).getImm();
1025
4
    TmpInst.setOpcode(Opcode == PPC::CLRRDI? 
PPC::RLDICR2
:
PPC::RLDICRo2
);
1026
4
    TmpInst.addOperand(Inst.getOperand(0));
1027
4
    TmpInst.addOperand(Inst.getOperand(1));
1028
4
    TmpInst.addOperand(MCOperand::createImm(0));
1029
4
    TmpInst.addOperand(MCOperand::createImm(63 - N));
1030
4
    Inst = TmpInst;
1031
4
    break;
1032
4
  }
1033
4
  case PPC::CLRLSLDI:
1034
4
  case PPC::CLRLSLDIo: {
1035
4
    MCInst TmpInst;
1036
4
    int64_t B = Inst.getOperand(2).getImm();
1037
4
    int64_t N = Inst.getOperand(3).getImm();
1038
4
    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? 
PPC::RLDIC2
:
PPC::RLDICo2
);
1039
4
    TmpInst.addOperand(Inst.getOperand(0));
1040
4
    TmpInst.addOperand(Inst.getOperand(1));
1041
4
    TmpInst.addOperand(MCOperand::createImm(N));
1042
4
    TmpInst.addOperand(MCOperand::createImm(B - N));
1043
4
    Inst = TmpInst;
1044
4
    break;
1045
4
  }
1046
8
  case PPC::RLWINMbm:
1047
8
  case PPC::RLWINMobm: {
1048
8
    unsigned MB, ME;
1049
8
    int64_t BM = Inst.getOperand(3).getImm();
1050
8
    if (!isRunOfOnes(BM, MB, ME))
1051
0
      break;
1052
8
1053
8
    MCInst TmpInst;
1054
8
    TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? 
PPC::RLWINM4
:
PPC::RLWINMo4
);
1055
8
    TmpInst.addOperand(Inst.getOperand(0));
1056
8
    TmpInst.addOperand(Inst.getOperand(1));
1057
8
    TmpInst.addOperand(Inst.getOperand(2));
1058
8
    TmpInst.addOperand(MCOperand::createImm(MB));
1059
8
    TmpInst.addOperand(MCOperand::createImm(ME));
1060
8
    Inst = TmpInst;
1061
8
    break;
1062
8
  }
1063
8
  case PPC::RLWIMIbm:
1064
8
  case PPC::RLWIMIobm: {
1065
8
    unsigned MB, ME;
1066
8
    int64_t BM = Inst.getOperand(3).getImm();
1067
8
    if (!isRunOfOnes(BM, MB, ME))
1068
0
      break;
1069
8
1070
8
    MCInst TmpInst;
1071
8
    TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? 
PPC::RLWIMI4
:
PPC::RLWIMIo4
);
1072
8
    TmpInst.addOperand(Inst.getOperand(0));
1073
8
    TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1074
8
    TmpInst.addOperand(Inst.getOperand(1));
1075
8
    TmpInst.addOperand(Inst.getOperand(2));
1076
8
    TmpInst.addOperand(MCOperand::createImm(MB));
1077
8
    TmpInst.addOperand(MCOperand::createImm(ME));
1078
8
    Inst = TmpInst;
1079
8
    break;
1080
8
  }
1081
8
  case PPC::RLWNMbm:
1082
8
  case PPC::RLWNMobm: {
1083
8
    unsigned MB, ME;
1084
8
    int64_t BM = Inst.getOperand(3).getImm();
1085
8
    if (!isRunOfOnes(BM, MB, ME))
1086
0
      break;
1087
8
1088
8
    MCInst TmpInst;
1089
8
    TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? 
PPC::RLWNM4
:
PPC::RLWNMo4
);
1090
8
    TmpInst.addOperand(Inst.getOperand(0));
1091
8
    TmpInst.addOperand(Inst.getOperand(1));
1092
8
    TmpInst.addOperand(Inst.getOperand(2));
1093
8
    TmpInst.addOperand(MCOperand::createImm(MB));
1094
8
    TmpInst.addOperand(MCOperand::createImm(ME));
1095
8
    Inst = TmpInst;
1096
8
    break;
1097
8
  }
1098
41
  case PPC::MFTB: {
1099
41
    if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1100
24
      assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1101
24
      Inst.setOpcode(PPC::MFSPR);
1102
24
    }
1103
41
    break;
1104
8
  }
1105
8
  case PPC::CP_COPYx:
1106
4
  case PPC::CP_COPY_FIRST: {
1107
4
    MCInst TmpInst;
1108
4
    TmpInst.setOpcode(PPC::CP_COPY);
1109
4
    TmpInst.addOperand(Inst.getOperand(0));
1110
4
    TmpInst.addOperand(Inst.getOperand(1));
1111
4
    TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 
02
:
12
));
1112
4
1113
4
    Inst = TmpInst;
1114
4
    break;
1115
4
  }
1116
4
  case PPC::CP_PASTEx :
1117
4
  case PPC::CP_PASTE_LAST: {
1118
4
    MCInst TmpInst;
1119
4
    TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1120
2
                      PPC::CP_PASTE : PPC::CP_PASTEo);
1121
4
    TmpInst.addOperand(Inst.getOperand(0));
1122
4
    TmpInst.addOperand(Inst.getOperand(1));
1123
4
    TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 
02
:
12
));
1124
4
1125
4
    Inst = TmpInst;
1126
4
    break;
1127
4
  }
1128
7.78k
  }
1129
7.78k
}
1130
1131
static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
1132
                                         unsigned VariantID = 0);
1133
1134
bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1135
                                           OperandVector &Operands,
1136
                                           MCStreamer &Out, uint64_t &ErrorInfo,
1137
7.82k
                                           bool MatchingInlineAsm) {
1138
7.82k
  MCInst Inst;
1139
7.82k
1140
7.82k
  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1141
7.82k
  case Match_Success:
1142
7.78k
    // Post-process instructions (typically extended mnemonics)
1143
7.78k
    ProcessInstruction(Inst, Operands);
1144
7.78k
    Inst.setLoc(IDLoc);
1145
7.78k
    Out.EmitInstruction(Inst, getSTI());
1146
7.78k
    return false;
1147
7.82k
  case Match_MissingFeature:
1148
0
    return Error(IDLoc, "instruction use requires an option to be enabled");
1149
7.82k
  case Match_MnemonicFail: {
1150
4
    FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1151
4
    std::string Suggestion = PPCMnemonicSpellCheck(
1152
4
        ((PPCOperand &)*Operands[0]).getToken(), FBS);
1153
4
    return Error(IDLoc, "invalid instruction" + Suggestion,
1154
4
                 ((PPCOperand &)*Operands[0]).getLocRange());
1155
7.82k
  }
1156
7.82k
  case Match_InvalidOperand: {
1157
32
    SMLoc ErrorLoc = IDLoc;
1158
32
    if (ErrorInfo != ~0ULL) {
1159
32
      if (ErrorInfo >= Operands.size())
1160
0
        return Error(IDLoc, "too few operands for instruction");
1161
32
1162
32
      ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1163
32
      if (ErrorLoc == SMLoc()) 
ErrorLoc = IDLoc0
;
1164
32
    }
1165
32
1166
32
    return Error(ErrorLoc, "invalid operand for instruction");
1167
0
  }
1168
0
  }
1169
0
1170
0
  llvm_unreachable("Implement any new match types added!");
1171
0
}
1172
1173
2.00k
bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1174
2.00k
  if (getParser().getTok().is(AsmToken::Identifier)) {
1175
1.98k
    StringRef Name = getParser().getTok().getString();
1176
1.98k
    if (Name.equals_lower("lr")) {
1177
3
      RegNo = isPPC64()? PPC::LR8 : 
PPC::LR0
;
1178
3
      IntVal = 8;
1179
1.97k
    } else if (Name.equals_lower("ctr")) {
1180
2
      RegNo = isPPC64()? PPC::CTR8 : 
PPC::CTR0
;
1181
2
      IntVal = 9;
1182
1.97k
    } else if (Name.equals_lower("vrsave")) {
1183
2
      RegNo = PPC::VRSAVE;
1184
2
      IntVal = 256;
1185
1.97k
    } else if (Name.startswith_lower("r") &&
1186
1.97k
               
!Name.substr(1).getAsInteger(10, IntVal)1.78k
&&
IntVal < 321.78k
) {
1187
1.77k
      RegNo = isPPC64()? 
XRegs[IntVal]1.72k
:
RRegs[IntVal]48
;
1188
1.77k
    } else 
if (201
Name.startswith_lower("f")201
&&
1189
201
               
!Name.substr(1).getAsInteger(10, IntVal)66
&&
IntVal < 3266
) {
1190
66
      RegNo = FRegs[IntVal];
1191
135
    } else if (Name.startswith_lower("vs") &&
1192
135
               
!Name.substr(2).getAsInteger(10, IntVal)4
&&
IntVal < 644
) {
1193
4
      RegNo = VSRegs[IntVal];
1194
131
    } else if (Name.startswith_lower("v") &&
1195
131
               
!Name.substr(1).getAsInteger(10, IntVal)66
&&
IntVal < 3266
) {
1196
66
      RegNo = VRegs[IntVal];
1197
66
    } else 
if (65
Name.startswith_lower("q")65
&&
1198
65
               
!Name.substr(1).getAsInteger(10, IntVal)2
&&
IntVal < 322
) {
1199
2
      RegNo = QFRegs[IntVal];
1200
63
    } else if (Name.startswith_lower("cr") &&
1201
63
               
!Name.substr(2).getAsInteger(10, IntVal)50
&&
IntVal < 850
) {
1202
50
      RegNo = CRRegs[IntVal];
1203
50
    } else
1204
13
      return true;
1205
1.96k
    getParser().Lex();
1206
1.96k
    return false;
1207
1.96k
  }
1208
18
  return true;
1209
18
}
1210
1211
bool PPCAsmParser::
1212
221
ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1213
221
  const AsmToken &Tok = getParser().getTok();
1214
221
  StartLoc = Tok.getLoc();
1215
221
  EndLoc = Tok.getEndLoc();
1216
221
  RegNo = 0;
1217
221
  int64_t IntVal;
1218
221
  if (MatchRegisterName(RegNo, IntVal))
1219
0
    return TokError("invalid register name");
1220
221
  return false;
1221
221
}
1222
1223
/// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1224
/// the expression and check for VK_PPC_LO/HI/HA
1225
/// symbol variants.  If all symbols with modifier use the same
1226
/// variant, return the corresponding PPCMCExpr::VariantKind,
1227
/// and a modified expression using the default symbol variant.
1228
/// Otherwise, return NULL.
1229
const MCExpr *PPCAsmParser::
1230
ExtractModifierFromExpr(const MCExpr *E,
1231
15.1k
                        PPCMCExpr::VariantKind &Variant) {
1232
15.1k
  MCContext &Context = getParser().getContext();
1233
15.1k
  Variant = PPCMCExpr::VK_PPC_None;
1234
15.1k
1235
15.1k
  switch (E->getKind()) {
1236
15.1k
  case MCExpr::Target:
1237
12.2k
  case MCExpr::Constant:
1238
12.2k
    return nullptr;
1239
12.2k
1240
12.2k
  case MCExpr::SymbolRef: {
1241
2.50k
    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1242
2.50k
1243
2.50k
    switch (SRE->getKind()) {
1244
2.50k
    case MCSymbolRefExpr::VK_PPC_LO:
1245
151
      Variant = PPCMCExpr::VK_PPC_LO;
1246
151
      break;
1247
2.50k
    case MCSymbolRefExpr::VK_PPC_HI:
1248
23
      Variant = PPCMCExpr::VK_PPC_HI;
1249
23
      break;
1250
2.50k
    case MCSymbolRefExpr::VK_PPC_HA:
1251
138
      Variant = PPCMCExpr::VK_PPC_HA;
1252
138
      break;
1253
2.50k
    case MCSymbolRefExpr::VK_PPC_HIGH:
1254
6
      Variant = PPCMCExpr::VK_PPC_HIGH;
1255
6
      break;
1256
2.50k
    case MCSymbolRefExpr::VK_PPC_HIGHA:
1257
6
      Variant = PPCMCExpr::VK_PPC_HIGHA;
1258
6
      break;
1259
2.50k
    case MCSymbolRefExpr::VK_PPC_HIGHER:
1260
8
      Variant = PPCMCExpr::VK_PPC_HIGHER;
1261
8
      break;
1262
2.50k
    case MCSymbolRefExpr::VK_PPC_HIGHERA:
1263
8
      Variant = PPCMCExpr::VK_PPC_HIGHERA;
1264
8
      break;
1265
2.50k
    case MCSymbolRefExpr::VK_PPC_HIGHEST:
1266
8
      Variant = PPCMCExpr::VK_PPC_HIGHEST;
1267
8
      break;
1268
2.50k
    case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1269
8
      Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1270
8
      break;
1271
2.50k
    default:
1272
2.14k
      return nullptr;
1273
356
    }
1274
356
1275
356
    return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1276
356
  }
1277
356
1278
356
  case MCExpr::Unary: {
1279
5
    const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1280
5
    const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1281
5
    if (!Sub)
1282
0
      return nullptr;
1283
5
    return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1284
5
  }
1285
5
1286
419
  case MCExpr::Binary: {
1287
419
    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1288
419
    PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1289
419
    const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1290
419
    const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1291
419
1292
419
    if (!LHS && !RHS)
1293
186
      return nullptr;
1294
233
1295
233
    if (!LHS) LHS = BE->getLHS();
1296
233
    if (!RHS) 
RHS = BE->getRHS()0
;
1297
233
1298
233
    if (LHSVariant == PPCMCExpr::VK_PPC_None)
1299
233
      Variant = RHSVariant;
1300
0
    else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1301
0
      Variant = LHSVariant;
1302
0
    else if (LHSVariant == RHSVariant)
1303
0
      Variant = LHSVariant;
1304
0
    else
1305
0
      return nullptr;
1306
233
1307
233
    return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1308
233
  }
1309
0
  }
1310
0
1311
0
  llvm_unreachable("Invalid expression kind!");
1312
0
}
1313
1314
/// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1315
/// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1316
/// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1317
/// FIXME: This is a hack.
1318
const MCExpr *PPCAsmParser::
1319
15.1k
FixupVariantKind(const MCExpr *E) {
1320
15.1k
  MCContext &Context = getParser().getContext();
1321
15.1k
1322
15.1k
  switch (E->getKind()) {
1323
15.1k
  case MCExpr::Target:
1324
12.2k
  case MCExpr::Constant:
1325
12.2k
    return E;
1326
12.2k
1327
12.2k
  case MCExpr::SymbolRef: {
1328
2.50k
    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1329
2.50k
    MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1330
2.50k
1331
2.50k
    switch (SRE->getKind()) {
1332
2.50k
    case MCSymbolRefExpr::VK_TLSGD:
1333
11
      Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1334
11
      break;
1335
2.50k
    case MCSymbolRefExpr::VK_TLSLD:
1336
27
      Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1337
27
      break;
1338
2.50k
    default:
1339
2.46k
      return E;
1340
38
    }
1341
38
    return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1342
38
  }
1343
38
1344
38
  case MCExpr::Unary: {
1345
5
    const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1346
5
    const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1347
5
    if (Sub == UE->getSubExpr())
1348
5
      return E;
1349
0
    return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1350
0
  }
1351
0
1352
419
  case MCExpr::Binary: {
1353
419
    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1354
419
    const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1355
419
    const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1356
419
    if (LHS == BE->getLHS() && RHS == BE->getRHS())
1357
419
      return E;
1358
0
    return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1359
0
  }
1360
0
  }
1361
0
1362
0
  llvm_unreachable("Invalid expression kind!");
1363
0
}
1364
1365
/// ParseExpression.  This differs from the default "parseExpression" in that
1366
/// it handles modifiers.
1367
bool PPCAsmParser::
1368
14.3k
ParseExpression(const MCExpr *&EVal) {
1369
14.3k
1370
14.3k
  if (isDarwin())
1371
25
    return ParseDarwinExpression(EVal);
1372
14.3k
1373
14.3k
  // (ELF Platforms)
1374
14.3k
  // Handle \code @l/@ha \endcode
1375
14.3k
  if (getParser().parseExpression(EVal))
1376
2
    return true;
1377
14.3k
1378
14.3k
  EVal = FixupVariantKind(EVal);
1379
14.3k
1380
14.3k
  PPCMCExpr::VariantKind Variant;
1381
14.3k
  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1382
14.3k
  if (E)
1383
356
    EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1384
14.3k
1385
14.3k
  return false;
1386
14.3k
}
1387
1388
/// ParseDarwinExpression.  (MachO Platforms)
1389
/// This differs from the default "parseExpression" in that it handles detection
1390
/// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1391
/// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1392
/// syntax form so it is done here.  TODO: Determine if there is merit in
1393
/// arranging for this to be done at a higher level.
1394
bool PPCAsmParser::
1395
25
ParseDarwinExpression(const MCExpr *&EVal) {
1396
25
  MCAsmParser &Parser = getParser();
1397
25
  PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1398
25
  switch (getLexer().getKind()) {
1399
25
  default:
1400
18
    break;
1401
25
  case AsmToken::Identifier:
1402
7
    // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1403
7
    // something starting with any other char should be part of the
1404
7
    // asm syntax.  If handwritten asm includes an identifier like lo16,
1405
7
    // then all bets are off - but no-one would do that, right?
1406
7
    StringRef poss = Parser.getTok().getString();
1407
7
    if (poss.equals_lower("lo16")) {
1408
2
      Variant = PPCMCExpr::VK_PPC_LO;
1409
5
    } else if (poss.equals_lower("hi16")) {
1410
0
      Variant = PPCMCExpr::VK_PPC_HI;
1411
5
    } else if (poss.equals_lower("ha16")) {
1412
2
      Variant = PPCMCExpr::VK_PPC_HA;
1413
2
    }
1414
7
    if (Variant != PPCMCExpr::VK_PPC_None) {
1415
4
      Parser.Lex(); // Eat the xx16
1416
4
      if (getLexer().isNot(AsmToken::LParen))
1417
0
        return Error(Parser.getTok().getLoc(), "expected '('");
1418
4
      Parser.Lex(); // Eat the '('
1419
4
    }
1420
7
    break;
1421
25
  }
1422
25
1423
25
  if (getParser().parseExpression(EVal))
1424
0
    return true;
1425
25
1426
25
  if (Variant != PPCMCExpr::VK_PPC_None) {
1427
4
    if (getLexer().isNot(AsmToken::RParen))
1428
0
      return Error(Parser.getTok().getLoc(), "expected ')'");
1429
4
    Parser.Lex(); // Eat the ')'
1430
4
    EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1431
4
  }
1432
25
  return false;
1433
25
}
1434
1435
/// ParseOperand
1436
/// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1437
/// rNN for MachO.
1438
15.9k
bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1439
15.9k
  MCAsmParser &Parser = getParser();
1440
15.9k
  SMLoc S = Parser.getTok().getLoc();
1441
15.9k
  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1442
15.9k
  const MCExpr *EVal;
1443
15.9k
1444
15.9k
  // Attempt to parse the next token as an immediate
1445
15.9k
  switch (getLexer().getKind()) {
1446
15.9k
  // Special handling for register names.  These are interpreted
1447
15.9k
  // as immediates corresponding to the register number.
1448
15.9k
  case AsmToken::Percent:
1449
1.59k
    Parser.Lex(); // Eat the '%'.
1450
1.59k
    unsigned RegNo;
1451
1.59k
    int64_t IntVal;
1452
1.59k
    if (MatchRegisterName(RegNo, IntVal))
1453
2
      return Error(S, "invalid register name");
1454
1.59k
1455
1.59k
    Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1456
1.59k
    return false;
1457
1.59k
1458
14.3k
  case AsmToken::Identifier:
1459
14.3k
  case AsmToken::LParen:
1460
14.3k
  case AsmToken::Plus:
1461
14.3k
  case AsmToken::Minus:
1462
14.3k
  case AsmToken::Integer:
1463
14.3k
  case AsmToken::Dot:
1464
14.3k
  case AsmToken::Dollar:
1465
14.3k
  case AsmToken::Exclaim:
1466
14.3k
  case AsmToken::Tilde:
1467
14.3k
    // Note that non-register-name identifiers from the compiler will begin
1468
14.3k
    // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1469
14.3k
    // identifiers like r31foo - so we fall through in the event that parsing
1470
14.3k
    // a register name fails.
1471
14.3k
    if (isDarwin()) {
1472
55
      unsigned RegNo;
1473
55
      int64_t IntVal;
1474
55
      if (!MatchRegisterName(RegNo, IntVal)) {
1475
30
        Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1476
30
        return false;
1477
30
      }
1478
14.3k
    }
1479
14.3k
    // All other expressions
1480
14.3k
1481
14.3k
    if (!ParseExpression(EVal))
1482
14.3k
      break;
1483
2
    // Fall-through
1484
2
    LLVM_FALLTHROUGH;
1485
2
  default:
1486
2
    return Error(S, "unknown operand");
1487
14.3k
  }
1488
14.3k
1489
14.3k
  // Push the parsed operand into the list of operands
1490
14.3k
  Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1491
14.3k
1492
14.3k
  // Check whether this is a TLS call expression
1493
14.3k
  bool TLSCall = false;
1494
14.3k
  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1495
1.68k
    TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1496
14.3k
1497
14.3k
  if (TLSCall && 
getLexer().is(AsmToken::LParen)38
) {
1498
38
    const MCExpr *TLSSym;
1499
38
1500
38
    Parser.Lex(); // Eat the '('.
1501
38
    S = Parser.getTok().getLoc();
1502
38
    if (ParseExpression(TLSSym))
1503
0
      return Error(S, "invalid TLS call expression");
1504
38
    if (getLexer().isNot(AsmToken::RParen))
1505
0
      return Error(Parser.getTok().getLoc(), "missing ')'");
1506
38
    E = Parser.getTok().getLoc();
1507
38
    Parser.Lex(); // Eat the ')'.
1508
38
1509
38
    Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1510
38
  }
1511
14.3k
1512
14.3k
  // Otherwise, check for D-form memory operands
1513
14.3k
  if (!TLSCall && 
getLexer().is(AsmToken::LParen)14.2k
) {
1514
771
    Parser.Lex(); // Eat the '('.
1515
771
    S = Parser.getTok().getLoc();
1516
771
1517
771
    int64_t IntVal;
1518
771
    switch (getLexer().getKind()) {
1519
771
    case AsmToken::Percent:
1520
117
      Parser.Lex(); // Eat the '%'.
1521
117
      unsigned RegNo;
1522
117
      if (MatchRegisterName(RegNo, IntVal))
1523
4
        return Error(S, "invalid register name");
1524
113
      break;
1525
113
1526
644
    case AsmToken::Integer:
1527
644
      if (isDarwin())
1528
0
        return Error(S, "unexpected integer value");
1529
644
      else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1530
644
               IntVal > 31)
1531
4
        return Error(S, "invalid register number");
1532
640
      break;
1533
640
   case AsmToken::Identifier:
1534
10
    if (isDarwin()) {
1535
10
      unsigned RegNo;
1536
10
      if (!MatchRegisterName(RegNo, IntVal)) {
1537
10
        break;
1538
10
      }
1539
0
    }
1540
0
    LLVM_FALLTHROUGH;
1541
0
1542
0
    default:
1543
0
      return Error(S, "invalid memory operand");
1544
763
    }
1545
763
1546
763
    E = Parser.getTok().getLoc();
1547
763
    if (parseToken(AsmToken::RParen, "missing ')'"))
1548
0
      return true;
1549
763
    Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1550
763
  }
1551
14.3k
1552
14.3k
  
return false14.3k
;
1553
14.3k
}
1554
1555
/// Parse an instruction mnemonic followed by its operands.
1556
bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1557
7.83k
                                    SMLoc NameLoc, OperandVector &Operands) {
1558
7.83k
  // The first operand is the token for the instruction name.
1559
7.83k
  // If the next character is a '+' or '-', we need to add it to the
1560
7.83k
  // instruction name, to match what TableGen is doing.
1561
7.83k
  std::string NewOpcode;
1562
7.83k
  if (parseOptionalToken(AsmToken::Plus)) {
1563
448
    NewOpcode = Name;
1564
448
    NewOpcode += '+';
1565
448
    Name = NewOpcode;
1566
448
  }
1567
7.83k
  if (parseOptionalToken(AsmToken::Minus)) {
1568
474
    NewOpcode = Name;
1569
474
    NewOpcode += '-';
1570
474
    Name = NewOpcode;
1571
474
  }
1572
7.83k
  // If the instruction ends in a '.', we need to create a separate
1573
7.83k
  // token for it, to match what TableGen is doing.
1574
7.83k
  size_t Dot = Name.find('.');
1575
7.83k
  StringRef Mnemonic = Name.slice(0, Dot);
1576
7.83k
  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1577
922
    Operands.push_back(
1578
922
        PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1579
6.91k
  else
1580
6.91k
    Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1581
7.83k
  if (Dot != StringRef::npos) {
1582
417
    SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1583
417
    StringRef DotStr = Name.slice(Dot, StringRef::npos);
1584
417
    if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1585
0
      Operands.push_back(
1586
0
          PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1587
417
    else
1588
417
      Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1589
417
  }
1590
7.83k
1591
7.83k
  // If there are no more operands then finish
1592
7.83k
  if (parseOptionalToken(AsmToken::EndOfStatement))
1593
780
    return false;
1594
7.05k
1595
7.05k
  // Parse the first operand
1596
7.05k
  if (ParseOperand(Operands))
1597
2
    return true;
1598
7.05k
1599
15.9k
  
while (7.05k
!parseOptionalToken(AsmToken::EndOfStatement)) {
1600
8.91k
    if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1601
10
      return true;
1602
8.91k
  }
1603
7.05k
1604
7.05k
  // We'll now deal with an unfortunate special case: the syntax for the dcbt
1605
7.05k
  // and dcbtst instructions differs for server vs. embedded cores.
1606
7.05k
  //  The syntax for dcbt is:
1607
7.05k
  //    dcbt ra, rb, th [server]
1608
7.05k
  //    dcbt th, ra, rb [embedded]
1609
7.05k
  //  where th can be omitted when it is 0. dcbtst is the same. We take the
1610
7.05k
  //  server form to be the default, so swap the operands if we're parsing for
1611
7.05k
  //  an embedded core (they'll be swapped again upon printing).
1612
7.05k
  
if (7.04k
getSTI().getFeatureBits()[PPC::FeatureBookE]7.04k
&&
1613
7.04k
      
Operands.size() == 49
&&
1614
7.04k
      
(9
Name == "dcbt"9
||
Name == "dcbtst"7
)) {
1615
4
    std::swap(Operands[1], Operands[3]);
1616
4
    std::swap(Operands[2], Operands[1]);
1617
4
  }
1618
7.04k
1619
7.04k
  return false;
1620
7.05k
}
1621
1622
/// ParseDirective parses the PPC specific directives
1623
2.29k
bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1624
2.29k
  StringRef IDVal = DirectiveID.getIdentifier();
1625
2.29k
  if (isDarwin()) {
1626
35
    if (IDVal == ".machine")
1627
2
      ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1628
33
    else
1629
33
      return true;
1630
2.25k
  } else if (IDVal == ".word")
1631
47
    ParseDirectiveWord(2, DirectiveID);
1632
2.21k
  else if (IDVal == ".llong")
1633
15
    ParseDirectiveWord(8, DirectiveID);
1634
2.19k
  else if (IDVal == ".tc")
1635
42
    ParseDirectiveTC(isPPC64() ? 
838
:
44
, DirectiveID);
1636
2.15k
  else if (IDVal == ".machine")
1637
42
    ParseDirectiveMachine(DirectiveID.getLoc());
1638
2.11k
  else if (IDVal == ".abiversion")
1639
95
    ParseDirectiveAbiVersion(DirectiveID.getLoc());
1640
2.01k
  else if (IDVal == ".localentry")
1641
126
    ParseDirectiveLocalEntry(DirectiveID.getLoc());
1642
1.89k
  else
1643
1.89k
    return true;
1644
369
  return false;
1645
369
}
1646
1647
/// ParseDirectiveWord
1648
///  ::= .word [ expression (, expression)* ]
1649
104
bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1650
104
  auto parseOp = [&]() -> bool {
1651
98
    const MCExpr *Value;
1652
98
    SMLoc ExprLoc = getParser().getTok().getLoc();
1653
98
    if (getParser().parseExpression(Value))
1654
6
      return true;
1655
92
    if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1656
48
      assert(Size <= 8 && "Invalid size");
1657
48
      uint64_t IntValue = MCE->getValue();
1658
48
      if (!isUIntN(8 * Size, IntValue) && 
!isIntN(8 * Size, IntValue)0
)
1659
0
        return Error(ExprLoc, "literal value out of range for '" +
1660
0
                                  ID.getIdentifier() + "' directive");
1661
48
      getStreamer().EmitIntValue(IntValue, Size);
1662
48
    } else
1663
44
      getStreamer().EmitValue(Value, Size, ExprLoc);
1664
92
    return false;
1665
92
  };
1666
104
1667
104
  if (parseMany(parseOp))
1668
24
    return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1669
80
  return false;
1670
80
}
1671
1672
/// ParseDirectiveTC
1673
///  ::= .tc [ symbol (, expression)* ]
1674
42
bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1675
42
  MCAsmParser &Parser = getParser();
1676
42
  // Skip TC symbol, which is only used with XCOFF.
1677
210
  while (getLexer().isNot(AsmToken::EndOfStatement)
1678
210
         && getLexer().isNot(AsmToken::Comma))
1679
168
    Parser.Lex();
1680
42
  if (parseToken(AsmToken::Comma))
1681
0
    return addErrorSuffix(" in '.tc' directive");
1682
42
1683
42
  // Align to word size.
1684
42
  getParser().getStreamer().EmitValueToAlignment(Size);
1685
42
1686
42
  // Emit expressions.
1687
42
  return ParseDirectiveWord(Size, ID);
1688
42
}
1689
1690
/// ParseDirectiveMachine (ELF platforms)
1691
///  ::= .machine [ cpu | "push" | "pop" ]
1692
42
bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1693
42
  MCAsmParser &Parser = getParser();
1694
42
  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1695
42
      
Parser.getTok().isNot(AsmToken::String)21
)
1696
0
    return Error(L, "unexpected token in '.machine' directive");
1697
42
1698
42
  StringRef CPU = Parser.getTok().getIdentifier();
1699
42
1700
42
  // FIXME: Right now, the parser always allows any available
1701
42
  // instruction, so the .machine directive is not useful.
1702
42
  // Implement ".machine any" (by doing nothing) for the benefit
1703
42
  // of existing assembler code.  Likewise, we can then implement
1704
42
  // ".machine push" and ".machine pop" as no-op.
1705
42
  if (CPU != "any" && 
CPU != "push"12
&&
CPU != "pop"6
)
1706
0
    return TokError("unrecognized machine type");
1707
42
1708
42
  Parser.Lex();
1709
42
1710
42
  if (parseToken(AsmToken::EndOfStatement))
1711
12
    return addErrorSuffix(" in '.machine' directive");
1712
30
1713
30
  PPCTargetStreamer &TStreamer =
1714
30
      *static_cast<PPCTargetStreamer *>(
1715
30
           getParser().getStreamer().getTargetStreamer());
1716
30
  TStreamer.emitMachine(CPU);
1717
30
1718
30
  return false;
1719
30
}
1720
1721
/// ParseDarwinDirectiveMachine (Mach-o platforms)
1722
///  ::= .machine cpu-identifier
1723
2
bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1724
2
  MCAsmParser &Parser = getParser();
1725
2
  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1726
2
      
Parser.getTok().isNot(AsmToken::String)0
)
1727
0
    return Error(L, "unexpected token in directive");
1728
2
1729
2
  StringRef CPU = Parser.getTok().getIdentifier();
1730
2
  Parser.Lex();
1731
2
1732
2
  // FIXME: this is only the 'default' set of cpu variants.
1733
2
  // However we don't act on this information at present, this is simply
1734
2
  // allowing parsing to proceed with minimal sanity checking.
1735
2
  if (check(CPU != "ppc7400" && 
CPU != "ppc"1
&&
CPU != "ppc64"0
, L,
1736
2
            "unrecognized cpu type") ||
1737
2
      check(isPPC64() && 
(0
CPU == "ppc7400"0
||
CPU == "ppc"0
), L,
1738
2
            "wrong cpu type specified for 64bit") ||
1739
2
      check(!isPPC64() && CPU == "ppc64", L,
1740
2
            "wrong cpu type specified for 32bit") ||
1741
2
      parseToken(AsmToken::EndOfStatement))
1742
0
    return addErrorSuffix(" in '.machine' directive");
1743
2
  return false;
1744
2
}
1745
1746
/// ParseDirectiveAbiVersion
1747
///  ::= .abiversion constant-expression
1748
95
bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1749
95
  int64_t AbiVersion;
1750
95
  if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1751
95
            "expected constant expression") ||
1752
95
      parseToken(AsmToken::EndOfStatement))
1753
6
    return addErrorSuffix(" in '.abiversion' directive");
1754
89
1755
89
  PPCTargetStreamer &TStreamer =
1756
89
      *static_cast<PPCTargetStreamer *>(
1757
89
           getParser().getStreamer().getTargetStreamer());
1758
89
  TStreamer.emitAbiVersion(AbiVersion);
1759
89
1760
89
  return false;
1761
89
}
1762
1763
/// ParseDirectiveLocalEntry
1764
///  ::= .localentry symbol, expression
1765
126
bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1766
126
  StringRef Name;
1767
126
  if (getParser().parseIdentifier(Name))
1768
0
    return Error(L, "expected identifier in '.localentry' directive");
1769
126
1770
126
  MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1771
126
  const MCExpr *Expr;
1772
126
1773
126
  if (parseToken(AsmToken::Comma) ||
1774
126
      check(getParser().parseExpression(Expr), L, "expected expression") ||
1775
126
      parseToken(AsmToken::EndOfStatement))
1776
6
    return addErrorSuffix(" in '.localentry' directive");
1777
120
1778
120
  PPCTargetStreamer &TStreamer =
1779
120
      *static_cast<PPCTargetStreamer *>(
1780
120
           getParser().getStreamer().getTargetStreamer());
1781
120
  TStreamer.emitLocalEntry(Sym, Expr);
1782
120
1783
120
  return false;
1784
120
}
1785
1786
1787
1788
/// Force static initialization.
1789
91.7k
extern "C" void LLVMInitializePowerPCAsmParser() {
1790
91.7k
  RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target());
1791
91.7k
  RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target());
1792
91.7k
  RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget());
1793
91.7k
}
1794
1795
#define GET_REGISTER_MATCHER
1796
#define GET_MATCHER_IMPLEMENTATION
1797
#define GET_MNEMONIC_SPELL_CHECKER
1798
#include "PPCGenAsmMatcher.inc"
1799
1800
// Define this matcher function after the auto-generated include so we
1801
// have the match class enum definitions.
1802
unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1803
1.65k
                                                  unsigned Kind) {
1804
1.65k
  // If the kind is a token for a literal immediate, check if our asm
1805
1.65k
  // operand matches. This is for InstAliases which have a fixed-value
1806
1.65k
  // immediate in the syntax.
1807
1.65k
  int64_t ImmVal;
1808
1.65k
  switch (Kind) {
1809
1.65k
    
case MCK_0: ImmVal = 0; break118
;
1810
1.65k
    
case MCK_1: ImmVal = 1; break94
;
1811
1.65k
    
case MCK_2: ImmVal = 2; break56
;
1812
1.65k
    
case MCK_3: ImmVal = 3; break36
;
1813
1.65k
    
case MCK_4: ImmVal = 4; break16
;
1814
1.65k
    
case MCK_5: ImmVal = 5; break12
;
1815
1.65k
    
case MCK_6: ImmVal = 6; break8
;
1816
1.65k
    
case MCK_7: ImmVal = 7; break4
;
1817
1.65k
    
default: return Match_InvalidOperand1.31k
;
1818
344
  }
1819
344
1820
344
  PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1821
344
  if (Op.isImm() && Op.getImm() == ImmVal)
1822
126
    return Match_Success;
1823
218
1824
218
  return Match_InvalidOperand;
1825
218
}
1826
1827
const MCExpr *
1828
PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1829
                                  MCSymbolRefExpr::VariantKind Variant,
1830
69
                                  MCContext &Ctx) {
1831
69
  switch (Variant) {
1832
69
  case MCSymbolRefExpr::VK_PPC_LO:
1833
19
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1834
69
  case MCSymbolRefExpr::VK_PPC_HI:
1835
12
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1836
69
  case MCSymbolRefExpr::VK_PPC_HA:
1837
12
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1838
69
  case MCSymbolRefExpr::VK_PPC_HIGH:
1839
0
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, false, Ctx);
1840
69
  case MCSymbolRefExpr::VK_PPC_HIGHA:
1841
0
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, false, Ctx);
1842
69
  case MCSymbolRefExpr::VK_PPC_HIGHER:
1843
0
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1844
69
  case MCSymbolRefExpr::VK_PPC_HIGHERA:
1845
0
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1846
69
  case MCSymbolRefExpr::VK_PPC_HIGHEST:
1847
0
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1848
69
  case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1849
0
    return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1850
69
  default:
1851
26
    return nullptr;
1852
69
  }
1853
69
}