Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This class prints an PPC MCInst to a .s file.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MCTargetDesc/PPCInstPrinter.h"
14
#include "MCTargetDesc/PPCMCTargetDesc.h"
15
#include "MCTargetDesc/PPCPredicates.h"
16
#include "PPCInstrInfo.h"
17
#include "llvm/CodeGen/TargetOpcodes.h"
18
#include "llvm/MC/MCExpr.h"
19
#include "llvm/MC/MCInst.h"
20
#include "llvm/MC/MCInstrInfo.h"
21
#include "llvm/MC/MCRegisterInfo.h"
22
#include "llvm/MC/MCSubtargetInfo.h"
23
#include "llvm/MC/MCSymbol.h"
24
#include "llvm/Support/CommandLine.h"
25
#include "llvm/Support/raw_ostream.h"
26
using namespace llvm;
27
28
#define DEBUG_TYPE "asm-printer"
29
30
// FIXME: Once the integrated assembler supports full register names, tie this
31
// to the verbose-asm setting.
32
static cl::opt<bool>
33
FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34
             cl::desc("Use full register names when printing assembly"));
35
36
// Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37
static cl::opt<bool>
38
ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39
             cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40
41
// Prints full register names with percent symbol.
42
static cl::opt<bool>
43
FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44
                        cl::init(false),
45
                        cl::desc("Prints full register names with percent"));
46
47
#define PRINT_ALIAS_INSTR
48
#include "PPCGenAsmWriter.inc"
49
50
2.31k
void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51
2.31k
  const char *RegName = getRegisterName(RegNo);
52
2.31k
  if (RegName[0] == 'q' /* QPX */) {
53
313
    // The system toolchain on the BG/Q does not understand QPX register names
54
313
    // in .cfi_* directives, so print the name of the floating-point
55
313
    // subregister instead.
56
313
    std::string RN(RegName);
57
313
58
313
    RN[0] = 'f';
59
313
    OS << RN;
60
313
61
313
    return;
62
313
  }
63
2.00k
64
2.00k
  OS << RegName;
65
2.00k
}
66
67
void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
68
113k
                               StringRef Annot, const MCSubtargetInfo &STI) {
69
113k
  // Check for slwi/srwi mnemonics.
70
113k
  if (MI->getOpcode() == PPC::RLWINM) {
71
1.27k
    unsigned char SH = MI->getOperand(2).getImm();
72
1.27k
    unsigned char MB = MI->getOperand(3).getImm();
73
1.27k
    unsigned char ME = MI->getOperand(4).getImm();
74
1.27k
    bool useSubstituteMnemonic = false;
75
1.27k
    if (SH <= 31 && MB == 0 && 
ME == (31-SH)237
) {
76
143
      O << "\tslwi "; useSubstituteMnemonic = true;
77
143
    }
78
1.27k
    if (SH <= 31 && MB == (32-SH) && 
ME == 31575
) {
79
575
      O << "\tsrwi "; useSubstituteMnemonic = true;
80
575
      SH = 32-SH;
81
575
    }
82
1.27k
    if (useSubstituteMnemonic) {
83
718
      printOperand(MI, 0, O);
84
718
      O << ", ";
85
718
      printOperand(MI, 1, O);
86
718
      O << ", " << (unsigned int)SH;
87
718
88
718
      printAnnotation(O, Annot);
89
718
      return;
90
718
    }
91
112k
  }
92
112k
93
112k
  if ((MI->getOpcode() == PPC::OR || 
MI->getOpcode() == PPC::OR8111k
) &&
94
112k
      
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()2.54k
) {
95
2.29k
    O << "\tmr ";
96
2.29k
    printOperand(MI, 0, O);
97
2.29k
    O << ", ";
98
2.29k
    printOperand(MI, 1, O);
99
2.29k
    printAnnotation(O, Annot);
100
2.29k
    return;
101
2.29k
  }
102
110k
103
110k
  if (MI->getOpcode() == PPC::RLDICR ||
104
110k
      
MI->getOpcode() == PPC::RLDICR_32109k
) {
105
865
    unsigned char SH = MI->getOperand(2).getImm();
106
865
    unsigned char ME = MI->getOperand(3).getImm();
107
865
    // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
108
865
    if (63-SH == ME) {
109
795
      O << "\tsldi ";
110
795
      printOperand(MI, 0, O);
111
795
      O << ", ";
112
795
      printOperand(MI, 1, O);
113
795
      O << ", " << (unsigned int)SH;
114
795
      printAnnotation(O, Annot);
115
795
      return;
116
795
    }
117
109k
  }
118
109k
119
109k
  // dcbt[st] is printed manually here because:
120
109k
  //  1. The assembly syntax is different between embedded and server targets
121
109k
  //  2. We must print the short mnemonics for TH == 0 because the
122
109k
  //     embedded/server syntax default will not be stable across assemblers
123
109k
  //  The syntax for dcbt is:
124
109k
  //    dcbt ra, rb, th [server]
125
109k
  //    dcbt th, ra, rb [embedded]
126
109k
  //  where th can be omitted when it is 0. dcbtst is the same.
127
109k
  if (MI->getOpcode() == PPC::DCBT || 
MI->getOpcode() == PPC::DCBTST109k
) {
128
72
    unsigned char TH = MI->getOperand(0).getImm();
129
72
    O << "\tdcbt";
130
72
    if (MI->getOpcode() == PPC::DCBTST)
131
25
      O << "st";
132
72
    if (TH == 16)
133
8
      O << "t";
134
72
    O << " ";
135
72
136
72
    bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
137
72
    if (IsBookE && 
TH != 021
&&
TH != 166
)
138
6
      O << (unsigned int) TH << ", ";
139
72
140
72
    printOperand(MI, 1, O);
141
72
    O << ", ";
142
72
    printOperand(MI, 2, O);
143
72
144
72
    if (!IsBookE && 
TH != 051
&&
TH != 1628
)
145
20
      O << ", " << (unsigned int) TH;
146
72
147
72
    printAnnotation(O, Annot);
148
72
    return;
149
72
  }
150
109k
151
109k
  if (MI->getOpcode() == PPC::DCBF) {
152
14
    unsigned char L = MI->getOperand(0).getImm();
153
14
    if (!L || 
L == 110
||
L == 35
) {
154
14
      O << "\tdcbf";
155
14
      if (L == 1 || 
L == 39
)
156
10
        O << "l";
157
14
      if (L == 3)
158
5
        O << "p";
159
14
      O << " ";
160
14
161
14
      printOperand(MI, 1, O);
162
14
      O << ", ";
163
14
      printOperand(MI, 2, O);
164
14
165
14
      printAnnotation(O, Annot);
166
14
      return;
167
14
    }
168
109k
  }
169
109k
170
109k
  if (!printAliasInstr(MI, O))
171
100k
    printInstruction(MI, O);
172
109k
  printAnnotation(O, Annot);
173
109k
}
174
175
176
void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
177
                                           raw_ostream &O,
178
3.79k
                                           const char *Modifier) {
179
3.79k
  unsigned Code = MI->getOperand(OpNo).getImm();
180
3.79k
181
3.79k
  if (StringRef(Modifier) == "cc") {
182
1.26k
    switch ((PPC::Predicate)Code) {
183
1.26k
    case PPC::PRED_LT_MINUS:
184
27
    case PPC::PRED_LT_PLUS:
185
27
    case PPC::PRED_LT:
186
27
      O << "lt";
187
27
      return;
188
341
    case PPC::PRED_LE_MINUS:
189
341
    case PPC::PRED_LE_PLUS:
190
341
    case PPC::PRED_LE:
191
341
      O << "le";
192
341
      return;
193
341
    case PPC::PRED_EQ_MINUS:
194
70
    case PPC::PRED_EQ_PLUS:
195
70
    case PPC::PRED_EQ:
196
70
      O << "eq";
197
70
      return;
198
375
    case PPC::PRED_GE_MINUS:
199
375
    case PPC::PRED_GE_PLUS:
200
375
    case PPC::PRED_GE:
201
375
      O << "ge";
202
375
      return;
203
375
    case PPC::PRED_GT_MINUS:
204
27
    case PPC::PRED_GT_PLUS:
205
27
    case PPC::PRED_GT:
206
27
      O << "gt";
207
27
      return;
208
36
    case PPC::PRED_NE_MINUS:
209
36
    case PPC::PRED_NE_PLUS:
210
36
    case PPC::PRED_NE:
211
36
      O << "ne";
212
36
      return;
213
192
    case PPC::PRED_UN_MINUS:
214
192
    case PPC::PRED_UN_PLUS:
215
192
    case PPC::PRED_UN:
216
192
      O << "un";
217
192
      return;
218
196
    case PPC::PRED_NU_MINUS:
219
196
    case PPC::PRED_NU_PLUS:
220
196
    case PPC::PRED_NU:
221
196
      O << "nu";
222
196
      return;
223
196
    case PPC::PRED_BIT_SET:
224
0
    case PPC::PRED_BIT_UNSET:
225
0
      llvm_unreachable("Invalid use of bit predicate code");
226
0
    }
227
0
    llvm_unreachable("Invalid predicate code");
228
0
  }
229
2.52k
230
2.52k
  if (StringRef(Modifier) == "pm") {
231
1.26k
    switch ((PPC::Predicate)Code) {
232
1.26k
    case PPC::PRED_LT:
233
715
    case PPC::PRED_LE:
234
715
    case PPC::PRED_EQ:
235
715
    case PPC::PRED_GE:
236
715
    case PPC::PRED_GT:
237
715
    case PPC::PRED_NE:
238
715
    case PPC::PRED_UN:
239
715
    case PPC::PRED_NU:
240
715
      return;
241
715
    case PPC::PRED_LT_MINUS:
242
282
    case PPC::PRED_LE_MINUS:
243
282
    case PPC::PRED_EQ_MINUS:
244
282
    case PPC::PRED_GE_MINUS:
245
282
    case PPC::PRED_GT_MINUS:
246
282
    case PPC::PRED_NE_MINUS:
247
282
    case PPC::PRED_UN_MINUS:
248
282
    case PPC::PRED_NU_MINUS:
249
282
      O << "-";
250
282
      return;
251
282
    case PPC::PRED_LT_PLUS:
252
267
    case PPC::PRED_LE_PLUS:
253
267
    case PPC::PRED_EQ_PLUS:
254
267
    case PPC::PRED_GE_PLUS:
255
267
    case PPC::PRED_GT_PLUS:
256
267
    case PPC::PRED_NE_PLUS:
257
267
    case PPC::PRED_UN_PLUS:
258
267
    case PPC::PRED_NU_PLUS:
259
267
      O << "+";
260
267
      return;
261
267
    case PPC::PRED_BIT_SET:
262
0
    case PPC::PRED_BIT_UNSET:
263
0
      llvm_unreachable("Invalid use of bit predicate code");
264
0
    }
265
0
    llvm_unreachable("Invalid predicate code");
266
0
  }
267
1.26k
268
1.26k
  assert(StringRef(Modifier) == "reg" &&
269
1.26k
         "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
270
1.26k
  printOperand(MI, OpNo+1, O);
271
1.26k
}
272
273
void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
274
0
                                       raw_ostream &O) {
275
0
  unsigned Code = MI->getOperand(OpNo).getImm();
276
0
  if (Code == 2)
277
0
    O << "-";
278
0
  else if (Code == 3)
279
0
    O << "+";
280
0
}
281
282
void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
283
98
                                       raw_ostream &O) {
284
98
  unsigned int Value = MI->getOperand(OpNo).getImm();
285
98
  assert(Value <= 1 && "Invalid u1imm argument!");
286
98
  O << (unsigned int)Value;
287
98
}
288
289
void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
290
1.35k
                                       raw_ostream &O) {
291
1.35k
  unsigned int Value = MI->getOperand(OpNo).getImm();
292
1.35k
  assert(Value <= 3 && "Invalid u2imm argument!");
293
1.35k
  O << (unsigned int)Value;
294
1.35k
}
295
296
void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
297
3
                                       raw_ostream &O) {
298
3
  unsigned int Value = MI->getOperand(OpNo).getImm();
299
3
  assert(Value <= 8 && "Invalid u3imm argument!");
300
3
  O << (unsigned int)Value;
301
3
}
302
303
void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
304
988
                                       raw_ostream &O) {
305
988
  unsigned int Value = MI->getOperand(OpNo).getImm();
306
988
  assert(Value <= 15 && "Invalid u4imm argument!");
307
988
  O << (unsigned int)Value;
308
988
}
309
310
void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
311
246
                                       raw_ostream &O) {
312
246
  int Value = MI->getOperand(OpNo).getImm();
313
246
  Value = SignExtend32<5>(Value);
314
246
  O << (int)Value;
315
246
}
316
317
void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
318
3.19k
                                       raw_ostream &O) {
319
3.19k
  unsigned int Value = MI->getOperand(OpNo).getImm();
320
3.19k
  assert(Value <= 31 && "Invalid u5imm argument!");
321
3.19k
  O << (unsigned int)Value;
322
3.19k
}
323
324
void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
325
2.74k
                                       raw_ostream &O) {
326
2.74k
  unsigned int Value = MI->getOperand(OpNo).getImm();
327
2.74k
  assert(Value <= 63 && "Invalid u6imm argument!");
328
2.74k
  O << (unsigned int)Value;
329
2.74k
}
330
331
void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
332
28
                                       raw_ostream &O) {
333
28
  unsigned int Value = MI->getOperand(OpNo).getImm();
334
28
  assert(Value <= 127 && "Invalid u7imm argument!");
335
28
  O << (unsigned int)Value;
336
28
}
337
338
// Operands of BUILD_VECTOR are signed and we use this to print operands
339
// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
340
// print as unsigned.
341
void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
342
39
                                       raw_ostream &O) {
343
39
  unsigned char Value = MI->getOperand(OpNo).getImm();
344
39
  O << (unsigned int)Value;
345
39
}
346
347
void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
348
4
                                        raw_ostream &O) {
349
4
  unsigned short Value = MI->getOperand(OpNo).getImm();
350
4
  assert(Value <= 1023 && "Invalid u10imm argument!");
351
4
  O << (unsigned short)Value;
352
4
}
353
354
void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
355
41
                                        raw_ostream &O) {
356
41
  unsigned short Value = MI->getOperand(OpNo).getImm();
357
41
  assert(Value <= 4095 && "Invalid u12imm argument!");
358
41
  O << (unsigned short)Value;
359
41
}
360
361
void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
362
40.9k
                                        raw_ostream &O) {
363
40.9k
  if (MI->getOperand(OpNo).isImm())
364
29.9k
    O << (short)MI->getOperand(OpNo).getImm();
365
10.9k
  else
366
10.9k
    printOperand(MI, OpNo, O);
367
40.9k
}
368
369
void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
370
1.98k
                                        raw_ostream &O) {
371
1.98k
  if (MI->getOperand(OpNo).isImm())
372
1.98k
    O << (unsigned short)MI->getOperand(OpNo).getImm();
373
6
  else
374
6
    printOperand(MI, OpNo, O);
375
1.98k
}
376
377
void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
378
6.29k
                                        raw_ostream &O) {
379
6.29k
  if (!MI->getOperand(OpNo).isImm())
380
5.98k
    return printOperand(MI, OpNo, O);
381
304
382
304
  // Branches can take an immediate operand.  This is used by the branch
383
304
  // selection pass to print .+8, an eight byte displacement from the PC.
384
304
  O << ".";
385
304
  int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
386
304
  if (Imm >= 0)
387
255
    O << "+";
388
304
  O << Imm;
389
304
}
390
391
void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
392
376
                                           raw_ostream &O) {
393
376
  if (!MI->getOperand(OpNo).isImm())
394
364
    return printOperand(MI, OpNo, O);
395
12
396
12
  O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
397
12
}
398
399
400
void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
401
145
                                 raw_ostream &O) {
402
145
  unsigned CCReg = MI->getOperand(OpNo).getReg();
403
145
  unsigned RegNo;
404
145
  switch (CCReg) {
405
145
  
default: 0
llvm_unreachable0
("Unknown CR register");
406
145
  
case PPC::CR0: RegNo = 0; break27
;
407
145
  
case PPC::CR1: RegNo = 1; break1
;
408
145
  
case PPC::CR2: RegNo = 2; break33
;
409
145
  
case PPC::CR3: RegNo = 3; break24
;
410
145
  
case PPC::CR4: RegNo = 4; break24
;
411
145
  
case PPC::CR5: RegNo = 5; break14
;
412
145
  
case PPC::CR6: RegNo = 6; break7
;
413
145
  
case PPC::CR7: RegNo = 7; break15
;
414
145
  }
415
145
  O << (0x80 >> RegNo);
416
145
}
417
418
void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
419
22.6k
                                    raw_ostream &O) {
420
22.6k
  printS16ImmOperand(MI, OpNo, O);
421
22.6k
  O << '(';
422
22.6k
  if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
423
0
    O << "0";
424
22.6k
  else
425
22.6k
    printOperand(MI, OpNo+1, O);
426
22.6k
  O << ')';
427
22.6k
}
428
429
void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
430
7.33k
                                    raw_ostream &O) {
431
7.33k
  // When used as the base register, r0 reads constant zero rather than
432
7.33k
  // the value contained in the register.  For this reason, the darwin
433
7.33k
  // assembler requires that we print r0 as 0 (no r) when used as the base.
434
7.33k
  if (MI->getOperand(OpNo).getReg() == PPC::R0)
435
0
    O << "0";
436
7.33k
  else
437
7.33k
    printOperand(MI, OpNo, O);
438
7.33k
  O << ", ";
439
7.33k
  printOperand(MI, OpNo+1, O);
440
7.33k
}
441
442
void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
443
32
                                  raw_ostream &O) {
444
32
  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
445
32
  // come at the _end_ of the expression.
446
32
  const MCOperand &Op = MI->getOperand(OpNo);
447
32
  const MCSymbolRefExpr *RefExp = nullptr;
448
32
  const MCConstantExpr *ConstExp = nullptr;
449
32
  if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
450
1
    RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
451
1
    ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
452
1
  } else
453
31
    RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
454
32
455
32
  O << RefExp->getSymbol().getName();
456
32
  O << '(';
457
32
  printOperand(MI, OpNo+1, O);
458
32
  O << ')';
459
32
  if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
460
10
    O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
461
32
  if (ConstExp != nullptr)
462
1
    O << '+' << ConstExp->getValue();
463
32
}
464
465
/// showRegistersWithPercentPrefix - Check if this register name should be
466
/// printed with a percentage symbol as prefix.
467
202k
bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
468
202k
  if (!FullRegNamesWithPercent || 
TT.isOSDarwin()2
||
TT.getOS() == Triple::AIX2
)
469
202k
    return false;
470
2
471
2
  switch (RegName[0]) {
472
2
  default:
473
0
    return false;
474
2
  case 'r':
475
2
  case 'f':
476
2
  case 'q':
477
2
  case 'v':
478
2
  case 'c':
479
2
    return true;
480
2
  }
481
2
}
482
483
/// getVerboseConditionalRegName - This method expands the condition register
484
/// when requested explicitly or targetting Darwin.
485
const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
486
                                                       unsigned RegEncoding)
487
202k
                                                       const {
488
202k
  if (!TT.isOSDarwin() && 
!FullRegNames202k
)
489
139k
    return nullptr;
490
63.0k
  if (RegNum < PPC::CR0EQ || 
RegNum > PPC::CR7UN251
)
491
62.7k
    return nullptr;
492
251
  const char *CRBits[] = {
493
251
    "lt", "gt", "eq", "un",
494
251
    "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
495
251
    "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
496
251
    "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
497
251
    "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
498
251
    "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
499
251
    "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
500
251
    "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
501
251
  };
502
251
  return CRBits[RegEncoding];
503
251
}
504
505
// showRegistersWithPrefix - This method determines whether registers
506
// should be number-only or include the prefix.
507
202k
bool PPCInstPrinter::showRegistersWithPrefix() const {
508
202k
  if (TT.getOS() == Triple::AIX)
509
0
    return false;
510
202k
  return TT.isOSDarwin() || 
FullRegNamesWithPercent202k
||
FullRegNames202k
;
511
202k
}
512
513
void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
514
220k
                                  raw_ostream &O) {
515
220k
  const MCOperand &Op = MI->getOperand(OpNo);
516
220k
  if (Op.isReg()) {
517
202k
    unsigned Reg = Op.getReg();
518
202k
    if (!ShowVSRNumsAsVR)
519
156k
      Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
520
156k
                                              Reg, OpNo);
521
202k
522
202k
    const char *RegName;
523
202k
    RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
524
202k
    if (RegName == nullptr)
525
202k
     RegName = getRegisterName(Reg);
526
202k
    if (showRegistersWithPercentPrefix(RegName))
527
2
      O << "%";
528
202k
    if (!showRegistersWithPrefix())
529
139k
      RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
530
202k
531
202k
    O << RegName;
532
202k
    return;
533
202k
  }
534
17.7k
535
17.7k
  if (Op.isImm()) {
536
397
    O << Op.getImm();
537
397
    return;
538
397
  }
539
17.3k
540
17.3k
  assert(Op.isExpr() && "unknown operand kind in printOperand");
541
17.3k
  Op.getExpr()->print(O, &MAI);
542
17.3k
}
543