Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the PPCMCCodeEmitter class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "MCTargetDesc/PPCFixupKinds.h"
14
#include "PPCInstrInfo.h"
15
#include "PPCMCCodeEmitter.h"
16
#include "llvm/ADT/SmallVector.h"
17
#include "llvm/ADT/Statistic.h"
18
#include "llvm/ADT/Triple.h"
19
#include "llvm/MC/MCFixup.h"
20
#include "llvm/MC/MCInstrDesc.h"
21
#include "llvm/MC/MCRegisterInfo.h"
22
#include "llvm/Support/Endian.h"
23
#include "llvm/Support/EndianStream.h"
24
#include "llvm/Support/ErrorHandling.h"
25
#include "llvm/Support/MathExtras.h"
26
#include "llvm/Support/raw_ostream.h"
27
#include <cassert>
28
#include <cstdint>
29
30
using namespace llvm;
31
32
#define DEBUG_TYPE "mccodeemitter"
33
34
STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35
36
MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37
                                            const MCRegisterInfo &MRI,
38
285
                                            MCContext &Ctx) {
39
285
  return new PPCMCCodeEmitter(MCII, Ctx);
40
285
}
41
42
unsigned PPCMCCodeEmitter::
43
getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
44
                    SmallVectorImpl<MCFixup> &Fixups,
45
235
                    const MCSubtargetInfo &STI) const {
46
235
  const MCOperand &MO = MI.getOperand(OpNo);
47
235
  if (MO.isReg() || MO.isImm()) 
return getMachineOpValue(MI, MO, Fixups, STI)2
;
48
233
49
233
  // Add a fixup for the branch target.
50
233
  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
51
233
                                   (MCFixupKind)PPC::fixup_ppc_br24));
52
233
  return 0;
53
233
}
54
55
unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
56
                                     SmallVectorImpl<MCFixup> &Fixups,
57
406
                                     const MCSubtargetInfo &STI) const {
58
406
  const MCOperand &MO = MI.getOperand(OpNo);
59
406
  if (MO.isReg() || MO.isImm()) 
return getMachineOpValue(MI, MO, Fixups, STI)2
;
60
404
61
404
  // Add a fixup for the branch target.
62
404
  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
63
404
                                   (MCFixupKind)PPC::fixup_ppc_brcond14));
64
404
  return 0;
65
404
}
66
67
unsigned PPCMCCodeEmitter::
68
getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
69
                       SmallVectorImpl<MCFixup> &Fixups,
70
11
                       const MCSubtargetInfo &STI) const {
71
11
  const MCOperand &MO = MI.getOperand(OpNo);
72
11
  if (MO.isReg() || MO.isImm()) 
return getMachineOpValue(MI, MO, Fixups, STI)3
;
73
8
74
8
  // Add a fixup for the branch target.
75
8
  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
76
8
                                   (MCFixupKind)PPC::fixup_ppc_br24abs));
77
8
  return 0;
78
8
}
79
80
unsigned PPCMCCodeEmitter::
81
getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
82
                     SmallVectorImpl<MCFixup> &Fixups,
83
370
                     const MCSubtargetInfo &STI) const {
84
370
  const MCOperand &MO = MI.getOperand(OpNo);
85
370
  if (MO.isReg() || MO.isImm()) 
return getMachineOpValue(MI, MO, Fixups, STI)2
;
86
368
87
368
  // Add a fixup for the branch target.
88
368
  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
89
368
                                   (MCFixupKind)PPC::fixup_ppc_brcond14abs));
90
368
  return 0;
91
368
}
92
93
unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
94
                                       SmallVectorImpl<MCFixup> &Fixups,
95
1.30k
                                       const MCSubtargetInfo &STI) const {
96
1.30k
  const MCOperand &MO = MI.getOperand(OpNo);
97
1.30k
  if (MO.isReg() || MO.isImm()) 
return getMachineOpValue(MI, MO, Fixups, STI)439
;
98
869
99
869
  // Add a fixup for the immediate field.
100
869
  Fixups.push_back(MCFixup::create(IsLittleEndian? 
0443
:
2426
, MO.getExpr(),
101
869
                                   (MCFixupKind)PPC::fixup_ppc_half16));
102
869
  return 0;
103
869
}
104
105
unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
106
                                            SmallVectorImpl<MCFixup> &Fixups,
107
234
                                            const MCSubtargetInfo &STI) const {
108
234
  // Encode (imm, reg) as a memri, which has the low 16-bits as the
109
234
  // displacement and the next 5 bits as the register #.
110
234
  assert(MI.getOperand(OpNo+1).isReg());
111
234
  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
112
234
113
234
  const MCOperand &MO = MI.getOperand(OpNo);
114
234
  if (MO.isImm())
115
189
    return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
116
45
117
45
  // Add a fixup for the displacement field.
118
45
  Fixups.push_back(MCFixup::create(IsLittleEndian? 
019
:
226
, MO.getExpr(),
119
45
                                   (MCFixupKind)PPC::fixup_ppc_half16));
120
45
  return RegBits;
121
45
}
122
123
unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
124
                                       SmallVectorImpl<MCFixup> &Fixups,
125
577
                                       const MCSubtargetInfo &STI) const {
126
577
  // Encode (imm, reg) as a memrix, which has the low 14-bits as the
127
577
  // displacement and the next 5 bits as the register #.
128
577
  assert(MI.getOperand(OpNo+1).isReg());
129
577
  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
130
577
131
577
  const MCOperand &MO = MI.getOperand(OpNo);
132
577
  if (MO.isImm())
133
392
    return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
134
185
135
185
  // Add a fixup for the displacement field.
136
185
  Fixups.push_back(MCFixup::create(IsLittleEndian? 
090
:
295
, MO.getExpr(),
137
185
                                   (MCFixupKind)PPC::fixup_ppc_half16ds));
138
185
  return RegBits;
139
185
}
140
141
unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
142
                                       SmallVectorImpl<MCFixup> &Fixups,
143
18
                                       const MCSubtargetInfo &STI) const {
144
18
  // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
145
18
  // displacement and the next 5 bits as the register #.
146
18
  assert(MI.getOperand(OpNo+1).isReg());
147
18
  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
148
18
149
18
  const MCOperand &MO = MI.getOperand(OpNo);
150
18
  if (MO.isImm()) {
151
8
    assert(!(MO.getImm() % 16) &&
152
8
           "Expecting an immediate that is a multiple of 16");
153
8
    return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
154
8
  }
155
10
156
10
  // Otherwise add a fixup for the displacement field.
157
10
  Fixups.push_back(MCFixup::create(IsLittleEndian? 
07
:
23
, MO.getExpr(),
158
10
                                   (MCFixupKind)PPC::fixup_ppc_half16ds));
159
10
  return RegBits;
160
10
}
161
162
unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
163
                                              SmallVectorImpl<MCFixup> &Fixups,
164
                                              const MCSubtargetInfo &STI)
165
36
                                              const {
166
36
  // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
167
36
  // as the displacement and the next 5 bits as the register #.
168
36
  assert(MI.getOperand(OpNo+1).isReg());
169
36
  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
170
36
171
36
  const MCOperand &MO = MI.getOperand(OpNo);
172
36
  assert(MO.isImm());
173
36
  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
174
36
  return reverseBits(Imm | RegBits) >> 22;
175
36
}
176
177
unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
178
                                              SmallVectorImpl<MCFixup> &Fixups,
179
                                              const MCSubtargetInfo &STI)
180
54
                                              const {
181
54
  // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
182
54
  // as the displacement and the next 5 bits as the register #.
183
54
  assert(MI.getOperand(OpNo+1).isReg());
184
54
  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
185
54
186
54
  const MCOperand &MO = MI.getOperand(OpNo);
187
54
  assert(MO.isImm());
188
54
  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
189
54
  return reverseBits(Imm | RegBits) >> 22;
190
54
}
191
192
unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
193
                                              SmallVectorImpl<MCFixup> &Fixups,
194
                                              const MCSubtargetInfo &STI)
195
14
                                              const {
196
14
  // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
197
14
  // as the displacement and the next 5 bits as the register #.
198
14
  assert(MI.getOperand(OpNo+1).isReg());
199
14
  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
200
14
201
14
  const MCOperand &MO = MI.getOperand(OpNo);
202
14
  assert(MO.isImm());
203
14
  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
204
14
  return reverseBits(Imm | RegBits) >> 22;
205
14
}
206
207
unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
208
                                       SmallVectorImpl<MCFixup> &Fixups,
209
40
                                       const MCSubtargetInfo &STI) const {
210
40
  const MCOperand &MO = MI.getOperand(OpNo);
211
40
  if (MO.isReg()) 
return getMachineOpValue(MI, MO, Fixups, STI)0
;
212
40
213
40
  // Add a fixup for the TLS register, which simply provides a relocation
214
40
  // hint to the linker that this statement is part of a relocation sequence.
215
40
  // Return the thread-pointer register's encoding.
216
40
  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
217
40
                                   (MCFixupKind)PPC::fixup_ppc_nofixup));
218
40
  const Triple &TT = STI.getTargetTriple();
219
40
  bool isPPC64 = TT.isPPC64();
220
40
  return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? 
PPC::X1333
:
PPC::R27
);
221
40
}
222
223
unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
224
                                       SmallVectorImpl<MCFixup> &Fixups,
225
39
                                       const MCSubtargetInfo &STI) const {
226
39
  // For special TLS calls, we need two fixups; one for the branch target
227
39
  // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
228
39
  // and one for the TLSGD or TLSLD symbol, which is emitted here.
229
39
  const MCOperand &MO = MI.getOperand(OpNo+1);
230
39
  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
231
39
                                   (MCFixupKind)PPC::fixup_ppc_nofixup));
232
39
  return getDirectBrEncoding(MI, OpNo, Fixups, STI);
233
39
}
234
235
unsigned PPCMCCodeEmitter::
236
get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
237
                    SmallVectorImpl<MCFixup> &Fixups,
238
7
                    const MCSubtargetInfo &STI) const {
239
7
  const MCOperand &MO = MI.getOperand(OpNo);
240
7
  assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
241
7
          MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
242
7
         (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
243
7
  return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
244
7
}
245
246
// Get the index for this operand in this instruction. This is needed for
247
// computing the register number in PPCInstrInfo::getRegNumForOperand() for
248
// any instructions that use a different numbering scheme for registers in
249
// different operands.
250
13.9k
static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
251
26.0k
  for (unsigned i = 0; i < MI.getNumOperands(); 
i++12.0k
) {
252
26.0k
    const MCOperand &Op = MI.getOperand(i);
253
26.0k
    if (&Op == &MO)
254
13.9k
      return i;
255
26.0k
  }
256
13.9k
  
llvm_unreachable0
("This operand is not part of this instruction");
257
13.9k
  
return ~0U0
; // Silence any warnings about no return.
258
13.9k
}
259
260
unsigned PPCMCCodeEmitter::
261
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
262
                  SmallVectorImpl<MCFixup> &Fixups,
263
17.9k
                  const MCSubtargetInfo &STI) const {
264
17.9k
  if (MO.isReg()) {
265
13.9k
    // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
266
13.9k
    // The GPR operand should come through here though.
267
13.9k
    assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
268
13.9k
            MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
269
13.9k
           MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
270
13.9k
    unsigned OpNo = getOpIdxForMO(MI, MO);
271
13.9k
    unsigned Reg =
272
13.9k
      PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
273
13.9k
                                        MO.getReg(), OpNo);
274
13.9k
    return CTX.getRegisterInfo()->getEncodingValue(Reg);
275
13.9k
  }
276
4.06k
277
4.06k
  assert(MO.isImm() &&
278
4.06k
         "Relocation required in an instruction that we cannot encode!");
279
4.06k
  return MO.getImm();
280
4.06k
}
281
282
void PPCMCCodeEmitter::encodeInstruction(
283
    const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
284
8.01k
    const MCSubtargetInfo &STI) const {
285
8.01k
  verifyInstructionPredicates(MI,
286
8.01k
                              computeAvailableFeatures(STI.getFeatureBits()));
287
8.01k
288
8.01k
  uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
289
8.01k
290
8.01k
  // Output the constant in big/little endian byte order.
291
8.01k
  unsigned Size = getInstSizeInBytes(MI);
292
8.01k
  support::endianness E = IsLittleEndian ? 
support::little3.85k
:
support::big4.15k
;
293
8.01k
  switch (Size) {
294
8.01k
  case 0:
295
1
    break;
296
8.01k
  case 4:
297
8.00k
    support::endian::write<uint32_t>(OS, Bits, E);
298
8.00k
    break;
299
8.01k
  case 8:
300
3
    // If we emit a pair of instructions, the first one is
301
3
    // always in the top 32 bits, even on little-endian.
302
3
    support::endian::write<uint32_t>(OS, Bits >> 32, E);
303
3
    support::endian::write<uint32_t>(OS, Bits, E);
304
3
    break;
305
8.01k
  default:
306
0
    llvm_unreachable("Invalid instruction size");
307
8.01k
  }
308
8.01k
309
8.01k
  ++MCNumEmitted; // Keep track of the # of mi's emitted.
310
8.01k
}
311
312
// Get the number of bytes used to encode the given MCInst.
313
8.01k
unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
314
8.01k
  unsigned Opcode = MI.getOpcode();
315
8.01k
  const MCInstrDesc &Desc = MCII.get(Opcode);
316
8.01k
  return Desc.getSize();
317
8.01k
}
318
319
#define ENABLE_INSTR_PREDICATE_VERIFIER
320
#include "PPCGenMCCodeEmitter.inc"