Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp
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Source (jump to first uncovered line)
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//===------------- PPCExpandISEL.cpp - Expand ISEL instruction ------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// A pass that expands the ISEL instruction into an if-then-else sequence.
10
// This pass must be run post-RA since all operands must be physical registers.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "PPC.h"
15
#include "PPCInstrInfo.h"
16
#include "PPCSubtarget.h"
17
#include "llvm/ADT/DenseMap.h"
18
#include "llvm/ADT/Statistic.h"
19
#include "llvm/CodeGen/LivePhysRegs.h"
20
#include "llvm/CodeGen/MachineFunctionPass.h"
21
#include "llvm/CodeGen/MachineInstrBuilder.h"
22
#include "llvm/CodeGen/MachineRegisterInfo.h"
23
#include "llvm/Support/CommandLine.h"
24
#include "llvm/Support/Debug.h"
25
#include "llvm/Support/raw_ostream.h"
26
27
using namespace llvm;
28
29
#define DEBUG_TYPE "ppc-expand-isel"
30
31
STATISTIC(NumExpanded, "Number of ISEL instructions expanded");
32
STATISTIC(NumRemoved, "Number of ISEL instructions removed");
33
STATISTIC(NumFolded, "Number of ISEL instructions folded");
34
35
// If -ppc-gen-isel=false is set, we will disable generating the ISEL
36
// instruction on all PPC targets. Otherwise, if the user set option
37
// -misel or the platform supports ISEL by default, still generate the
38
// ISEL instruction, else expand it.
39
static cl::opt<bool>
40
    GenerateISEL("ppc-gen-isel",
41
                 cl::desc("Enable generating the ISEL instruction."),
42
                 cl::init(true), cl::Hidden);
43
44
namespace {
45
class PPCExpandISEL : public MachineFunctionPass {
46
  DebugLoc dl;
47
  MachineFunction *MF;
48
  const TargetInstrInfo *TII;
49
  bool IsTrueBlockRequired;
50
  bool IsFalseBlockRequired;
51
  MachineBasicBlock *TrueBlock;
52
  MachineBasicBlock *FalseBlock;
53
  MachineBasicBlock *NewSuccessor;
54
  MachineBasicBlock::iterator TrueBlockI;
55
  MachineBasicBlock::iterator FalseBlockI;
56
57
  typedef SmallVector<MachineInstr *, 4> BlockISELList;
58
  typedef SmallDenseMap<int, BlockISELList> ISELInstructionList;
59
60
  // A map of MBB numbers to their lists of contained ISEL instructions.
61
  // Please note when we traverse this list and expand ISEL, we only remove
62
  // the ISEL from the MBB not from this list.
63
  ISELInstructionList ISELInstructions;
64
65
  /// Initialize the object.
66
  void initialize(MachineFunction &MFParam);
67
68
  void handleSpecialCases(BlockISELList &BIL, MachineBasicBlock *MBB);
69
  void reorganizeBlockLayout(BlockISELList &BIL, MachineBasicBlock *MBB);
70
  void populateBlocks(BlockISELList &BIL);
71
  void expandMergeableISELs(BlockISELList &BIL);
72
  void expandAndMergeISELs();
73
74
  bool canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI);
75
76
  ///  Is this instruction an ISEL or ISEL8?
77
103k
  static bool isISEL(const MachineInstr &MI) {
78
103k
    return (MI.getOpcode() == PPC::ISEL || 
MI.getOpcode() == PPC::ISEL8103k
);
79
103k
  }
80
81
  ///  Is this instruction an ISEL8?
82
308
  static bool isISEL8(const MachineInstr &MI) {
83
308
    return (MI.getOpcode() == PPC::ISEL8);
84
308
  }
85
86
  /// Are the two operands using the same register?
87
2.47k
  bool useSameRegister(const MachineOperand &Op1, const MachineOperand &Op2) {
88
2.47k
    return (Op1.getReg() == Op2.getReg());
89
2.47k
  }
90
91
  ///
92
  ///  Collect all ISEL instructions from the current function.
93
  ///
94
  /// Walk the current function and collect all the ISEL instructions that are
95
  /// found. The instructions are placed in the ISELInstructions vector.
96
  ///
97
  /// \return true if any ISEL instructions were found, false otherwise
98
  ///
99
  bool collectISELInstructions();
100
101
public:
102
  static char ID;
103
1.81k
  PPCExpandISEL() : MachineFunctionPass(ID) {
104
1.81k
    initializePPCExpandISELPass(*PassRegistry::getPassRegistry());
105
1.81k
  }
106
107
  ///
108
  ///  Determine whether to generate the ISEL instruction or expand it.
109
  ///
110
  /// Expand ISEL instruction into if-then-else sequence when one of
111
  /// the following two conditions hold:
112
  /// (1) -ppc-gen-isel=false
113
  /// (2) hasISEL() return false
114
  /// Otherwise, still generate ISEL instruction.
115
  /// The -ppc-gen-isel option is set to true by default. Which means the ISEL
116
  /// instruction is still generated by default on targets that support them.
117
  ///
118
  /// \return true if ISEL should be expanded into if-then-else code sequence;
119
  ///         false if ISEL instruction should be generated, i.e. not expanded.
120
  ///
121
  static bool isExpandISELEnabled(const MachineFunction &MF);
122
123
#ifndef NDEBUG
124
  void DumpISELInstructions() const;
125
#endif
126
127
11.2k
  bool runOnMachineFunction(MachineFunction &MF) override {
128
11.2k
    LLVM_DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n");
129
11.2k
    initialize(MF);
130
11.2k
131
11.2k
    if (!collectISELInstructions()) {
132
10.8k
      LLVM_DEBUG(dbgs() << "No ISEL instructions in this function\n");
133
10.8k
      return false;
134
10.8k
    }
135
446
136
#ifndef NDEBUG
137
    DumpISELInstructions();
138
#endif
139
140
446
    expandAndMergeISELs();
141
446
142
446
    return true;
143
446
  }
144
};
145
} // end anonymous namespace
146
147
11.2k
void PPCExpandISEL::initialize(MachineFunction &MFParam) {
148
11.2k
  MF = &MFParam;
149
11.2k
  TII = MF->getSubtarget().getInstrInfo();
150
11.2k
  ISELInstructions.clear();
151
11.2k
}
152
153
446
bool PPCExpandISEL::isExpandISELEnabled(const MachineFunction &MF) {
154
446
  return !GenerateISEL || 
!MF.getSubtarget<PPCSubtarget>().hasISEL()376
;
155
446
}
156
157
11.2k
bool PPCExpandISEL::collectISELInstructions() {
158
16.4k
  for (MachineBasicBlock &MBB : *MF) {
159
16.4k
    BlockISELList thisBlockISELs;
160
16.4k
    for (MachineInstr &MI : MBB)
161
103k
      if (isISEL(MI))
162
585
        thisBlockISELs.push_back(&MI);
163
16.4k
    if (!thisBlockISELs.empty())
164
497
      ISELInstructions.insert(std::make_pair(MBB.getNumber(), thisBlockISELs));
165
16.4k
  }
166
11.2k
  return !ISELInstructions.empty();
167
11.2k
}
168
169
#ifndef NDEBUG
170
void PPCExpandISEL::DumpISELInstructions() const {
171
  for (const auto &I : ISELInstructions) {
172
    LLVM_DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first))
173
                      << ":\n");
174
    for (const auto &VI : I.second)
175
      LLVM_DEBUG(dbgs() << "    "; VI->print(dbgs()));
176
  }
177
}
178
#endif
179
180
/// Contiguous ISELs that have the same condition can be merged.
181
36
bool PPCExpandISEL::canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI) {
182
36
  // Same Condition Register?
183
36
  if (!useSameRegister(PrevPushedMI->getOperand(3), MI->getOperand(3)))
184
8
    return false;
185
28
186
28
  MachineBasicBlock::iterator PrevPushedMBBI = *PrevPushedMI;
187
28
  MachineBasicBlock::iterator MBBI = *MI;
188
28
  return (std::prev(MBBI) == PrevPushedMBBI); // Contiguous ISELs?
189
28
}
190
191
446
void PPCExpandISEL::expandAndMergeISELs() {
192
446
  bool ExpandISELEnabled = isExpandISELEnabled(*MF);
193
446
194
497
  for (auto &BlockList : ISELInstructions) {
195
497
    LLVM_DEBUG(
196
497
        dbgs() << "Expanding ISEL instructions in "
197
497
               << printMBBReference(*MF->getBlockNumbered(BlockList.first))
198
497
               << "\n");
199
497
    BlockISELList &CurrentISELList = BlockList.second;
200
497
    auto I = CurrentISELList.begin();
201
497
    auto E = CurrentISELList.end();
202
497
203
1.06k
    while (I != E) {
204
569
      assert(isISEL(**I) && "Expecting an ISEL instruction");
205
569
      MachineOperand &Dest = (*I)->getOperand(0);
206
569
      MachineOperand &TrueValue = (*I)->getOperand(1);
207
569
      MachineOperand &FalseValue = (*I)->getOperand(2);
208
569
209
569
      // Special case 1, all registers used by ISEL are the same one.
210
569
      // The non-redundant isel 0, 0, 0, N would not satisfy these conditions
211
569
      // as it would be ISEL %R0, %ZERO, %R0, %CRN.
212
569
      if (useSameRegister(Dest, TrueValue) &&
213
569
          
useSameRegister(Dest, FalseValue)146
) {
214
4
        LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction: " << **I
215
4
                          << "\n");
216
4
        // FIXME: if the CR field used has no other uses, we could eliminate the
217
4
        // instruction that defines it. This would have to be done manually
218
4
        // since this pass runs too late to run DCE after it.
219
4
        NumRemoved++;
220
4
        (*I)->eraseFromParent();
221
4
        I++;
222
565
      } else if (useSameRegister(TrueValue, FalseValue)) {
223
3
        // Special case 2, the two input registers used by ISEL are the same.
224
3
        // Note: the non-foldable isel RX, 0, 0, N would not satisfy this
225
3
        // condition as it would be ISEL %RX, %ZERO, %R0, %CRN, which makes it
226
3
        // safe to fold ISEL to MR(OR) instead of ADDI.
227
3
        MachineBasicBlock *MBB = (*I)->getParent();
228
3
        LLVM_DEBUG(
229
3
            dbgs() << "Fold the ISEL instruction to an unconditional copy:\n");
230
3
        LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
231
3
        NumFolded++;
232
3
        // Note: we're using both the TrueValue and FalseValue operands so as
233
3
        // not to lose the kill flag if it is set on either of them.
234
3
        BuildMI(*MBB, (*I), dl, TII->get(isISEL8(**I) ? 
PPC::OR82
:
PPC::OR1
))
235
3
            .add(Dest)
236
3
            .add(TrueValue)
237
3
            .add(FalseValue);
238
3
        (*I)->eraseFromParent();
239
3
        I++;
240
562
      } else if (ExpandISELEnabled) { // Normal cases expansion enabled
241
215
        LLVM_DEBUG(dbgs() << "Expand ISEL instructions:\n");
242
215
        LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
243
215
        BlockISELList SubISELList;
244
215
        SubISELList.push_back(*I++);
245
215
        // Collect the ISELs that can be merged together.
246
215
        // This will eat up ISEL instructions without considering whether they
247
215
        // may be redundant or foldable to a register copy. So we still keep
248
215
        // the handleSpecialCases() downstream to handle them.
249
231
        while (I != E && 
canMerge(SubISELList.back(), *I)36
) {
250
16
          LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
251
16
          SubISELList.push_back(*I++);
252
16
        }
253
215
254
215
        expandMergeableISELs(SubISELList);
255
347
      } else { // Normal cases expansion disabled
256
347
        I++; // leave the ISEL as it is
257
347
      }
258
569
    } // end while
259
497
  } // end for
260
446
}
261
262
void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
263
215
                                       MachineBasicBlock *MBB) {
264
215
  IsTrueBlockRequired = false;
265
215
  IsFalseBlockRequired = false;
266
215
267
215
  auto MI = BIL.begin();
268
446
  while (MI != BIL.end()) {
269
231
    assert(isISEL(**MI) && "Expecting an ISEL instruction");
270
231
    LLVM_DEBUG(dbgs() << "ISEL: " << **MI << "\n");
271
231
272
231
    MachineOperand &Dest = (*MI)->getOperand(0);
273
231
    MachineOperand &TrueValue = (*MI)->getOperand(1);
274
231
    MachineOperand &FalseValue = (*MI)->getOperand(2);
275
231
276
231
    // If at least one of the ISEL instructions satisfy the following
277
231
    // condition, we need the True Block:
278
231
    // The Dest Register and True Value Register are not the same
279
231
    // Similarly, if at least one of the ISEL instructions satisfy the
280
231
    // following condition, we need the False Block:
281
231
    // The Dest Register and False Value Register are not the same.
282
231
    bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
283
231
    bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
284
231
285
231
    // Special case 1, all registers used by ISEL are the same one.
286
231
    if (!IsADDIInstRequired && 
!IsORIInstRequired58
) {
287
0
      LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction.");
288
0
      // FIXME: if the CR field used has no other uses, we could eliminate the
289
0
      // instruction that defines it. This would have to be done manually
290
0
      // since this pass runs too late to run DCE after it.
291
0
      NumRemoved++;
292
0
      (*MI)->eraseFromParent();
293
0
      // Setting MI to the erase result keeps the iterator valid and increased.
294
0
      MI = BIL.erase(MI);
295
0
      continue;
296
0
    }
297
231
298
231
    // Special case 2, the two input registers used by ISEL are the same.
299
231
    // Note 1: We favor merging ISEL expansions over folding a single one. If
300
231
    // the passed list has multiple merge-able ISEL's, we won't fold any.
301
231
    // Note 2: There is no need to test for PPC::R0/PPC::X0 because PPC::ZERO/
302
231
    // PPC::ZERO8 will be used for the first operand if the value is meant to
303
231
    // be zero. In this case, the useSameRegister method will return false,
304
231
    // thereby preventing this ISEL from being folded.
305
231
    if (useSameRegister(TrueValue, FalseValue) && 
(BIL.size() == 1)0
) {
306
0
      LLVM_DEBUG(
307
0
          dbgs() << "Fold the ISEL instruction to an unconditional copy.");
308
0
      NumFolded++;
309
0
      // Note: we're using both the TrueValue and FalseValue operands so as
310
0
      // not to lose the kill flag if it is set on either of them.
311
0
      BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::OR8 : PPC::OR))
312
0
          .add(Dest)
313
0
          .add(TrueValue)
314
0
          .add(FalseValue);
315
0
      (*MI)->eraseFromParent();
316
0
      // Setting MI to the erase result keeps the iterator valid and increased.
317
0
      MI = BIL.erase(MI);
318
0
      continue;
319
0
    }
320
231
321
231
    IsTrueBlockRequired |= IsADDIInstRequired;
322
231
    IsFalseBlockRequired |= IsORIInstRequired;
323
231
    MI++;
324
231
  }
325
215
}
326
327
void PPCExpandISEL::reorganizeBlockLayout(BlockISELList &BIL,
328
215
                                          MachineBasicBlock *MBB) {
329
215
  if (BIL.empty())
330
0
    return;
331
215
332
215
  assert((IsTrueBlockRequired || IsFalseBlockRequired) &&
333
215
         "Should have been handled by special cases earlier!");
334
215
335
215
  MachineBasicBlock *Successor = nullptr;
336
215
  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
337
215
  MachineBasicBlock::iterator MBBI = (*BIL.back());
338
215
  NewSuccessor = (MBBI != MBB->getLastNonDebugInstr() || 
!MBB->canFallThrough()4
)
339
215
                     // Another BB is needed to move the instructions that
340
215
                     // follow this ISEL.  If the ISEL is the last instruction
341
215
                     // in a block that can't fall through, we also need a block
342
215
                     // to branch to.
343
215
                     ? 
MF->CreateMachineBasicBlock(LLVM_BB)212
344
215
                     : 
nullptr3
;
345
215
346
215
  MachineFunction::iterator It = MBB->getIterator();
347
215
  ++It; // Point to the successor block of MBB.
348
215
349
215
  // If NewSuccessor is NULL then the last ISEL in this group is the last
350
215
  // non-debug instruction in this block. Find the fall-through successor
351
215
  // of this block to use when updating the CFG below.
352
215
  if (!NewSuccessor) {
353
3
    for (auto &Succ : MBB->successors()) {
354
3
      if (MBB->isLayoutSuccessor(Succ)) {
355
3
        Successor = Succ;
356
3
        break;
357
3
      }
358
3
    }
359
3
  } else
360
212
    Successor = NewSuccessor;
361
215
362
215
  // The FalseBlock and TrueBlock are inserted after the MBB block but before
363
215
  // its successor.
364
215
  // Note this need to be done *after* the above setting the Successor code.
365
215
  if (IsFalseBlockRequired) {
366
124
    FalseBlock = MF->CreateMachineBasicBlock(LLVM_BB);
367
124
    MF->insert(It, FalseBlock);
368
124
  }
369
215
370
215
  if (IsTrueBlockRequired) {
371
167
    TrueBlock = MF->CreateMachineBasicBlock(LLVM_BB);
372
167
    MF->insert(It, TrueBlock);
373
167
  }
374
215
375
215
  if (NewSuccessor) {
376
212
    MF->insert(It, NewSuccessor);
377
212
378
212
    // Transfer the rest of this block into the new successor block.
379
212
    NewSuccessor->splice(NewSuccessor->end(), MBB,
380
212
                         std::next(MachineBasicBlock::iterator(BIL.back())),
381
212
                         MBB->end());
382
212
    NewSuccessor->transferSuccessorsAndUpdatePHIs(MBB);
383
212
384
212
    // Copy the original liveIns of MBB to NewSuccessor.
385
212
    for (auto &LI : MBB->liveins())
386
2.01k
      NewSuccessor->addLiveIn(LI);
387
212
388
212
    // After splitting the NewSuccessor block, Regs defined but not killed
389
212
    // in MBB should be treated as liveins of NewSuccessor.
390
212
    // Note: Cannot use stepBackward instead since we are using the Reg
391
212
    // liveness state at the end of MBB (liveOut of MBB) as the liveIn for
392
212
    // NewSuccessor. Otherwise, will cause cyclic dependence.
393
212
    LivePhysRegs LPR(*MF->getSubtarget<PPCSubtarget>().getRegisterInfo());
394
212
    SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 2> Clobbers;
395
212
    for (MachineInstr &MI : *MBB)
396
1.48k
      LPR.stepForward(MI, Clobbers);
397
212
    for (auto &LI : LPR)
398
1.82k
      NewSuccessor->addLiveIn(LI);
399
212
  } else {
400
3
    // Remove successor from MBB.
401
3
    MBB->removeSuccessor(Successor);
402
3
  }
403
215
404
215
  // Note that this needs to be done *after* transfering the successors from MBB
405
215
  // to the NewSuccessor block, otherwise these blocks will also be transferred
406
215
  // as successors!
407
215
  MBB->addSuccessor(IsTrueBlockRequired ? 
TrueBlock167
:
Successor48
);
408
215
  MBB->addSuccessor(IsFalseBlockRequired ? 
FalseBlock124
:
Successor91
);
409
215
410
215
  if (IsTrueBlockRequired) {
411
167
    TrueBlockI = TrueBlock->begin();
412
167
    TrueBlock->addSuccessor(Successor);
413
167
  }
414
215
415
215
  if (IsFalseBlockRequired) {
416
124
    FalseBlockI = FalseBlock->begin();
417
124
    FalseBlock->addSuccessor(Successor);
418
124
  }
419
215
420
215
  // Conditional branch to the TrueBlock or Successor
421
215
  BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC))
422
215
      .add(BIL.back()->getOperand(3))
423
215
      .addMBB(IsTrueBlockRequired ? 
TrueBlock167
:
Successor48
);
424
215
425
215
  // Jump over the true block to the new successor if the condition is false.
426
215
  BuildMI(*(IsFalseBlockRequired ? 
FalseBlock124
:
MBB91
),
427
215
          (IsFalseBlockRequired ? 
FalseBlockI124
:
BIL.back()91
), dl,
428
215
          TII->get(PPC::B))
429
215
      .addMBB(Successor);
430
215
431
215
  if (IsFalseBlockRequired)
432
124
    FalseBlockI = FalseBlock->begin(); // get the position of PPC::B
433
215
}
434
435
215
void PPCExpandISEL::populateBlocks(BlockISELList &BIL) {
436
231
  for (auto &MI : BIL) {
437
231
    assert(isISEL(*MI) && "Expecting an ISEL instruction");
438
231
439
231
    MachineOperand &Dest = MI->getOperand(0);       // location to store to
440
231
    MachineOperand &TrueValue = MI->getOperand(1);  // Value to store if
441
231
                                                       // condition is true
442
231
    MachineOperand &FalseValue = MI->getOperand(2); // Value to store if
443
231
                                                       // condition is false
444
231
    MachineOperand &ConditionRegister = MI->getOperand(3); // Condition
445
231
446
231
    LLVM_DEBUG(dbgs() << "Dest: " << Dest << "\n");
447
231
    LLVM_DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n");
448
231
    LLVM_DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n");
449
231
    LLVM_DEBUG(dbgs() << "ConditionRegister: " << ConditionRegister << "\n");
450
231
451
231
    // If the Dest Register and True Value Register are not the same one, we
452
231
    // need the True Block.
453
231
    bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
454
231
    bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
455
231
456
231
    if (IsADDIInstRequired) {
457
173
      // Copy the result into the destination if the condition is true.
458
173
      BuildMI(*TrueBlock, TrueBlockI, dl,
459
173
              TII->get(isISEL8(*MI) ? 
PPC::ADDI865
:
PPC::ADDI108
))
460
173
          .add(Dest)
461
173
          .add(TrueValue)
462
173
          .add(MachineOperand::CreateImm(0));
463
173
464
173
      // Add the LiveIn registers required by true block.
465
173
      TrueBlock->addLiveIn(TrueValue.getReg());
466
173
    }
467
231
468
231
    if (IsORIInstRequired) {
469
132
      // Add the LiveIn registers required by false block.
470
132
      FalseBlock->addLiveIn(FalseValue.getReg());
471
132
    }
472
231
473
231
    if (NewSuccessor) {
474
228
      // Add the LiveIn registers required by NewSuccessor block.
475
228
      NewSuccessor->addLiveIn(Dest.getReg());
476
228
      NewSuccessor->addLiveIn(TrueValue.getReg());
477
228
      NewSuccessor->addLiveIn(FalseValue.getReg());
478
228
      NewSuccessor->addLiveIn(ConditionRegister.getReg());
479
228
    }
480
231
481
231
    // Copy the value into the destination if the condition is false.
482
231
    if (IsORIInstRequired)
483
132
      BuildMI(*FalseBlock, FalseBlockI, dl,
484
132
              TII->get(isISEL8(*MI) ? 
PPC::ORI856
:
PPC::ORI76
))
485
132
          .add(Dest)
486
132
          .add(FalseValue)
487
132
          .add(MachineOperand::CreateImm(0));
488
231
489
231
    MI->eraseFromParent(); // Remove the ISEL instruction.
490
231
491
231
    NumExpanded++;
492
231
  }
493
215
}
494
495
215
void PPCExpandISEL::expandMergeableISELs(BlockISELList &BIL) {
496
215
  // At this stage all the ISELs of BIL are in the same MBB.
497
215
  MachineBasicBlock *MBB = BIL.back()->getParent();
498
215
499
215
  handleSpecialCases(BIL, MBB);
500
215
  reorganizeBlockLayout(BIL, MBB);
501
215
  populateBlocks(BIL);
502
215
}
503
504
INITIALIZE_PASS(PPCExpandISEL, DEBUG_TYPE, "PowerPC Expand ISEL Generation",
505
                false, false)
506
char PPCExpandISEL::ID = 0;
507
508
1.80k
FunctionPass *llvm::createPPCExpandISELPass() { return new PPCExpandISEL(); }