Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCFastISel.cpp
Line
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Source (jump to first uncovered line)
1
//===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file defines the PowerPC-specific support for the FastISel class. Some
10
// of the target-specific code is generated by tablegen in the file
11
// PPCGenFastISel.inc, which is #included here.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "MCTargetDesc/PPCPredicates.h"
16
#include "PPC.h"
17
#include "PPCCCState.h"
18
#include "PPCCallingConv.h"
19
#include "PPCISelLowering.h"
20
#include "PPCMachineFunctionInfo.h"
21
#include "PPCSubtarget.h"
22
#include "PPCTargetMachine.h"
23
#include "llvm/ADT/Optional.h"
24
#include "llvm/CodeGen/CallingConvLower.h"
25
#include "llvm/CodeGen/FastISel.h"
26
#include "llvm/CodeGen/FunctionLoweringInfo.h"
27
#include "llvm/CodeGen/MachineConstantPool.h"
28
#include "llvm/CodeGen/MachineFrameInfo.h"
29
#include "llvm/CodeGen/MachineInstrBuilder.h"
30
#include "llvm/CodeGen/MachineRegisterInfo.h"
31
#include "llvm/CodeGen/TargetLowering.h"
32
#include "llvm/IR/CallingConv.h"
33
#include "llvm/IR/GetElementPtrTypeIterator.h"
34
#include "llvm/IR/GlobalAlias.h"
35
#include "llvm/IR/GlobalVariable.h"
36
#include "llvm/IR/IntrinsicInst.h"
37
#include "llvm/IR/Operator.h"
38
#include "llvm/Support/Debug.h"
39
#include "llvm/Target/TargetMachine.h"
40
41
//===----------------------------------------------------------------------===//
42
//
43
// TBD:
44
//   fastLowerArguments: Handle simple cases.
45
//   PPCMaterializeGV: Handle TLS.
46
//   SelectCall: Handle function pointers.
47
//   SelectCall: Handle multi-register return values.
48
//   SelectCall: Optimize away nops for local calls.
49
//   processCallArgs: Handle bit-converted arguments.
50
//   finishCall: Handle multi-register return values.
51
//   PPCComputeAddress: Handle parameter references as FrameIndex's.
52
//   PPCEmitCmp: Handle immediate as operand 1.
53
//   SelectCall: Handle small byval arguments.
54
//   SelectIntrinsicCall: Implement.
55
//   SelectSelect: Implement.
56
//   Consider factoring isTypeLegal into the base class.
57
//   Implement switches and jump tables.
58
//
59
//===----------------------------------------------------------------------===//
60
using namespace llvm;
61
62
#define DEBUG_TYPE "ppcfastisel"
63
64
namespace {
65
66
typedef struct Address {
67
  enum {
68
    RegBase,
69
    FrameIndexBase
70
  } BaseType;
71
72
  union {
73
    unsigned Reg;
74
    int FI;
75
  } Base;
76
77
  long Offset;
78
79
  // Innocuous defaults for our address.
80
  Address()
81
346
   : BaseType(RegBase), Offset(0) {
82
346
     Base.Reg = 0;
83
346
   }
84
} Address;
85
86
class PPCFastISel final : public FastISel {
87
88
  const TargetMachine &TM;
89
  const PPCSubtarget *PPCSubTarget;
90
  PPCFunctionInfo *PPCFuncInfo;
91
  const TargetInstrInfo &TII;
92
  const TargetLowering &TLI;
93
  LLVMContext *Context;
94
95
  public:
96
    explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
97
                         const TargetLibraryInfo *LibInfo)
98
        : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
99
          PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
100
          PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
101
          TII(*PPCSubTarget->getInstrInfo()),
102
          TLI(*PPCSubTarget->getTargetLowering()),
103
692
          Context(&FuncInfo.Fn->getContext()) {}
104
105
  // Backend specific FastISel code.
106
  private:
107
    bool fastSelectInstruction(const Instruction *I) override;
108
    unsigned fastMaterializeConstant(const Constant *C) override;
109
    unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
110
    bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
111
                             const LoadInst *LI) override;
112
    bool fastLowerArguments() override;
113
    unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114
    unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
115
                             const TargetRegisterClass *RC,
116
                             unsigned Op0, bool Op0IsKill,
117
                             uint64_t Imm);
118
    unsigned fastEmitInst_r(unsigned MachineInstOpcode,
119
                            const TargetRegisterClass *RC,
120
                            unsigned Op0, bool Op0IsKill);
121
    unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
122
                             const TargetRegisterClass *RC,
123
                             unsigned Op0, bool Op0IsKill,
124
                             unsigned Op1, bool Op1IsKill);
125
126
    bool fastLowerCall(CallLoweringInfo &CLI) override;
127
128
  // Instruction selection routines.
129
  private:
130
    bool SelectLoad(const Instruction *I);
131
    bool SelectStore(const Instruction *I);
132
    bool SelectBranch(const Instruction *I);
133
    bool SelectIndirectBr(const Instruction *I);
134
    bool SelectFPExt(const Instruction *I);
135
    bool SelectFPTrunc(const Instruction *I);
136
    bool SelectIToFP(const Instruction *I, bool IsSigned);
137
    bool SelectFPToI(const Instruction *I, bool IsSigned);
138
    bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
139
    bool SelectRet(const Instruction *I);
140
    bool SelectTrunc(const Instruction *I);
141
    bool SelectIntExt(const Instruction *I);
142
143
  // Utility routines.
144
  private:
145
    bool isTypeLegal(Type *Ty, MVT &VT);
146
    bool isLoadTypeLegal(Type *Ty, MVT &VT);
147
    bool isValueAvailable(const Value *V) const;
148
414
    bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
149
414
      return RC->getID() == PPC::VSFRCRegClassID;
150
414
    }
151
373
    bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
152
373
      return RC->getID() == PPC::VSSRCRegClassID;
153
373
    }
154
    unsigned copyRegToRegClass(const TargetRegisterClass *ToRC,
155
                               unsigned SrcReg, unsigned Flag = 0,
156
44
                               unsigned SubReg = 0) {
157
44
      unsigned TmpReg = createResultReg(ToRC);
158
44
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
159
44
              TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
160
44
      return TmpReg;
161
44
    }
162
    bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
163
                    bool isZExt, unsigned DestReg,
164
                    const PPC::Predicate Pred);
165
    bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
166
                     const TargetRegisterClass *RC, bool IsZExt = true,
167
                     unsigned FP64LoadOpc = PPC::LFD);
168
    bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
169
    bool PPCComputeAddress(const Value *Obj, Address &Addr);
170
    void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
171
                            unsigned &IndexReg);
172
    bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
173
                           unsigned DestReg, bool IsZExt);
174
    unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
175
    unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
176
    unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
177
                               bool UseSExt = true);
178
    unsigned PPCMaterialize32BitInt(int64_t Imm,
179
                                    const TargetRegisterClass *RC);
180
    unsigned PPCMaterialize64BitInt(int64_t Imm,
181
                                    const TargetRegisterClass *RC);
182
    unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
183
                             unsigned SrcReg, bool IsSigned);
184
    unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
185
186
  // Call handling routines.
187
  private:
188
    bool processCallArgs(SmallVectorImpl<Value*> &Args,
189
                         SmallVectorImpl<unsigned> &ArgRegs,
190
                         SmallVectorImpl<MVT> &ArgVTs,
191
                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
192
                         SmallVectorImpl<unsigned> &RegArgs,
193
                         CallingConv::ID CC,
194
                         unsigned &NumBytes,
195
                         bool IsVarArg);
196
    bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
197
198
  private:
199
  #include "PPCGenFastISel.inc"
200
201
};
202
203
} // end anonymous namespace
204
205
65
static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
206
65
  switch (Pred) {
207
65
    // These are not representable with any single compare.
208
65
    case CmpInst::FCMP_FALSE:
209
6
    case CmpInst::FCMP_TRUE:
210
6
    // Major concern about the following 6 cases is NaN result. The comparison
211
6
    // result consists of 4 bits, indicating lt, eq, gt and un (unordered),
212
6
    // only one of which will be set. The result is generated by fcmpu
213
6
    // instruction. However, bc instruction only inspects one of the first 3
214
6
    // bits, so when un is set, bc instruction may jump to an undesired
215
6
    // place.
216
6
    //
217
6
    // More specifically, if we expect an unordered comparison and un is set, we
218
6
    // expect to always go to true branch; in such case UEQ, UGT and ULT still
219
6
    // give false, which are undesired; but UNE, UGE, ULE happen to give true,
220
6
    // since they are tested by inspecting !eq, !lt, !gt, respectively.
221
6
    //
222
6
    // Similarly, for ordered comparison, when un is set, we always expect the
223
6
    // result to be false. In such case OGT, OLT and OEQ is good, since they are
224
6
    // actually testing GT, LT, and EQ respectively, which are false. OGE, OLE
225
6
    // and ONE are tested through !lt, !gt and !eq, and these are true.
226
6
    case CmpInst::FCMP_UEQ:
227
6
    case CmpInst::FCMP_UGT:
228
6
    case CmpInst::FCMP_ULT:
229
6
    case CmpInst::FCMP_OGE:
230
6
    case CmpInst::FCMP_OLE:
231
6
    case CmpInst::FCMP_ONE:
232
6
    default:
233
6
      return Optional<PPC::Predicate>();
234
6
235
46
    case CmpInst::FCMP_OEQ:
236
46
    case CmpInst::ICMP_EQ:
237
46
      return PPC::PRED_EQ;
238
46
239
46
    case CmpInst::FCMP_OGT:
240
4
    case CmpInst::ICMP_UGT:
241
4
    case CmpInst::ICMP_SGT:
242
4
      return PPC::PRED_GT;
243
4
244
4
    case CmpInst::FCMP_UGE:
245
1
    case CmpInst::ICMP_UGE:
246
1
    case CmpInst::ICMP_SGE:
247
1
      return PPC::PRED_GE;
248
1
249
5
    case CmpInst::FCMP_OLT:
250
5
    case CmpInst::ICMP_ULT:
251
5
    case CmpInst::ICMP_SLT:
252
5
      return PPC::PRED_LT;
253
5
254
5
    case CmpInst::FCMP_ULE:
255
1
    case CmpInst::ICMP_ULE:
256
1
    case CmpInst::ICMP_SLE:
257
1
      return PPC::PRED_LE;
258
1
259
2
    case CmpInst::FCMP_UNE:
260
2
    case CmpInst::ICMP_NE:
261
2
      return PPC::PRED_NE;
262
2
263
2
    case CmpInst::FCMP_ORD:
264
0
      return PPC::PRED_NU;
265
2
266
2
    case CmpInst::FCMP_UNO:
267
0
      return PPC::PRED_UN;
268
65
  }
269
65
}
270
271
// Determine whether the type Ty is simple enough to be handled by
272
// fast-isel, and return its equivalent machine type in VT.
273
// FIXME: Copied directly from ARM -- factor into base class?
274
574
bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
275
574
  EVT Evt = TLI.getValueType(DL, Ty, true);
276
574
277
574
  // Only handle simple types.
278
574
  if (Evt == MVT::Other || !Evt.isSimple()) 
return false0
;
279
574
  VT = Evt.getSimpleVT();
280
574
281
574
  // Handle all legal types, i.e. a register that will directly hold this
282
574
  // value.
283
574
  return TLI.isTypeLegal(VT);
284
574
}
285
286
// Determine whether the type Ty is simple enough to be handled by
287
// fast-isel as a load target, and return its equivalent machine type in VT.
288
321
bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
289
321
  if (isTypeLegal(Ty, VT)) 
return true285
;
290
36
291
36
  // If this is a type than can be sign or zero-extended to a basic operation
292
36
  // go ahead and accept it now.
293
36
  if (VT == MVT::i8 || 
VT == MVT::i1615
||
VT == MVT::i320
) {
294
36
    return true;
295
36
  }
296
0
297
0
  return false;
298
0
}
299
300
67
bool PPCFastISel::isValueAvailable(const Value *V) const {
301
67
  if (!isa<Instruction>(V))
302
0
    return true;
303
67
304
67
  const auto *I = cast<Instruction>(V);
305
67
  return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
306
67
}
307
308
// Given a value Obj, create an Address object Addr that represents its
309
// address.  Return false if we can't handle it.
310
294
bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
311
294
  const User *U = nullptr;
312
294
  unsigned Opcode = Instruction::UserOp1;
313
294
  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
314
163
    // Don't walk into other basic blocks unless the object is an alloca from
315
163
    // another block, otherwise it may not have a virtual register assigned.
316
163
    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
317
163
        
FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB20
) {
318
163
      Opcode = I->getOpcode();
319
163
      U = I;
320
163
    }
321
163
  } else 
if (const ConstantExpr *131
C131
= dyn_cast<ConstantExpr>(Obj)) {
322
9
    Opcode = C->getOpcode();
323
9
    U = C;
324
9
  }
325
294
326
294
  switch (Opcode) {
327
294
    default:
328
127
      break;
329
294
    case Instruction::BitCast:
330
1
      // Look through bitcasts.
331
1
      return PPCComputeAddress(U->getOperand(0), Addr);
332
294
    case Instruction::IntToPtr:
333
4
      // Look past no-op inttoptrs.
334
4
      if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
335
4
          TLI.getPointerTy(DL))
336
4
        return PPCComputeAddress(U->getOperand(0), Addr);
337
0
      break;
338
0
    case Instruction::PtrToInt:
339
0
      // Look past no-op ptrtoints.
340
0
      if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
341
0
        return PPCComputeAddress(U->getOperand(0), Addr);
342
0
      break;
343
19
    case Instruction::GetElementPtr: {
344
19
      Address SavedAddr = Addr;
345
19
      long TmpOffset = Addr.Offset;
346
19
347
19
      // Iterate through the GEP folding the constants into offsets where
348
19
      // we can.
349
19
      gep_type_iterator GTI = gep_type_begin(U);
350
19
      for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
351
53
           II != IE; 
++II, ++GTI34
) {
352
36
        const Value *Op = *II;
353
36
        if (StructType *STy = GTI.getStructTypeOrNull()) {
354
11
          const StructLayout *SL = DL.getStructLayout(STy);
355
11
          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
356
11
          TmpOffset += SL->getElementOffset(Idx);
357
25
        } else {
358
25
          uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
359
25
          for (;;) {
360
25
            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
361
23
              // Constant-offset addressing.
362
23
              TmpOffset += CI->getSExtValue() * S;
363
23
              break;
364
23
            }
365
2
            if (canFoldAddIntoGEP(U, Op)) {
366
0
              // A compatible add with a constant operand. Fold the constant.
367
0
              ConstantInt *CI =
368
0
              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
369
0
              TmpOffset += CI->getSExtValue() * S;
370
0
              // Iterate on the other operand.
371
0
              Op = cast<AddOperator>(Op)->getOperand(0);
372
0
              continue;
373
0
            }
374
2
            // Unsupported
375
2
            goto unsupported_gep;
376
2
          }
377
25
        }
378
36
      }
379
19
380
19
      // Try to grab the base operand now.
381
19
      Addr.Offset = TmpOffset;
382
17
      if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
383
0
384
0
      // We failed, restore everything and try the other options.
385
0
      Addr = SavedAddr;
386
0
387
2
      unsupported_gep:
388
2
      break;
389
0
    }
390
143
    case Instruction::Alloca: {
391
143
      const AllocaInst *AI = cast<AllocaInst>(Obj);
392
143
      DenseMap<const AllocaInst*, int>::iterator SI =
393
143
        FuncInfo.StaticAllocaMap.find(AI);
394
143
      if (SI != FuncInfo.StaticAllocaMap.end()) {
395
143
        Addr.BaseType = Address::FrameIndexBase;
396
143
        Addr.Base.FI = SI->second;
397
143
        return true;
398
143
      }
399
0
      break;
400
0
    }
401
129
  }
402
129
403
129
  // FIXME: References to parameters fall through to the behavior
404
129
  // below.  They should be able to reference a frame index since
405
129
  // they are stored to the stack, so we can get "ld rx, offset(r1)"
406
129
  // instead of "addi ry, r1, offset / ld rx, 0(ry)".  Obj will
407
129
  // just contain the parameter.  Try to handle this with a FI.
408
129
409
129
  // Try to get this in a register if nothing else has worked.
410
129
  if (Addr.Base.Reg == 0)
411
129
    Addr.Base.Reg = getRegForValue(Obj);
412
129
413
129
  // Prevent assignment of base register to X0, which is inappropriate
414
129
  // for loads and stores alike.
415
129
  if (Addr.Base.Reg != 0)
416
121
    MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
417
129
418
129
  return Addr.Base.Reg != 0;
419
129
}
420
421
// Fix up some addresses that can't be used directly.  For example, if
422
// an offset won't fit in an instruction field, we may need to move it
423
// into an index register.
424
void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
425
361
                                     unsigned &IndexReg) {
426
361
427
361
  // Check whether the offset fits in the instruction field.
428
361
  if (!isInt<16>(Addr.Offset))
429
3
    UseOffset = false;
430
361
431
361
  // If this is a stack pointer and the offset needs to be simplified then
432
361
  // put the alloca address into a register, set the base type back to
433
361
  // register and continue. This should almost never happen.
434
361
  if (!UseOffset && 
Addr.BaseType == Address::FrameIndexBase6
) {
435
0
    unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
436
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
437
0
            ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
438
0
    Addr.Base.Reg = ResultReg;
439
0
    Addr.BaseType = Address::RegBase;
440
0
  }
441
361
442
361
  if (!UseOffset) {
443
6
    IntegerType *OffsetTy = Type::getInt64Ty(*Context);
444
6
    const ConstantInt *Offset =
445
6
      ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
446
6
    IndexReg = PPCMaterializeInt(Offset, MVT::i64);
447
6
    assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
448
6
  }
449
361
}
450
451
// Emit a load instruction if possible, returning true if we succeeded,
452
// otherwise false.  See commentary below for how the register class of
453
// the load is determined.
454
bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
455
                              const TargetRegisterClass *RC,
456
162
                              bool IsZExt, unsigned FP64LoadOpc) {
457
162
  unsigned Opc;
458
162
  bool UseOffset = true;
459
162
  bool HasSPE = PPCSubTarget->hasSPE();
460
162
461
162
  // If ResultReg is given, it determines the register class of the load.
462
162
  // Otherwise, RC is the register class to use.  If the result of the
463
162
  // load isn't anticipated in this block, both may be zero, in which
464
162
  // case we must make a conservative guess.  In particular, don't assign
465
162
  // R0 or X0 to the result register, as the result may be used in a load,
466
162
  // store, add-immediate, or isel that won't permit this.  (Though
467
162
  // perhaps the spill and reload of live-exit values would handle this?)
468
162
  const TargetRegisterClass *UseRC =
469
162
    (ResultReg ? 
MRI.getRegClass(ResultReg)20
:
470
162
     
(RC 142
?
RC142
:
471
142
      
(VT == MVT::f64 0
?
(HasSPE 0
?
&PPC::SPERCRegClass0
:
&PPC::F8RCRegClass0
) :
472
0
       (VT == MVT::f32 ? (HasSPE ? &PPC::SPE4RCRegClass : &PPC::F4RCRegClass) :
473
0
        (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
474
0
         &PPC::GPRC_and_GPRC_NOR0RegClass)))));
475
162
476
162
  bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
477
162
478
162
  switch (VT.SimpleTy) {
479
162
    default: // e.g., vector types not handled
480
20
      return false;
481
162
    case MVT::i8:
482
9
      Opc = Is32BitInt ? 
PPC::LBZ6
:
PPC::LBZ83
;
483
9
      break;
484
162
    case MVT::i16:
485
6
      Opc = (IsZExt ? 
(Is32BitInt 4
?
PPC::LHZ2
:
PPC::LHZ82
)
486
6
                    : 
(Is32BitInt 2
?
PPC::LHA1
:
PPC::LHA81
));
487
6
      break;
488
162
    case MVT::i32:
489
53
      Opc = (IsZExt ? 
(Is32BitInt 40
?
PPC::LWZ31
:
PPC::LWZ89
)
490
53
                    : 
(Is32BitInt 13
?
PPC::LWA_3211
:
PPC::LWA2
));
491
53
      if ((Opc == PPC::LWA || 
Opc == PPC::LWA_3251
) &&
((Addr.Offset & 3) != 0)13
)
492
1
        UseOffset = false;
493
53
      break;
494
162
    case MVT::i64:
495
27
      Opc = PPC::LD;
496
27
      assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
497
27
             "64-bit load with 32-bit target??");
498
27
      UseOffset = ((Addr.Offset & 3) == 0);
499
27
      break;
500
162
    case MVT::f32:
501
4
      Opc = PPCSubTarget->hasSPE() ? 
PPC::SPELWZ0
: PPC::LFS;
502
4
      break;
503
162
    case MVT::f64:
504
43
      Opc = FP64LoadOpc;
505
43
      break;
506
142
  }
507
142
508
142
  // If necessary, materialize the offset into a register and use
509
142
  // the indexed form.  Also handle stack pointers with special needs.
510
142
  unsigned IndexReg = 0;
511
142
  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
512
142
513
142
  // If this is a potential VSX load with an offset of 0, a VSX indexed load can
514
142
  // be used.
515
142
  bool IsVSSRC = isVSSRCRegClass(UseRC);
516
142
  bool IsVSFRC = isVSFRCRegClass(UseRC);
517
142
  bool Is32VSXLoad = IsVSSRC && 
Opc == PPC::LFS0
;
518
142
  bool Is64VSXLoad = IsVSFRC && 
Opc == PPC::LFD2
;
519
142
  if ((Is32VSXLoad || Is64VSXLoad) &&
520
142
      
(Addr.BaseType != Address::FrameIndexBase)2
&&
UseOffset1
&&
521
142
      
(Addr.Offset == 0)1
) {
522
1
    UseOffset = false;
523
1
  }
524
142
525
142
  if (ResultReg == 0)
526
122
    ResultReg = createResultReg(UseRC);
527
142
528
142
  // Note: If we still have a frame index here, we know the offset is
529
142
  // in range, as otherwise PPCSimplifyAddress would have converted it
530
142
  // into a RegBase.
531
142
  if (Addr.BaseType == Address::FrameIndexBase) {
532
89
    // VSX only provides an indexed load.
533
89
    if (Is32VSXLoad || Is64VSXLoad) 
return false1
;
534
88
535
88
    MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
536
88
        MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
537
88
                                          Addr.Offset),
538
88
        MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
539
88
        MFI.getObjectAlignment(Addr.Base.FI));
540
88
541
88
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
542
88
      .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
543
88
544
88
  // Base reg with offset in range.
545
88
  } else 
if (53
UseOffset53
) {
546
49
    // VSX only provides an indexed load.
547
49
    if (Is32VSXLoad || Is64VSXLoad) 
return false0
;
548
49
549
49
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
550
49
      .addImm(Addr.Offset).addReg(Addr.Base.Reg);
551
49
552
49
  // Indexed form.
553
49
  } else {
554
4
    // Get the RR opcode corresponding to the RI one.  FIXME: It would be
555
4
    // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
556
4
    // is hard to get at.
557
4
    switch (Opc) {
558
4
      
default: 0
llvm_unreachable0
("Unexpected opcode!");
559
4
      
case PPC::LBZ: Opc = PPC::LBZX; break0
;
560
4
      
case PPC::LBZ8: Opc = PPC::LBZX8; break0
;
561
4
      
case PPC::LHZ: Opc = PPC::LHZX; break0
;
562
4
      
case PPC::LHZ8: Opc = PPC::LHZX8; break0
;
563
4
      
case PPC::LHA: Opc = PPC::LHAX; break0
;
564
4
      
case PPC::LHA8: Opc = PPC::LHAX8; break0
;
565
4
      
case PPC::LWZ: Opc = PPC::LWZX; break0
;
566
4
      
case PPC::LWZ8: Opc = PPC::LWZX8; break0
;
567
4
      
case PPC::LWA: Opc = PPC::LWAX; break1
;
568
4
      
case PPC::LWA_32: Opc = PPC::LWAX_32; break0
;
569
4
      
case PPC::LD: Opc = PPC::LDX; break2
;
570
4
      
case PPC::LFS: Opc = IsVSSRC 0
?
PPC::LXSSPX0
:
PPC::LFSX0
; break;
571
4
      
case PPC::LFD: Opc = IsVSFRC 1
?
PPC::LXSDX1
:
PPC::LFDX0
; break;
572
4
      
case PPC::EVLDD: Opc = PPC::EVLDDX; break0
;
573
4
      
case PPC::SPELWZ: Opc = PPC::SPELWZX; break0
;
574
4
    }
575
4
576
4
    auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
577
4
                       ResultReg);
578
4
579
4
    // If we have an index register defined we use it in the store inst,
580
4
    // otherwise we use X0 as base as it makes the vector instructions to
581
4
    // use zero in the computation of the effective address regardless the
582
4
    // content of the register.
583
4
    if (IndexReg)
584
3
      MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
585
1
    else
586
1
      MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
587
4
  }
588
142
589
142
  
return true141
;
590
142
}
591
592
// Attempt to fast-select a load instruction.
593
73
bool PPCFastISel::SelectLoad(const Instruction *I) {
594
73
  // FIXME: No atomic loads are supported.
595
73
  if (cast<LoadInst>(I)->isAtomic())
596
0
    return false;
597
73
598
73
  // Verify we have a legal type before going any further.
599
73
  MVT VT;
600
73
  if (!isLoadTypeLegal(I->getType(), VT))
601
0
    return false;
602
73
603
73
  // See if we can handle this address.
604
73
  Address Addr;
605
73
  if (!PPCComputeAddress(I->getOperand(0), Addr))
606
3
    return false;
607
70
608
70
  // Look at the currently assigned register for this instruction
609
70
  // to determine the required register class.  This is necessary
610
70
  // to constrain RA from using R0/X0 when this is not legal.
611
70
  unsigned AssignedReg = FuncInfo.ValueMap[I];
612
70
  const TargetRegisterClass *RC =
613
70
    AssignedReg ? MRI.getRegClass(AssignedReg) : 
nullptr0
;
614
70
615
70
  unsigned ResultReg = 0;
616
70
  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
617
70
      PPCSubTarget->hasSPE() ? 
PPC::EVLDD0
: PPC::LFD))
618
21
    return false;
619
49
  updateValueMap(I, ResultReg);
620
49
  return true;
621
49
}
622
623
// Emit a store instruction to store SrcReg at Addr.
624
248
bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
625
248
  assert(SrcReg && "Nothing to store!");
626
248
  unsigned Opc;
627
248
  bool UseOffset = true;
628
248
629
248
  const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
630
248
  bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
631
248
632
248
  switch (VT.SimpleTy) {
633
248
    default: // e.g., vector types not handled
634
29
      return false;
635
248
    case MVT::i8:
636
7
      Opc = Is32BitInt ? PPC::STB : 
PPC::STB80
;
637
7
      break;
638
248
    case MVT::i16:
639
8
      Opc = Is32BitInt ? PPC::STH : 
PPC::STH80
;
640
8
      break;
641
248
    case MVT::i32:
642
44
      assert(Is32BitInt && "Not GPRC for i32??");
643
44
      Opc = PPC::STW;
644
44
      break;
645
248
    case MVT::i64:
646
68
      Opc = PPC::STD;
647
68
      UseOffset = ((Addr.Offset & 3) == 0);
648
68
      break;
649
248
    case MVT::f32:
650
28
      Opc = PPCSubTarget->hasSPE() ? 
PPC::SPESTW0
: PPC::STFS;
651
28
      break;
652
248
    case MVT::f64:
653
64
      Opc = PPCSubTarget->hasSPE() ? 
PPC::EVSTDD0
: PPC::STFD;
654
64
      break;
655
219
  }
656
219
657
219
  // If necessary, materialize the offset into a register and use
658
219
  // the indexed form.  Also handle stack pointers with special needs.
659
219
  unsigned IndexReg = 0;
660
219
  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
661
219
662
219
  // If this is a potential VSX store with an offset of 0, a VSX indexed store
663
219
  // can be used.
664
219
  bool IsVSSRC = isVSSRCRegClass(RC);
665
219
  bool IsVSFRC = isVSFRCRegClass(RC);
666
219
  bool Is32VSXStore = IsVSSRC && 
Opc == PPC::STFS0
;
667
219
  bool Is64VSXStore = IsVSFRC && 
Opc == PPC::STFD3
;
668
219
  if ((Is32VSXStore || Is64VSXStore) &&
669
219
      
(Addr.BaseType != Address::FrameIndexBase)3
&&
UseOffset1
&&
670
219
      
(Addr.Offset == 0)1
) {
671
1
    UseOffset = false;
672
1
  }
673
219
674
219
  // Note: If we still have a frame index here, we know the offset is
675
219
  // in range, as otherwise PPCSimplifyAddress would have converted it
676
219
  // into a RegBase.
677
219
  if (Addr.BaseType == Address::FrameIndexBase) {
678
187
    // VSX only provides an indexed store.
679
187
    if (Is32VSXStore || Is64VSXStore) 
return false2
;
680
185
681
185
    MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
682
185
        MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
683
185
                                          Addr.Offset),
684
185
        MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
685
185
        MFI.getObjectAlignment(Addr.Base.FI));
686
185
687
185
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
688
185
        .addReg(SrcReg)
689
185
        .addImm(Addr.Offset)
690
185
        .addFrameIndex(Addr.Base.FI)
691
185
        .addMemOperand(MMO);
692
185
693
185
  // Base reg with offset in range.
694
185
  } else 
if (32
UseOffset32
) {
695
28
    // VSX only provides an indexed store.
696
28
    if (Is32VSXStore || Is64VSXStore)
697
0
      return false;
698
28
699
28
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
700
28
      .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
701
28
702
28
  // Indexed form.
703
28
  } else {
704
4
    // Get the RR opcode corresponding to the RI one.  FIXME: It would be
705
4
    // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
706
4
    // is hard to get at.
707
4
    switch (Opc) {
708
4
      
default: 0
llvm_unreachable0
("Unexpected opcode!");
709
4
      
case PPC::STB: Opc = PPC::STBX; break0
;
710
4
      
case PPC::STH : Opc = PPC::STHX; break0
;
711
4
      
case PPC::STW : Opc = PPC::STWX; break1
;
712
4
      
case PPC::STB8: Opc = PPC::STBX8; break0
;
713
4
      
case PPC::STH8: Opc = PPC::STHX8; break0
;
714
4
      
case PPC::STW8: Opc = PPC::STWX8; break0
;
715
4
      
case PPC::STD: Opc = PPC::STDX; break2
;
716
4
      
case PPC::STFS: Opc = IsVSSRC 0
?
PPC::STXSSPX0
:
PPC::STFSX0
; break;
717
4
      
case PPC::STFD: Opc = IsVSFRC 1
?
PPC::STXSDX1
:
PPC::STFDX0
; break;
718
4
      
case PPC::EVSTDD: Opc = PPC::EVSTDDX; break0
;
719
4
      
case PPC::SPESTW: Opc = PPC::SPESTWX; break0
;
720
4
    }
721
4
722
4
    auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
723
4
        .addReg(SrcReg);
724
4
725
4
    // If we have an index register defined we use it in the store inst,
726
4
    // otherwise we use X0 as base as it makes the vector instructions to
727
4
    // use zero in the computation of the effective address regardless the
728
4
    // content of the register.
729
4
    if (IndexReg)
730
3
      MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
731
1
    else
732
1
      MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
733
4
  }
734
219
735
219
  
return true217
;
736
219
}
737
738
// Attempt to fast-select a store instruction.
739
177
bool PPCFastISel::SelectStore(const Instruction *I) {
740
177
  Value *Op0 = I->getOperand(0);
741
177
  unsigned SrcReg = 0;
742
177
743
177
  // FIXME: No atomics loads are supported.
744
177
  if (cast<StoreInst>(I)->isAtomic())
745
1
    return false;
746
176
747
176
  // Verify we have a legal type before going any further.
748
176
  MVT VT;
749
176
  if (!isLoadTypeLegal(Op0->getType(), VT))
750
0
    return false;
751
176
752
176
  // Get the value to be stored into a register.
753
176
  SrcReg = getRegForValue(Op0);
754
176
  if (SrcReg == 0)
755
0
    return false;
756
176
757
176
  // See if we can handle this address.
758
176
  Address Addr;
759
176
  if (!PPCComputeAddress(I->getOperand(1), Addr))
760
2
    return false;
761
174
762
174
  if (!PPCEmitStore(VT, SrcReg, Addr))
763
29
    return false;
764
145
765
145
  return true;
766
145
}
767
768
// Attempt to fast-select a branch instruction.
769
84
bool PPCFastISel::SelectBranch(const Instruction *I) {
770
84
  const BranchInst *BI = cast<BranchInst>(I);
771
84
  MachineBasicBlock *BrBB = FuncInfo.MBB;
772
84
  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
773
84
  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
774
84
775
84
  // For now, just try the simplest case where it's fed by a compare.
776
84
  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
777
67
    if (isValueAvailable(CI)) {
778
65
      Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
779
65
      if (!OptPPCPred)
780
6
        return false;
781
59
782
59
      PPC::Predicate PPCPred = OptPPCPred.getValue();
783
59
784
59
      // Take advantage of fall-through opportunities.
785
59
      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
786
51
        std::swap(TBB, FBB);
787
51
        PPCPred = PPC::InvertPredicate(PPCPred);
788
51
      }
789
59
790
59
      unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
791
59
792
59
      if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
793
59
                      CondReg, PPCPred))
794
0
        return false;
795
59
796
59
      BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
797
59
        .addImm(PPCSubTarget->hasSPE() ? 
PPC::PRED_SPE0
: PPCPred)
798
59
        .addReg(CondReg).addMBB(TBB);
799
59
      finishCondBranch(BI->getParent(), TBB, FBB);
800
59
      return true;
801
59
    }
802
17
  } else if (const ConstantInt *CI =
803
5
             dyn_cast<ConstantInt>(BI->getCondition())) {
804
5
    uint64_t Imm = CI->getZExtValue();
805
5
    MachineBasicBlock *Target = (Imm == 0) ? 
FBB3
:
TBB2
;
806
5
    fastEmitBranch(Target, DbgLoc);
807
5
    return true;
808
5
  }
809
14
810
14
  // FIXME: ARM looks for a case where the block containing the compare
811
14
  // has been split from the block containing the branch.  If this happens,
812
14
  // there is a vreg available containing the result of the compare.  I'm
813
14
  // not sure we can do much, as we've lost the predicate information with
814
14
  // the compare instruction -- we have a 4-bit CR but don't know which bit
815
14
  // to test here.
816
14
  return false;
817
14
}
818
819
// Attempt to emit a compare of the two source values.  Signed and unsigned
820
// comparisons are supported.  Return false if we can't handle it.
821
bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
822
                             bool IsZExt, unsigned DestReg,
823
59
                             const PPC::Predicate Pred) {
824
59
  Type *Ty = SrcValue1->getType();
825
59
  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
826
59
  if (!SrcEVT.isSimple())
827
0
    return false;
828
59
  MVT SrcVT = SrcEVT.getSimpleVT();
829
59
830
59
  if (SrcVT == MVT::i1 && 
PPCSubTarget->useCRBits()0
)
831
0
    return false;
832
59
833
59
  // See if operand 2 is an immediate encodeable in the compare.
834
59
  // FIXME: Operands are not in canonical order at -O0, so an immediate
835
59
  // operand in position 1 is a lost opportunity for now.  We are
836
59
  // similar to ARM in this regard.
837
59
  long Imm = 0;
838
59
  bool UseImm = false;
839
59
  const bool HasSPE = PPCSubTarget->hasSPE();
840
59
841
59
  // Only 16-bit integer constants can be represented in compares for
842
59
  // PowerPC.  Others will be materialized into a register.
843
59
  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
844
32
    if (SrcVT == MVT::i64 || 
SrcVT == MVT::i3223
||
SrcVT == MVT::i1611
||
845
32
        
SrcVT == MVT::i87
||
SrcVT == MVT::i10
) {
846
32
      const APInt &CIVal = ConstInt->getValue();
847
32
      Imm = (IsZExt) ? 
(long)CIVal.getZExtValue()2
:
(long)CIVal.getSExtValue()30
;
848
32
      if ((IsZExt && 
isUInt<16>(Imm)2
) ||
(30
!IsZExt30
&&
isInt<16>(Imm)30
))
849
28
        UseImm = true;
850
32
    }
851
32
  }
852
59
853
59
  unsigned SrcReg1 = getRegForValue(SrcValue1);
854
59
  if (SrcReg1 == 0)
855
0
    return false;
856
59
857
59
  unsigned SrcReg2 = 0;
858
59
  if (!UseImm) {
859
31
    SrcReg2 = getRegForValue(SrcValue2);
860
31
    if (SrcReg2 == 0)
861
0
      return false;
862
59
  }
863
59
864
59
  unsigned CmpOpc;
865
59
  bool NeedsExt = false;
866
59
867
59
  auto RC1 = MRI.getRegClass(SrcReg1);
868
59
  auto RC2 = SrcReg2 != 0 ? 
MRI.getRegClass(SrcReg2)31
:
nullptr28
;
869
59
870
59
  switch (SrcVT.SimpleTy) {
871
59
    
default: return false0
;
872
59
    case MVT::f32:
873
6
      if (HasSPE) {
874
0
        switch (Pred) {
875
0
          default: return false;
876
0
          case PPC::PRED_EQ:
877
0
            CmpOpc = PPC::EFSCMPEQ;
878
0
            break;
879
0
          case PPC::PRED_LT:
880
0
            CmpOpc = PPC::EFSCMPLT;
881
0
            break;
882
0
          case PPC::PRED_GT:
883
0
            CmpOpc = PPC::EFSCMPGT;
884
0
            break;
885
6
        }
886
6
      } else {
887
6
        CmpOpc = PPC::FCMPUS;
888
6
        if (isVSSRCRegClass(RC1))
889
2
          SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1);
890
6
        if (RC2 && isVSSRCRegClass(RC2))
891
1
          SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
892
6
      }
893
6
      break;
894
13
    case MVT::f64:
895
13
      if (HasSPE) {
896
0
        switch (Pred) {
897
0
          default: return false;
898
0
          case PPC::PRED_EQ:
899
0
            CmpOpc = PPC::EFDCMPEQ;
900
0
            break;
901
0
          case PPC::PRED_LT:
902
0
            CmpOpc = PPC::EFDCMPLT;
903
0
            break;
904
0
          case PPC::PRED_GT:
905
0
            CmpOpc = PPC::EFDCMPGT;
906
0
            break;
907
13
        }
908
13
      } else if (isVSFRCRegClass(RC1) || 
(4
RC24
&&
isVSFRCRegClass(RC2)4
)) {
909
10
        CmpOpc = PPC::XSCMPUDP;
910
10
      } else {
911
3
        CmpOpc = PPC::FCMPUD;
912
3
      }
913
13
      break;
914
15
    case MVT::i1:
915
15
    case MVT::i8:
916
15
    case MVT::i16:
917
15
      NeedsExt = true;
918
15
      LLVM_FALLTHROUGH;
919
29
    case MVT::i32:
920
29
      if (!UseImm)
921
8
        CmpOpc = IsZExt ? 
PPC::CMPLW0
: PPC::CMPW;
922
21
      else
923
21
        CmpOpc = IsZExt ? 
PPC::CMPLWI2
:
PPC::CMPWI19
;
924
29
      break;
925
15
    case MVT::i64:
926
11
      if (!UseImm)
927
4
        CmpOpc = IsZExt ? 
PPC::CMPLD0
: PPC::CMPD;
928
7
      else
929
7
        CmpOpc = IsZExt ? 
PPC::CMPLDI0
: PPC::CMPDI;
930
11
      break;
931
59
  }
932
59
933
59
  if (NeedsExt) {
934
15
    unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
935
15
    if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
936
0
      return false;
937
15
    SrcReg1 = ExtReg;
938
15
939
15
    if (!UseImm) {
940
4
      unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
941
4
      if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
942
0
        return false;
943
4
      SrcReg2 = ExtReg;
944
4
    }
945
15
  }
946
59
947
59
  if (!UseImm)
948
31
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
949
31
      .addReg(SrcReg1).addReg(SrcReg2);
950
28
  else
951
28
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
952
28
      .addReg(SrcReg1).addImm(Imm);
953
59
954
59
  return true;
955
59
}
956
957
// Attempt to fast-select a floating-point extend instruction.
958
0
bool PPCFastISel::SelectFPExt(const Instruction *I) {
959
0
  Value *Src  = I->getOperand(0);
960
0
  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
961
0
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
962
0
963
0
  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
964
0
    return false;
965
0
966
0
  unsigned SrcReg = getRegForValue(Src);
967
0
  if (!SrcReg)
968
0
    return false;
969
0
970
0
  // No code is generated for a FP extend.
971
0
  updateValueMap(I, SrcReg);
972
0
  return true;
973
0
}
974
975
// Attempt to fast-select a floating-point truncate instruction.
976
2
bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
977
2
  Value *Src  = I->getOperand(0);
978
2
  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
979
2
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
980
2
981
2
  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
982
0
    return false;
983
2
984
2
  unsigned SrcReg = getRegForValue(Src);
985
2
  if (!SrcReg)
986
0
    return false;
987
2
988
2
  // Round the result to single precision.
989
2
  unsigned DestReg;
990
2
  auto RC = MRI.getRegClass(SrcReg);
991
2
  if (PPCSubTarget->hasSPE()) {
992
0
    DestReg = createResultReg(&PPC::SPE4RCRegClass);
993
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
994
0
      TII.get(PPC::EFSCFD), DestReg)
995
0
      .addReg(SrcReg);
996
2
  } else if (isVSFRCRegClass(RC)) {
997
1
    DestReg = createResultReg(&PPC::VSSRCRegClass);
998
1
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
999
1
      TII.get(PPC::XSRSP), DestReg)
1000
1
      .addReg(SrcReg);
1001
1
  } else {
1002
1
    DestReg = createResultReg(&PPC::F4RCRegClass);
1003
1
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1004
1
      TII.get(PPC::FRSP), DestReg)
1005
1
      .addReg(SrcReg);
1006
1
  }
1007
2
1008
2
  updateValueMap(I, DestReg);
1009
2
  return true;
1010
2
}
1011
1012
// Move an i32 or i64 value in a GPR to an f64 value in an FPR.
1013
// FIXME: When direct register moves are implemented (see PowerISA 2.07),
1014
// those should be used instead of moving via a stack slot when the
1015
// subtarget permits.
1016
// FIXME: The code here is sloppy for the 4-byte case.  Can use a 4-byte
1017
// stack slot and 4-byte store/load sequence.  Or just sext the 4-byte
1018
// case to 8 bytes which produces tighter code but wastes stack space.
1019
unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
1020
40
                                     bool IsSigned) {
1021
40
1022
40
  // If necessary, extend 32-bit int to 64-bit.
1023
40
  if (SrcVT == MVT::i32) {
1024
10
    unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1025
10
    if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1026
0
      return 0;
1027
10
    SrcReg = TmpReg;
1028
10
  }
1029
40
1030
40
  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1031
40
  Address Addr;
1032
40
  Addr.BaseType = Address::FrameIndexBase;
1033
40
  Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1034
40
1035
40
  // Store the value from the GPR.
1036
40
  if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1037
0
    return 0;
1038
40
1039
40
  // Load the integer value into an FPR.  The kind of load used depends
1040
40
  // on a number of conditions.
1041
40
  unsigned LoadOpc = PPC::LFD;
1042
40
1043
40
  if (SrcVT == MVT::i32) {
1044
10
    if (!IsSigned) {
1045
4
      LoadOpc = PPC::LFIWZX;
1046
4
      Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 
02
:
42
;
1047
6
    } else if (PPCSubTarget->hasLFIWAX()) {
1048
4
      LoadOpc = PPC::LFIWAX;
1049
4
      Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 
02
:
42
;
1050
4
    }
1051
10
  }
1052
40
1053
40
  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1054
40
  unsigned ResultReg = 0;
1055
40
  if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1056
0
    return 0;
1057
40
1058
40
  return ResultReg;
1059
40
}
1060
1061
// Attempt to fast-select an integer-to-floating-point conversion.
1062
// FIXME: Once fast-isel has better support for VSX, conversions using
1063
//        direct moves should be implemented.
1064
58
bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
1065
58
  MVT DstVT;
1066
58
  Type *DstTy = I->getType();
1067
58
  if (!isTypeLegal(DstTy, DstVT))
1068
0
    return false;
1069
58
1070
58
  if (DstVT != MVT::f32 && 
DstVT != MVT::f6432
)
1071
4
    return false;
1072
54
1073
54
  Value *Src = I->getOperand(0);
1074
54
  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1075
54
  if (!SrcEVT.isSimple())
1076
0
    return false;
1077
54
1078
54
  MVT SrcVT = SrcEVT.getSimpleVT();
1079
54
1080
54
  if (SrcVT != MVT::i8  && 
SrcVT != MVT::i1641
&&
1081
54
      
SrcVT != MVT::i3228
&&
SrcVT != MVT::i6415
)
1082
2
    return false;
1083
52
1084
52
  unsigned SrcReg = getRegForValue(Src);
1085
52
  if (SrcReg == 0)
1086
0
    return false;
1087
52
1088
52
  // Shortcut for SPE.  Doesn't need to store/load, since it's all in the GPRs
1089
52
  if (PPCSubTarget->hasSPE()) {
1090
0
    unsigned Opc;
1091
0
    if (DstVT == MVT::f32)
1092
0
      Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI;
1093
0
    else
1094
0
      Opc = IsSigned ? PPC::EFDCFSI : PPC::EFDCFUI;
1095
0
1096
0
    unsigned DestReg = createResultReg(&PPC::SPERCRegClass);
1097
0
    // Generate the convert.
1098
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1099
0
      .addReg(SrcReg);
1100
0
    updateValueMap(I, DestReg);
1101
0
    return true;
1102
0
  }
1103
52
1104
52
  // We can only lower an unsigned convert if we have the newer
1105
52
  // floating-point conversion operations.
1106
52
  if (!IsSigned && 
!PPCSubTarget->hasFPCVT()24
)
1107
8
    return false;
1108
44
1109
44
  // FIXME: For now we require the newer floating-point conversion operations
1110
44
  // (which are present only on P7 and A2 server models) when converting
1111
44
  // to single-precision float.  Otherwise we have to generate a lot of
1112
44
  // fiddly code to avoid double rounding.  If necessary, the fiddly code
1113
44
  // can be found in PPCTargetLowering::LowerINT_TO_FP().
1114
44
  if (DstVT == MVT::f32 && 
!PPCSubTarget->hasFPCVT()20
)
1115
4
    return false;
1116
40
1117
40
  // Extend the input if necessary.
1118
40
  if (SrcVT == MVT::i8 || 
SrcVT == MVT::i1630
) {
1119
20
    unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1120
20
    if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1121
0
      return false;
1122
20
    SrcVT = MVT::i64;
1123
20
    SrcReg = TmpReg;
1124
20
  }
1125
40
1126
40
  // Move the integer value to an FPR.
1127
40
  unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1128
40
  if (FPReg == 0)
1129
0
    return false;
1130
40
1131
40
  // Determine the opcode for the conversion.
1132
40
  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1133
40
  unsigned DestReg = createResultReg(RC);
1134
40
  unsigned Opc;
1135
40
1136
40
  if (DstVT == MVT::f32)
1137
16
    Opc = IsSigned ? 
PPC::FCFIDS8
:
PPC::FCFIDUS8
;
1138
24
  else
1139
24
    Opc = IsSigned ? 
PPC::FCFID16
:
PPC::FCFIDU8
;
1140
40
1141
40
  // Generate the convert.
1142
40
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1143
40
    .addReg(FPReg);
1144
40
1145
40
  updateValueMap(I, DestReg);
1146
40
  return true;
1147
40
}
1148
1149
// Move the floating-point value in SrcReg into an integer destination
1150
// register, and return the register (or zero if we can't handle it).
1151
// FIXME: When direct register moves are implemented (see PowerISA 2.07),
1152
// those should be used instead of moving via a stack slot when the
1153
// subtarget permits.
1154
unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1155
34
                                      unsigned SrcReg, bool IsSigned) {
1156
34
  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1157
34
  // Note that if have STFIWX available, we could use a 4-byte stack
1158
34
  // slot for i32, but this being fast-isel we'll just go with the
1159
34
  // easiest code gen possible.
1160
34
  Address Addr;
1161
34
  Addr.BaseType = Address::FrameIndexBase;
1162
34
  Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1163
34
1164
34
  // Store the value from the FPR.
1165
34
  if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1166
2
    return 0;
1167
32
1168
32
  // Reload it into a GPR.  If we want an i32 on big endian, modify the
1169
32
  // address to have a 4-byte offset so we load from the right place.
1170
32
  if (VT == MVT::i32)
1171
20
    Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 
06
:
414
;
1172
32
1173
32
  // Look at the currently assigned register for this instruction
1174
32
  // to determine the required register class.
1175
32
  unsigned AssignedReg = FuncInfo.ValueMap[I];
1176
32
  const TargetRegisterClass *RC =
1177
32
    AssignedReg ? MRI.getRegClass(AssignedReg) : 
nullptr0
;
1178
32
1179
32
  unsigned ResultReg = 0;
1180
32
  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1181
0
    return 0;
1182
32
1183
32
  return ResultReg;
1184
32
}
1185
1186
// Attempt to fast-select a floating-point-to-integer conversion.
1187
// FIXME: Once fast-isel has better support for VSX, conversions using
1188
//        direct moves should be implemented.
1189
39
bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1190
39
  MVT DstVT, SrcVT;
1191
39
  Type *DstTy = I->getType();
1192
39
  if (!isTypeLegal(DstTy, DstVT))
1193
0
    return false;
1194
39
1195
39
  if (DstVT != MVT::i32 && 
DstVT != MVT::i6417
)
1196
3
    return false;
1197
36
1198
36
  // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG.
1199
36
  if (DstVT == MVT::i64 && 
!IsSigned14
&&
1200
36
      
!PPCSubTarget->hasFPCVT()6
&&
!PPCSubTarget->hasSPE()2
)
1201
2
    return false;
1202
34
1203
34
  Value *Src = I->getOperand(0);
1204
34
  Type *SrcTy = Src->getType();
1205
34
  if (!isTypeLegal(SrcTy, SrcVT))
1206
0
    return false;
1207
34
1208
34
  if (SrcVT != MVT::f32 && 
SrcVT != MVT::f6416
)
1209
0
    return false;
1210
34
1211
34
  unsigned SrcReg = getRegForValue(Src);
1212
34
  if (SrcReg == 0)
1213
0
    return false;
1214
34
1215
34
  // Convert f32 to f64 or convert VSSRC to VSFRC if necessary. This is just a
1216
34
  // meaningless copy to get the register class right.
1217
34
  const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1218
34
  if (InRC == &PPC::F4RCRegClass)
1219
17
    SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
1220
17
  else if (InRC == &PPC::VSSRCRegClass)
1221
1
    SrcReg = copyRegToRegClass(&PPC::VSFRCRegClass, SrcReg);
1222
34
1223
34
  // Determine the opcode for the conversion, which takes place
1224
34
  // entirely within FPRs or VSRs.
1225
34
  unsigned DestReg;
1226
34
  unsigned Opc;
1227
34
  auto RC = MRI.getRegClass(SrcReg);
1228
34
1229
34
  if (PPCSubTarget->hasSPE()) {
1230
0
    DestReg = createResultReg(&PPC::GPRCRegClass);
1231
0
    if (IsSigned)
1232
0
      Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
1233
0
    else
1234
0
      Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
1235
34
  } else if (isVSFRCRegClass(RC)) {
1236
2
    DestReg = createResultReg(&PPC::VSFRCRegClass);
1237
2
    if (DstVT == MVT::i32) 
1238
2
      Opc = IsSigned ? 
PPC::XSCVDPSXWS1
:
PPC::XSCVDPUXWS1
;
1239
0
    else
1240
0
      Opc = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
1241
32
  } else {
1242
32
    DestReg = createResultReg(&PPC::F8RCRegClass);
1243
32
    if (DstVT == MVT::i32)
1244
20
      if (IsSigned)
1245
11
        Opc = PPC::FCTIWZ;
1246
9
      else
1247
9
        Opc = PPCSubTarget->hasFPCVT() ? 
PPC::FCTIWUZ4
:
PPC::FCTIDZ5
;
1248
12
    else
1249
12
      Opc = IsSigned ? 
PPC::FCTIDZ8
:
PPC::FCTIDUZ4
;
1250
32
  }
1251
34
1252
34
  // Generate the convert.
1253
34
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1254
34
    .addReg(SrcReg);
1255
34
1256
34
  // Now move the integer value from a float register to an integer register.
1257
34
  unsigned IntReg = PPCSubTarget->hasSPE() ? 
DestReg0
:
1258
34
    PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1259
34
1260
34
  if (IntReg == 0)
1261
2
    return false;
1262
32
1263
32
  updateValueMap(I, IntReg);
1264
32
  return true;
1265
32
}
1266
1267
// Attempt to fast-select a binary integer operation that isn't already
1268
// handled automatically.
1269
21
bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1270
21
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1271
21
1272
21
  // We can get here in the case when we have a binary operation on a non-legal
1273
21
  // type and the target independent selector doesn't know how to handle it.
1274
21
  if (DestVT != MVT::i16 && 
DestVT != MVT::i812
)
1275
4
    return false;
1276
17
1277
17
  // Look at the currently assigned register for this instruction
1278
17
  // to determine the required register class.  If there is no register,
1279
17
  // make a conservative choice (don't assign R0).
1280
17
  unsigned AssignedReg = FuncInfo.ValueMap[I];
1281
17
  const TargetRegisterClass *RC =
1282
17
    (AssignedReg ? MRI.getRegClass(AssignedReg) :
1283
17
     
&PPC::GPRC_and_GPRC_NOR0RegClass0
);
1284
17
  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1285
17
1286
17
  unsigned Opc;
1287
17
  switch (ISDOpcode) {
1288
17
    
default: return false0
;
1289
17
    case ISD::ADD:
1290
8
      Opc = IsGPRC ? PPC::ADD4 : 
PPC::ADD80
;
1291
8
      break;
1292
17
    case ISD::OR:
1293
4
      Opc = IsGPRC ? PPC::OR : 
PPC::OR80
;
1294
4
      break;
1295
17
    case ISD::SUB:
1296
5
      Opc = IsGPRC ? PPC::SUBF : 
PPC::SUBF80
;
1297
5
      break;
1298
17
  }
1299
17
1300
17
  unsigned ResultReg = createResultReg(RC ? RC : 
&PPC::G8RCRegClass0
);
1301
17
  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1302
17
  if (SrcReg1 == 0) 
return false0
;
1303
17
1304
17
  // Handle case of small immediate operand.
1305
17
  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1306
11
    const APInt &CIVal = ConstInt->getValue();
1307
11
    int Imm = (int)CIVal.getSExtValue();
1308
11
    bool UseImm = true;
1309
11
    if (isInt<16>(Imm)) {
1310
11
      switch (Opc) {
1311
11
        default:
1312
0
          llvm_unreachable("Missing case!");
1313
11
        case PPC::ADD4:
1314
6
          Opc = PPC::ADDI;
1315
6
          MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1316
6
          break;
1317
11
        case PPC::ADD8:
1318
0
          Opc = PPC::ADDI8;
1319
0
          MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1320
0
          break;
1321
11
        case PPC::OR:
1322
2
          Opc = PPC::ORI;
1323
2
          break;
1324
11
        case PPC::OR8:
1325
0
          Opc = PPC::ORI8;
1326
0
          break;
1327
11
        case PPC::SUBF:
1328
3
          if (Imm == -32768)
1329
1
            UseImm = false;
1330
2
          else {
1331
2
            Opc = PPC::ADDI;
1332
2
            MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1333
2
            Imm = -Imm;
1334
2
          }
1335
3
          break;
1336
11
        case PPC::SUBF8:
1337
0
          if (Imm == -32768)
1338
0
            UseImm = false;
1339
0
          else {
1340
0
            Opc = PPC::ADDI8;
1341
0
            MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1342
0
            Imm = -Imm;
1343
0
          }
1344
0
          break;
1345
11
      }
1346
11
1347
11
      if (UseImm) {
1348
10
        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1349
10
                ResultReg)
1350
10
            .addReg(SrcReg1)
1351
10
            .addImm(Imm);
1352
10
        updateValueMap(I, ResultReg);
1353
10
        return true;
1354
10
      }
1355
7
    }
1356
11
  }
1357
7
1358
7
  // Reg-reg case.
1359
7
  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1360
7
  if (SrcReg2 == 0) 
return false0
;
1361
7
1362
7
  // Reverse operands for subtract-from.
1363
7
  if (ISDOpcode == ISD::SUB)
1364
3
    std::swap(SrcReg1, SrcReg2);
1365
7
1366
7
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1367
7
    .addReg(SrcReg1).addReg(SrcReg2);
1368
7
  updateValueMap(I, ResultReg);
1369
7
  return true;
1370
7
}
1371
1372
// Handle arguments to a call that we're attempting to fast-select.
1373
// Return false if the arguments are too complex for us at the moment.
1374
bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1375
                                  SmallVectorImpl<unsigned> &ArgRegs,
1376
                                  SmallVectorImpl<MVT> &ArgVTs,
1377
                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1378
                                  SmallVectorImpl<unsigned> &RegArgs,
1379
                                  CallingConv::ID CC,
1380
                                  unsigned &NumBytes,
1381
96
                                  bool IsVarArg) {
1382
96
  SmallVector<CCValAssign, 16> ArgLocs;
1383
96
  CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1384
96
1385
96
  // Reserve space for the linkage area on the stack.
1386
96
  unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1387
96
  CCInfo.AllocateStack(LinkageSize, 8);
1388
96
1389
96
  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1390
96
1391
96
  // Bail out if we can't handle any of the arguments.
1392
177
  for (unsigned I = 0, E = ArgLocs.size(); I != E; 
++I81
) {
1393
81
    CCValAssign &VA = ArgLocs[I];
1394
81
    MVT ArgVT = ArgVTs[VA.getValNo()];
1395
81
1396
81
    // Skip vector arguments for now, as well as long double and
1397
81
    // uint128_t, and anything that isn't passed in a register.
1398
81
    if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1399
81
        !VA.isRegLoc() || VA.needsCustom())
1400
0
      return false;
1401
81
1402
81
    // Skip bit-converted arguments for now.
1403
81
    if (VA.getLocInfo() == CCValAssign::BCvt)
1404
0
      return false;
1405
81
  }
1406
96
1407
96
  // Get a count of how many bytes are to be pushed onto the stack.
1408
96
  NumBytes = CCInfo.getNextStackOffset();
1409
96
1410
96
  // The prolog code of the callee may store up to 8 GPR argument registers to
1411
96
  // the stack, allowing va_start to index over them in memory if its varargs.
1412
96
  // Because we cannot tell if this is needed on the caller side, we have to
1413
96
  // conservatively assume that it is needed.  As such, make sure we have at
1414
96
  // least enough stack space for the caller to store the 8 GPRs.
1415
96
  // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1416
96
  NumBytes = std::max(NumBytes, LinkageSize + 64);
1417
96
1418
96
  // Issue CALLSEQ_START.
1419
96
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1420
96
          TII.get(TII.getCallFrameSetupOpcode()))
1421
96
    .addImm(NumBytes).addImm(0);
1422
96
1423
96
  // Prepare to assign register arguments.  Every argument uses up a
1424
96
  // GPR protocol register even if it's passed in a floating-point
1425
96
  // register (unless we're using the fast calling convention).
1426
96
  unsigned NextGPR = PPC::X3;
1427
96
  unsigned NextFPR = PPC::F1;
1428
96
1429
96
  // Process arguments.
1430
177
  for (unsigned I = 0, E = ArgLocs.size(); I != E; 
++I81
) {
1431
81
    CCValAssign &VA = ArgLocs[I];
1432
81
    unsigned Arg = ArgRegs[VA.getValNo()];
1433
81
    MVT ArgVT = ArgVTs[VA.getValNo()];
1434
81
1435
81
    // Handle argument promotion and bitcasts.
1436
81
    switch (VA.getLocInfo()) {
1437
81
      default:
1438
0
        llvm_unreachable("Unknown loc info!");
1439
81
      case CCValAssign::Full:
1440
62
        break;
1441
81
      case CCValAssign::SExt: {
1442
2
        MVT DestVT = VA.getLocVT();
1443
2
        const TargetRegisterClass *RC =
1444
2
          (DestVT == MVT::i64) ? &PPC::G8RCRegClass : 
&PPC::GPRCRegClass0
;
1445
2
        unsigned TmpReg = createResultReg(RC);
1446
2
        if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1447
2
          
llvm_unreachable0
("Failed to emit a sext!");
1448
2
        ArgVT = DestVT;
1449
2
        Arg = TmpReg;
1450
2
        break;
1451
2
      }
1452
17
      case CCValAssign::AExt:
1453
17
      case CCValAssign::ZExt: {
1454
17
        MVT DestVT = VA.getLocVT();
1455
17
        const TargetRegisterClass *RC =
1456
17
          (DestVT == MVT::i64) ? &PPC::G8RCRegClass : 
&PPC::GPRCRegClass0
;
1457
17
        unsigned TmpReg = createResultReg(RC);
1458
17
        if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1459
17
          
llvm_unreachable0
("Failed to emit a zext!");
1460
17
        ArgVT = DestVT;
1461
17
        Arg = TmpReg;
1462
17
        break;
1463
17
      }
1464
17
      case CCValAssign::BCvt: {
1465
0
        // FIXME: Not yet handled.
1466
0
        llvm_unreachable("Should have bailed before getting here!");
1467
17
        
break0
;
1468
81
      }
1469
81
    }
1470
81
1471
81
    // Copy this argument to the appropriate register.
1472
81
    unsigned ArgReg;
1473
81
    if (ArgVT == MVT::f32 || 
ArgVT == MVT::f6479
) {
1474
18
      ArgReg = NextFPR++;
1475
18
      if (CC != CallingConv::Fast)
1476
10
        ++NextGPR;
1477
18
    } else
1478
63
      ArgReg = NextGPR++;
1479
81
1480
81
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1481
81
            TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1482
81
    RegArgs.push_back(ArgReg);
1483
81
  }
1484
96
1485
96
  return true;
1486
96
}
1487
1488
// For a call that we've determined we can fast-select, finish the
1489
// call sequence and generate a copy to obtain the return value (if any).
1490
96
bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1491
96
  CallingConv::ID CC = CLI.CallConv;
1492
96
1493
96
  // Issue CallSEQ_END.
1494
96
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1495
96
          TII.get(TII.getCallFrameDestroyOpcode()))
1496
96
    .addImm(NumBytes).addImm(0);
1497
96
1498
96
  // Next, generate a copy to obtain the return value.
1499
96
  // FIXME: No multi-register return values yet, though I don't foresee
1500
96
  // any real difficulties there.
1501
96
  if (RetVT != MVT::isVoid) {
1502
23
    SmallVector<CCValAssign, 16> RVLocs;
1503
23
    CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1504
23
    CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1505
23
    CCValAssign &VA = RVLocs[0];
1506
23
    assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1507
23
    assert(VA.isRegLoc() && "Can only return in registers!");
1508
23
1509
23
    MVT DestVT = VA.getValVT();
1510
23
    MVT CopyVT = DestVT;
1511
23
1512
23
    // Ints smaller than a register still arrive in a full 64-bit
1513
23
    // register, so make sure we recognize this.
1514
23
    if (RetVT == MVT::i8 || 
RetVT == MVT::i1621
||
RetVT == MVT::i3219
)
1515
12
      CopyVT = MVT::i64;
1516
23
1517
23
    unsigned SourcePhysReg = VA.getLocReg();
1518
23
    unsigned ResultReg = 0;
1519
23
1520
23
    if (RetVT == CopyVT) {
1521
11
      const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1522
11
      ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg);
1523
11
1524
11
    // If necessary, round the floating result to single precision.
1525
12
    } else if (CopyVT == MVT::f64) {
1526
0
      ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1527
0
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1528
0
              ResultReg).addReg(SourcePhysReg);
1529
0
1530
0
    // If only the low half of a general register is needed, generate
1531
0
    // a GPRC copy instead of a G8RC copy.  (EXTRACT_SUBREG can't be
1532
0
    // used along the fast-isel path (not lowered), and downstream logic
1533
0
    // also doesn't like a direct subreg copy on a physical reg.)
1534
12
    } else if (RetVT == MVT::i8 || 
RetVT == MVT::i1610
||
RetVT == MVT::i328
) {
1535
12
      // Convert physical register from G8RC to GPRC.
1536
12
      SourcePhysReg -= PPC::X0 - PPC::R0;
1537
12
      ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
1538
12
    }
1539
23
1540
23
    assert(ResultReg && "ResultReg unset!");
1541
23
    CLI.InRegs.push_back(SourcePhysReg);
1542
23
    CLI.ResultReg = ResultReg;
1543
23
    CLI.NumResultRegs = 1;
1544
23
  }
1545
96
1546
96
  return true;
1547
96
}
1548
1549
112
bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1550
112
  CallingConv::ID CC  = CLI.CallConv;
1551
112
  bool IsTailCall     = CLI.IsTailCall;
1552
112
  bool IsVarArg       = CLI.IsVarArg;
1553
112
  const Value *Callee = CLI.Callee;
1554
112
  const MCSymbol *Symbol = CLI.Symbol;
1555
112
1556
112
  if (!Callee && 
!Symbol0
)
1557
0
    return false;
1558
112
1559
112
  // Allow SelectionDAG isel to handle tail calls.
1560
112
  if (IsTailCall)
1561
0
    return false;
1562
112
1563
112
  // Let SDISel handle vararg functions.
1564
112
  if (IsVarArg)
1565
6
    return false;
1566
106
1567
106
  // Handle simple calls for now, with legal return types and
1568
106
  // those that can be extended.
1569
106
  Type *RetTy = CLI.RetTy;
1570
106
  MVT RetVT;
1571
106
  if (RetTy->isVoidTy())
1572
81
    RetVT = MVT::isVoid;
1573
25
  else if (!isTypeLegal(RetTy, RetVT) && 
RetVT != MVT::i164
&&
1574
25
           
RetVT != MVT::i82
)
1575
0
    return false;
1576
25
  else if (RetVT == MVT::i1 && 
PPCSubTarget->useCRBits()2
)
1577
2
    // We can't handle boolean returns when CR bits are in use.
1578
2
    return false;
1579
104
1580
104
  // FIXME: No multi-register return values yet.
1581
104
  if (RetVT != MVT::isVoid && 
RetVT != MVT::i823
&&
RetVT != MVT::i1621
&&
1582
104
      
RetVT != MVT::i3219
&&
RetVT != MVT::i6411
&&
RetVT != MVT::f322
&&
1583
104
      
RetVT != MVT::f642
) {
1584
0
    SmallVector<CCValAssign, 16> RVLocs;
1585
0
    CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1586
0
    CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1587
0
    if (RVLocs.size() > 1)
1588
0
      return false;
1589
104
  }
1590
104
1591
104
  // Bail early if more than 8 arguments, as we only currently
1592
104
  // handle arguments passed in registers.
1593
104
  unsigned NumArgs = CLI.OutVals.size();
1594
104
  if (NumArgs > 8)
1595
0
    return false;
1596
104
1597
104
  // Set up the argument vectors.
1598
104
  SmallVector<Value*, 8> Args;
1599
104
  SmallVector<unsigned, 8> ArgRegs;
1600
104
  SmallVector<MVT, 8> ArgVTs;
1601
104
  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1602
104
1603
104
  Args.reserve(NumArgs);
1604
104
  ArgRegs.reserve(NumArgs);
1605
104
  ArgVTs.reserve(NumArgs);
1606
104
  ArgFlags.reserve(NumArgs);
1607
104
1608
197
  for (unsigned i = 0, ie = NumArgs; i != ie; 
++i93
) {
1609
101
    // Only handle easy calls for now.  It would be reasonably easy
1610
101
    // to handle <= 8-byte structures passed ByVal in registers, but we
1611
101
    // have to ensure they are right-justified in the register.
1612
101
    ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1613
101
    if (Flags.isInReg() || Flags.isSRet() || 
Flags.isNest()99
||
Flags.isByVal()99
)
1614
4
      return false;
1615
97
1616
97
    Value *ArgValue = CLI.OutVals[i];
1617
97
    Type *ArgTy = ArgValue->getType();
1618
97
    MVT ArgVT;
1619
97
    if (!isTypeLegal(ArgTy, ArgVT) && 
ArgVT != MVT::i1618
&&
ArgVT != MVT::i814
)
1620
4
      return false;
1621
93
1622
93
    if (ArgVT.isVector())
1623
0
      return false;
1624
93
1625
93
    unsigned Arg = getRegForValue(ArgValue);
1626
93
    if (Arg == 0)
1627
0
      return false;
1628
93
1629
93
    Args.push_back(ArgValue);
1630
93
    ArgRegs.push_back(Arg);
1631
93
    ArgVTs.push_back(ArgVT);
1632
93
    ArgFlags.push_back(Flags);
1633
93
  }
1634
104
1635
104
  // Process the arguments.
1636
104
  SmallVector<unsigned, 8> RegArgs;
1637
96
  unsigned NumBytes;
1638
96
1639
96
  if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1640
96
                       RegArgs, CC, NumBytes, IsVarArg))
1641
0
    return false;
1642
96
1643
96
  MachineInstrBuilder MIB;
1644
96
  // FIXME: No handling for function pointers yet.  This requires
1645
96
  // implementing the function descriptor (OPD) setup.
1646
96
  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1647
96
  if (!GV) {
1648
10
    // patchpoints are a special case; they always dispatch to a pointer value.
1649
10
    // However, we don't actually want to generate the indirect call sequence
1650
10
    // here (that will be generated, as necessary, during asm printing), and
1651
10
    // the call we generate here will be erased by FastISel::selectPatchpoint,
1652
10
    // so don't try very hard...
1653
10
    if (CLI.IsPatchPoint)
1654
10
      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1655
0
    else
1656
0
      return false;
1657
86
  } else {
1658
86
    // Build direct call with NOP for TOC restore.
1659
86
    // FIXME: We can and should optimize away the NOP for local calls.
1660
86
    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1661
86
                  TII.get(PPC::BL8_NOP));
1662
86
    // Add callee.
1663
86
    MIB.addGlobalAddress(GV);
1664
86
  }
1665
96
1666
96
  // Add implicit physical register uses to the call.
1667
177
  
for (unsigned II = 0, IE = RegArgs.size(); 96
II != IE;
++II81
)
1668
81
    MIB.addReg(RegArgs[II], RegState::Implicit);
1669
96
1670
96
  // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1671
96
  // into the call.
1672
96
  PPCFuncInfo->setUsesTOCBasePtr();
1673
96
  MIB.addReg(PPC::X2, RegState::Implicit);
1674
96
1675
96
  // Add a register mask with the call-preserved registers.  Proper
1676
96
  // defs for return values will be added by setPhysRegsDeadExcept().
1677
96
  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1678
96
1679
96
  CLI.Call = MIB;
1680
96
1681
96
  // Finish off the call including any return values.
1682
96
  return finishCall(RetVT, CLI, NumBytes);
1683
96
}
1684
1685
// Attempt to fast-select a return instruction.
1686
703
bool PPCFastISel::SelectRet(const Instruction *I) {
1687
703
1688
703
  if (!FuncInfo.CanLowerReturn)
1689
0
    return false;
1690
703
1691
703
  if (TLI.supportSplitCSR(FuncInfo.MF))
1692
0
    return false;
1693
703
1694
703
  const ReturnInst *Ret = cast<ReturnInst>(I);
1695
703
  const Function &F = *I->getParent()->getParent();
1696
703
1697
703
  // Build a list of return value registers.
1698
703
  SmallVector<unsigned, 4> RetRegs;
1699
703
  CallingConv::ID CC = F.getCallingConv();
1700
703
1701
703
  if (Ret->getNumOperands() > 0) {
1702
479
    SmallVector<ISD::OutputArg, 4> Outs;
1703
479
    GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1704
479
1705
479
    // Analyze operands of the call, assigning locations to each operand.
1706
479
    SmallVector<CCValAssign, 16> ValLocs;
1707
479
    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1708
479
    CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1709
479
    const Value *RV = Ret->getOperand(0);
1710
479
1711
479
    // FIXME: Only one output register for now.
1712
479
    if (ValLocs.size() > 1)
1713
4
      return false;
1714
475
1715
475
    // Special case for returning a constant integer of any size - materialize
1716
475
    // the constant as an i64 and copy it to the return register.
1717
475
    if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1718
59
      CCValAssign &VA = ValLocs[0];
1719
59
1720
59
      unsigned RetReg = VA.getLocReg();
1721
59
      // We still need to worry about properly extending the sign. For example,
1722
59
      // we could have only a single bit or a constant that needs zero
1723
59
      // extension rather than sign extension. Make sure we pass the return
1724
59
      // value extension property to integer materialization.
1725
59
      unsigned SrcReg =
1726
59
          PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
1727
59
1728
59
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1729
59
            TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1730
59
1731
59
      RetRegs.push_back(RetReg);
1732
59
1733
416
    } else {
1734
416
      unsigned Reg = getRegForValue(RV);
1735
416
1736
416
      if (Reg == 0)
1737
28
        return false;
1738
388
1739
388
      // Copy the result values into the output registers.
1740
774
      
for (unsigned i = 0; 388
i < ValLocs.size();
++i386
) {
1741
388
1742
388
        CCValAssign &VA = ValLocs[i];
1743
388
        assert(VA.isRegLoc() && "Can only return in registers!");
1744
388
        RetRegs.push_back(VA.getLocReg());
1745
388
        unsigned SrcReg = Reg + VA.getValNo();
1746
388
1747
388
        EVT RVEVT = TLI.getValueType(DL, RV->getType());
1748
388
        if (!RVEVT.isSimple())
1749
0
          return false;
1750
388
        MVT RVVT = RVEVT.getSimpleVT();
1751
388
        MVT DestVT = VA.getLocVT();
1752
388
1753
388
        if (RVVT != DestVT && 
RVVT != MVT::i862
&&
1754
388
            
RVVT != MVT::i1656
&&
RVVT != MVT::i3252
)
1755
2
          return false;
1756
386
1757
386
        if (RVVT != DestVT) {
1758
60
          switch (VA.getLocInfo()) {
1759
60
            default:
1760
0
              llvm_unreachable("Unknown loc info!");
1761
60
            case CCValAssign::Full:
1762
0
              llvm_unreachable("Full value assign but types don't match?");
1763
60
            case CCValAssign::AExt:
1764
39
            case CCValAssign::ZExt: {
1765
39
              const TargetRegisterClass *RC =
1766
39
                (DestVT == MVT::i64) ? &PPC::G8RCRegClass : 
&PPC::GPRCRegClass0
;
1767
39
              unsigned TmpReg = createResultReg(RC);
1768
39
              if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1769
0
                return false;
1770
39
              SrcReg = TmpReg;
1771
39
              break;
1772
39
            }
1773
39
            case CCValAssign::SExt: {
1774
21
              const TargetRegisterClass *RC =
1775
21
                (DestVT == MVT::i64) ? &PPC::G8RCRegClass : 
&PPC::GPRCRegClass0
;
1776
21
              unsigned TmpReg = createResultReg(RC);
1777
21
              if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1778
0
                return false;
1779
21
              SrcReg = TmpReg;
1780
21
              break;
1781
21
            }
1782
60
          }
1783
60
        }
1784
386
1785
386
        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1786
386
                TII.get(TargetOpcode::COPY), RetRegs[i])
1787
386
          .addReg(SrcReg);
1788
386
      }
1789
388
    }
1790
475
  }
1791
703
1792
703
  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1793
669
                                    TII.get(PPC::BLR8));
1794
669
1795
1.11k
  for (unsigned i = 0, e = RetRegs.size(); i != e; 
++i445
)
1796
445
    MIB.addReg(RetRegs[i], RegState::Implicit);
1797
669
1798
669
  return true;
1799
703
}
1800
1801
// Attempt to emit an integer extend of SrcReg into DestReg.  Both
1802
// signed and zero extensions are supported.  Return false if we
1803
// can't handle it.
1804
bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1805
154
                                unsigned DestReg, bool IsZExt) {
1806
154
  if (DestVT != MVT::i32 && 
DestVT != MVT::i64122
)
1807
0
    return false;
1808
154
  if (SrcVT != MVT::i8 && 
SrcVT != MVT::i16107
&&
SrcVT != MVT::i3271
)
1809
4
    return false;
1810
150
1811
150
  // Signed extensions use EXTSB, EXTSH, EXTSW.
1812
150
  if (!IsZExt) {
1813
68
    unsigned Opc;
1814
68
    if (SrcVT == MVT::i8)
1815
24
      Opc = (DestVT == MVT::i32) ? 
PPC::EXTSB12
:
PPC::EXTSB8_32_6412
;
1816
44
    else if (SrcVT == MVT::i16)
1817
21
      Opc = (DestVT == MVT::i32) ? 
PPC::EXTSH11
:
PPC::EXTSH8_32_6410
;
1818
23
    else {
1819
23
      assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1820
23
      Opc = PPC::EXTSW_32_64;
1821
23
    }
1822
68
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1823
68
      .addReg(SrcReg);
1824
68
1825
68
  // Unsigned 32-bit extensions use RLWINM.
1826
82
  } else if (DestVT == MVT::i32) {
1827
8
    unsigned MB;
1828
8
    if (SrcVT == MVT::i8)
1829
5
      MB = 24;
1830
3
    else {
1831
3
      assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1832
3
      MB = 16;
1833
3
    }
1834
8
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1835
8
            DestReg)
1836
8
      .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1837
8
1838
8
  // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1839
74
  } else {
1840
74
    unsigned MB;
1841
74
    if (SrcVT == MVT::i8)
1842
18
      MB = 56;
1843
56
    else if (SrcVT == MVT::i16)
1844
12
      MB = 48;
1845
44
    else
1846
44
      MB = 32;
1847
74
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1848
74
            TII.get(PPC::RLDICL_32_64), DestReg)
1849
74
      .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1850
74
  }
1851
150
1852
150
  return true;
1853
150
}
1854
1855
// Attempt to fast-select an indirect branch instruction.
1856
1
bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1857
1
  unsigned AddrReg = getRegForValue(I->getOperand(0));
1858
1
  if (AddrReg == 0)
1859
0
    return false;
1860
1
1861
1
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1862
1
    .addReg(AddrReg);
1863
1
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1864
1
1865
1
  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1866
1
  for (const BasicBlock *SuccBB : IB->successors())
1867
2
    FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1868
1
1869
1
  return true;
1870
1
}
1871
1872
// Attempt to fast-select an integer truncate instruction.
1873
2
bool PPCFastISel::SelectTrunc(const Instruction *I) {
1874
2
  Value *Src  = I->getOperand(0);
1875
2
  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1876
2
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1877
2
1878
2
  if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && 
SrcVT != MVT::i160
)
1879
0
    return false;
1880
2
1881
2
  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1882
0
    return false;
1883
2
1884
2
  unsigned SrcReg = getRegForValue(Src);
1885
2
  if (!SrcReg)
1886
0
    return false;
1887
2
1888
2
  // The only interesting case is when we need to switch register classes.
1889
2
  if (SrcVT == MVT::i64)
1890
0
    SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
1891
2
1892
2
  updateValueMap(I, SrcReg);
1893
2
  return true;
1894
2
}
1895
1896
// Attempt to fast-select an integer extend instruction.
1897
26
bool PPCFastISel::SelectIntExt(const Instruction *I) {
1898
26
  Type *DestTy = I->getType();
1899
26
  Value *Src = I->getOperand(0);
1900
26
  Type *SrcTy = Src->getType();
1901
26
1902
26
  bool IsZExt = isa<ZExtInst>(I);
1903
26
  unsigned SrcReg = getRegForValue(Src);
1904
26
  if (!SrcReg) 
return false0
;
1905
26
1906
26
  EVT SrcEVT, DestEVT;
1907
26
  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1908
26
  DestEVT = TLI.getValueType(DL, DestTy, true);
1909
26
  if (!SrcEVT.isSimple())
1910
0
    return false;
1911
26
  if (!DestEVT.isSimple())
1912
0
    return false;
1913
26
1914
26
  MVT SrcVT = SrcEVT.getSimpleVT();
1915
26
  MVT DestVT = DestEVT.getSimpleVT();
1916
26
1917
26
  // If we know the register class needed for the result of this
1918
26
  // instruction, use it.  Otherwise pick the register class of the
1919
26
  // correct size that does not contain X0/R0, since we don't know
1920
26
  // whether downstream uses permit that assignment.
1921
26
  unsigned AssignedReg = FuncInfo.ValueMap[I];
1922
26
  const TargetRegisterClass *RC =
1923
26
    (AssignedReg ? MRI.getRegClass(AssignedReg) :
1924
26
     
(DestVT == MVT::i64 0
?
&PPC::G8RC_and_G8RC_NOX0RegClass0
:
1925
0
      &PPC::GPRC_and_GPRC_NOR0RegClass));
1926
26
  unsigned ResultReg = createResultReg(RC);
1927
26
1928
26
  if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1929
4
    return false;
1930
22
1931
22
  updateValueMap(I, ResultReg);
1932
22
  return true;
1933
22
}
1934
1935
// Attempt to fast-select an instruction that wasn't handled by
1936
// the table-generated machinery.
1937
1.46k
bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1938
1.46k
1939
1.46k
  switch (I->getOpcode()) {
1940
1.46k
    case Instruction::Load:
1941
73
      return SelectLoad(I);
1942
1.46k
    case Instruction::Store:
1943
177
      return SelectStore(I);
1944
1.46k
    case Instruction::Br:
1945
84
      return SelectBranch(I);
1946
1.46k
    case Instruction::IndirectBr:
1947
1
      return SelectIndirectBr(I);
1948
1.46k
    case Instruction::FPExt:
1949
0
      return SelectFPExt(I);
1950
1.46k
    case Instruction::FPTrunc:
1951
2
      return SelectFPTrunc(I);
1952
1.46k
    case Instruction::SIToFP:
1953
33
      return SelectIToFP(I, /*IsSigned*/ true);
1954
1.46k
    case Instruction::UIToFP:
1955
25
      return SelectIToFP(I, /*IsSigned*/ false);
1956
1.46k
    case Instruction::FPToSI:
1957
21
      return SelectFPToI(I, /*IsSigned*/ true);
1958
1.46k
    case Instruction::FPToUI:
1959
18
      return SelectFPToI(I, /*IsSigned*/ false);
1960
1.46k
    case Instruction::Add:
1961
9
      return SelectBinaryIntOp(I, ISD::ADD);
1962
1.46k
    case Instruction::Or:
1963
6
      return SelectBinaryIntOp(I, ISD::OR);
1964
1.46k
    case Instruction::Sub:
1965
6
      return SelectBinaryIntOp(I, ISD::SUB);
1966
1.46k
    case Instruction::Call:
1967
45
      // On AIX, call lowering uses the DAG-ISEL path currently so that the
1968
45
      // callee of the direct function call instruction will be mapped to the
1969
45
      // symbol for the function's entry point, which is distinct from the
1970
45
      // function descriptor symbol. The latter is the symbol whose XCOFF symbol
1971
45
      // name is the C-linkage name of the source level function.
1972
45
      if (TM.getTargetTriple().isOSAIX())
1973
0
        break;
1974
45
      return selectCall(I);
1975
703
    case Instruction::Ret:
1976
703
      return SelectRet(I);
1977
45
    case Instruction::Trunc:
1978
2
      return SelectTrunc(I);
1979
45
    case Instruction::ZExt:
1980
26
    case Instruction::SExt:
1981
26
      return SelectIntExt(I);
1982
26
    // Here add other flavors of Instruction::XXX that automated
1983
26
    // cases don't catch.  For example, switches are terminators
1984
26
    // that aren't yet handled.
1985
235
    default:
1986
235
      break;
1987
235
  }
1988
235
  return false;
1989
235
}
1990
1991
// Materialize a floating-point constant into a register, and return
1992
// the register number (or zero if we failed to handle it).
1993
31
unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1994
31
  // No plans to handle long double here.
1995
31
  if (VT != MVT::f32 && 
VT != MVT::f6419
)
1996
0
    return 0;
1997
31
1998
31
  // All FP constants are loaded from the constant pool.
1999
31
  unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
2000
31
  assert(Align > 0 && "Unexpectedly missing alignment information!");
2001
31
  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
2002
31
  const bool HasSPE = PPCSubTarget->hasSPE();
2003
31
  const TargetRegisterClass *RC;
2004
31
  if (HasSPE)
2005
0
    RC = ((VT == MVT::f32) ? &PPC::SPE4RCRegClass : &PPC::SPERCRegClass);
2006
31
  else
2007
31
    RC = ((VT == MVT::f32) ? 
&PPC::F4RCRegClass12
:
&PPC::F8RCRegClass19
);
2008
31
2009
31
  unsigned DestReg = createResultReg(RC);
2010
31
  CodeModel::Model CModel = TM.getCodeModel();
2011
31
2012
31
  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2013
31
      MachinePointerInfo::getConstantPool(*FuncInfo.MF),
2014
31
      MachineMemOperand::MOLoad, (VT == MVT::f32) ? 
412
:
819
, Align);
2015
31
2016
31
  unsigned Opc;
2017
31
2018
31
  if (HasSPE)
2019
0
    Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2020
31
  else
2021
31
    Opc = ((VT == MVT::f32) ? 
PPC::LFS12
:
PPC::LFD19
);
2022
31
2023
31
  unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2024
31
2025
31
  PPCFuncInfo->setUsesTOCBasePtr();
2026
31
  // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
2027
31
  if (CModel == CodeModel::Small) {
2028
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
2029
0
            TmpReg)
2030
0
      .addConstantPoolIndex(Idx).addReg(PPC::X2);
2031
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2032
0
      .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2033
31
  } else {
2034
31
    // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)).
2035
31
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2036
31
            TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
2037
31
    // But for large code model, we must generate a LDtocL followed
2038
31
    // by the LF[SD].
2039
31
    if (CModel == CodeModel::Large) {
2040
0
      unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2041
0
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2042
0
              TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
2043
0
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2044
0
          .addImm(0)
2045
0
          .addReg(TmpReg2);
2046
0
    } else
2047
31
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2048
31
        .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
2049
31
        .addReg(TmpReg)
2050
31
        .addMemOperand(MMO);
2051
31
  }
2052
31
2053
31
  return DestReg;
2054
31
}
2055
2056
// Materialize the address of a global value into a register, and return
2057
// the register number (or zero if we failed to handle it).
2058
74
unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
2059
74
  assert(VT == MVT::i64 && "Non-address!");
2060
74
  const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2061
74
  unsigned DestReg = createResultReg(RC);
2062
74
2063
74
  // Global values may be plain old object addresses, TLS object
2064
74
  // addresses, constant pool entries, or jump tables.  How we generate
2065
74
  // code for these may depend on small, medium, or large code model.
2066
74
  CodeModel::Model CModel = TM.getCodeModel();
2067
74
2068
74
  // FIXME: Jump tables are not yet required because fast-isel doesn't
2069
74
  // handle switches; if that changes, we need them as well.  For now,
2070
74
  // what follows assumes everything's a generic (or TLS) global address.
2071
74
2072
74
  // FIXME: We don't yet handle the complexity of TLS.
2073
74
  if (GV->isThreadLocal())
2074
8
    return 0;
2075
66
2076
66
  PPCFuncInfo->setUsesTOCBasePtr();
2077
66
  // For small code model, generate a simple TOC load.
2078
66
  if (CModel == CodeModel::Small)
2079
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
2080
0
            DestReg)
2081
0
        .addGlobalAddress(GV)
2082
0
        .addReg(PPC::X2);
2083
66
  else {
2084
66
    // If the address is an externally defined symbol, a symbol with common
2085
66
    // or externally available linkage, a non-local function address, or a
2086
66
    // jump table address (not yet needed), or if we are generating code
2087
66
    // for large code model, we generate:
2088
66
    //       LDtocL(GV, ADDIStocHA8(%x2, GV))
2089
66
    // Otherwise we generate:
2090
66
    //       ADDItocL(ADDIStocHA8(%x2, GV), GV)
2091
66
    // Either way, start with the ADDIStocHA8:
2092
66
    unsigned HighPartReg = createResultReg(RC);
2093
66
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2094
66
            HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
2095
66
2096
66
    unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
2097
66
    if (GVFlags & PPCII::MO_NLP_FLAG) {
2098
42
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2099
42
              DestReg).addGlobalAddress(GV).addReg(HighPartReg);
2100
42
    } else {
2101
24
      // Otherwise generate the ADDItocL.
2102
24
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
2103
24
              DestReg).addReg(HighPartReg).addGlobalAddress(GV);
2104
24
    }
2105
66
  }
2106
66
2107
66
  return DestReg;
2108
66
}
2109
2110
// Materialize a 32-bit integer constant into a register, and return
2111
// the register number (or zero if we failed to handle it).
2112
unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2113
38
                                             const TargetRegisterClass *RC) {
2114
38
  unsigned Lo = Imm & 0xFFFF;
2115
38
  unsigned Hi = (Imm >> 16) & 0xFFFF;
2116
38
2117
38
  unsigned ResultReg = createResultReg(RC);
2118
38
  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2119
38
2120
38
  if (isInt<16>(Imm))
2121
6
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2122
6
            TII.get(IsGPRC ? 
PPC::LI2
:
PPC::LI84
), ResultReg)
2123
6
      .addImm(Imm);
2124
32
  else if (Lo) {
2125
29
    // Both Lo and Hi have nonzero bits.
2126
29
    unsigned TmpReg = createResultReg(RC);
2127
29
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2128
29
            TII.get(IsGPRC ? 
PPC::LIS10
:
PPC::LIS819
), TmpReg)
2129
29
      .addImm(Hi);
2130
29
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2131
29
            TII.get(IsGPRC ? 
PPC::ORI10
:
PPC::ORI819
), ResultReg)
2132
29
      .addReg(TmpReg).addImm(Lo);
2133
29
  } else
2134
3
    // Just Hi bits.
2135
3
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2136
3
            TII.get(IsGPRC ? 
PPC::LIS2
:
PPC::LIS81
), ResultReg)
2137
3
        .addImm(Hi);
2138
38
2139
38
  return ResultReg;
2140
38
}
2141
2142
// Materialize a 64-bit integer constant into a register, and return
2143
// the register number (or zero if we failed to handle it).
2144
unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2145
24
                                             const TargetRegisterClass *RC) {
2146
24
  unsigned Remainder = 0;
2147
24
  unsigned Shift = 0;
2148
24
2149
24
  // If the value doesn't fit in 32 bits, see if we can shift it
2150
24
  // so that it fits in 32 bits.
2151
24
  if (!isInt<32>(Imm)) {
2152
3
    Shift = countTrailingZeros<uint64_t>(Imm);
2153
3
    int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2154
3
2155
3
    if (isInt<32>(ImmSh))
2156
1
      Imm = ImmSh;
2157
2
    else {
2158
2
      Remainder = Imm;
2159
2
      Shift = 32;
2160
2
      Imm >>= 32;
2161
2
    }
2162
3
  }
2163
24
2164
24
  // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2165
24
  // (if not shifted).
2166
24
  unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2167
24
  if (!Shift)
2168
21
    return TmpReg1;
2169
3
2170
3
  // If upper 32 bits were not zero, we've built them and need to shift
2171
3
  // them into place.
2172
3
  unsigned TmpReg2;
2173
3
  if (Imm) {
2174
2
    TmpReg2 = createResultReg(RC);
2175
2
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2176
2
            TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2177
2
  } else
2178
1
    TmpReg2 = TmpReg1;
2179
3
2180
3
  unsigned TmpReg3, Hi, Lo;
2181
3
  if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2182
2
    TmpReg3 = createResultReg(RC);
2183
2
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2184
2
            TmpReg3).addReg(TmpReg2).addImm(Hi);
2185
2
  } else
2186
1
    TmpReg3 = TmpReg2;
2187
3
2188
3
  if ((Lo = Remainder & 0xFFFF)) {
2189
2
    unsigned ResultReg = createResultReg(RC);
2190
2
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2191
2
            ResultReg).addReg(TmpReg3).addImm(Lo);
2192
2
    return ResultReg;
2193
2
  }
2194
1
2195
1
  return TmpReg3;
2196
1
}
2197
2198
// Materialize an integer constant into a register, and return
2199
// the register number (or zero if we failed to handle it).
2200
unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
2201
107
                                        bool UseSExt) {
2202
107
  // If we're using CR bit registers for i1 values, handle that as a special
2203
107
  // case first.
2204
107
  if (VT == MVT::i1 && 
PPCSubTarget->useCRBits()2
) {
2205
0
    unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2206
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2207
0
            TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2208
0
    return ImmReg;
2209
0
  }
2210
107
2211
107
  if (VT != MVT::i64 && 
VT != MVT::i3231
&&
VT != MVT::i1615
&&
VT != MVT::i811
&&
2212
107
      
VT != MVT::i12
)
2213
0
    return 0;
2214
107
2215
107
  const TargetRegisterClass *RC =
2216
107
      ((VT == MVT::i64) ? 
&PPC::G8RCRegClass76
:
&PPC::GPRCRegClass31
);
2217
107
  int64_t Imm = UseSExt ? 
CI->getSExtValue()53
:
CI->getZExtValue()54
;
2218
107
2219
107
  // If the constant is in range, use a load-immediate.
2220
107
  // Since LI will sign extend the constant we need to make sure that for
2221
107
  // our zeroext constants that the sign extended constant fits into 16-bits -
2222
107
  // a range of 0..0x7fff.
2223
107
  if (isInt<16>(Imm)) {
2224
73
    unsigned Opc = (VT == MVT::i64) ? 
PPC::LI854
:
PPC::LI19
;
2225
73
    unsigned ImmReg = createResultReg(RC);
2226
73
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2227
73
        .addImm(Imm);
2228
73
    return ImmReg;
2229
73
  }
2230
34
2231
34
  // Construct the constant piecewise.
2232
34
  if (VT == MVT::i64)
2233
22
    return PPCMaterialize64BitInt(Imm, RC);
2234
12
  else if (VT == MVT::i32)
2235
10
    return PPCMaterialize32BitInt(Imm, RC);
2236
2
2237
2
  return 0;
2238
2
}
2239
2240
// Materialize a constant into a register, and return the register
2241
// number (or zero if we failed to handle it).
2242
201
unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2243
201
  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2244
201
2245
201
  // Only handle simple types.
2246
201
  if (!CEVT.isSimple()) 
return 00
;
2247
201
  MVT VT = CEVT.getSimpleVT();
2248
201
2249
201
  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2250
31
    return PPCMaterializeFP(CFP, VT);
2251
170
  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2252
74
    return PPCMaterializeGV(GV, VT);
2253
96
  else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2254
42
    // Note that the code in FunctionLoweringInfo::ComputePHILiveOutRegInfo
2255
42
    // assumes that constant PHI operands will be zero extended, and failure to
2256
42
    // match that assumption will cause problems if we sign extend here but
2257
42
    // some user of a PHI is in a block for which we fall back to full SDAG
2258
42
    // instruction selection.
2259
42
    return PPCMaterializeInt(CI, VT, false);
2260
54
2261
54
  return 0;
2262
54
}
2263
2264
// Materialize the address created by an alloca into a register, and
2265
// return the register number (or zero if we failed to handle it).
2266
9
unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2267
9
  // Don't handle dynamic allocas.
2268
9
  if (!FuncInfo.StaticAllocaMap.count(AI)) 
return 00
;
2269
9
2270
9
  MVT VT;
2271
9
  if (!isLoadTypeLegal(AI->getType(), VT)) 
return 00
;
2272
9
2273
9
  DenseMap<const AllocaInst*, int>::iterator SI =
2274
9
    FuncInfo.StaticAllocaMap.find(AI);
2275
9
2276
9
  if (SI != FuncInfo.StaticAllocaMap.end()) {
2277
9
    unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2278
9
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2279
9
            ResultReg).addFrameIndex(SI->second).addImm(0);
2280
9
    return ResultReg;
2281
9
  }
2282
0
2283
0
  return 0;
2284
0
}
2285
2286
// Fold loads into extends when possible.
2287
// FIXME: We can have multiple redundant extend/trunc instructions
2288
// following a load.  The folding only picks up one.  Extend this
2289
// to check subsequent instructions for the same pattern and remove
2290
// them.  Thus ResultReg should be the def reg for the last redundant
2291
// instruction in a chain, and all intervening instructions can be
2292
// removed from parent.  Change test/CodeGen/PowerPC/fast-isel-fold.ll
2293
// to add ELF64-NOT: rldicl to the appropriate tests when this works.
2294
bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2295
63
                                      const LoadInst *LI) {
2296
63
  // Verify we have a legal type before going any further.
2297
63
  MVT VT;
2298
63
  if (!isLoadTypeLegal(LI->getType(), VT))
2299
0
    return false;
2300
63
2301
63
  // Combine load followed by zero- or sign-extend.
2302
63
  bool IsZExt = false;
2303
63
  switch(MI->getOpcode()) {
2304
63
    default:
2305
36
      return false;
2306
63
2307
63
    case PPC::RLDICL:
2308
14
    case PPC::RLDICL_32_64: {
2309
14
      IsZExt = true;
2310
14
      unsigned MB = MI->getOperand(3).getImm();
2311
14
      if ((VT == MVT::i8 && 
MB <= 563
) ||
2312
14
          
(11
VT == MVT::i1611
&&
MB <= 482
) ||
2313
14
          
(9
VT == MVT::i329
&&
MB <= 329
))
2314
14
        break;
2315
0
      return false;
2316
0
    }
2317
0
2318
2
    case PPC::RLWINM:
2319
2
    case PPC::RLWINM8: {
2320
2
      IsZExt = true;
2321
2
      unsigned MB = MI->getOperand(3).getImm();
2322
2
      if ((VT == MVT::i8 && 
MB <= 241
) ||
2323
2
          
(1
VT == MVT::i161
&&
MB <= 161
))
2324
2
        break;
2325
0
      return false;
2326
0
    }
2327
0
2328
4
    case PPC::EXTSB:
2329
4
    case PPC::EXTSB8:
2330
4
    case PPC::EXTSB8_32_64:
2331
4
      /* There is no sign-extending load-byte instruction. */
2332
4
      return false;
2333
4
2334
4
    case PPC::EXTSH:
2335
2
    case PPC::EXTSH8:
2336
2
    case PPC::EXTSH8_32_64: {
2337
2
      if (VT != MVT::i16 && 
VT != MVT::i80
)
2338
0
        return false;
2339
2
      break;
2340
2
    }
2341
2
2342
5
    case PPC::EXTSW:
2343
5
    case PPC::EXTSW_32:
2344
5
    case PPC::EXTSW_32_64: {
2345
5
      if (VT != MVT::i32 && 
VT != MVT::i160
&&
VT != MVT::i80
)
2346
0
        return false;
2347
5
      break;
2348
5
    }
2349
23
  }
2350
23
2351
23
  // See if we can handle this address.
2352
23
  Address Addr;
2353
23
  if (!PPCComputeAddress(LI->getOperand(0), Addr))
2354
3
    return false;
2355
20
2356
20
  unsigned ResultReg = MI->getOperand(0).getReg();
2357
20
2358
20
  if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,
2359
20
        PPCSubTarget->hasSPE() ? 
PPC::EVLDD0
: PPC::LFD))
2360
0
    return false;
2361
20
2362
20
  MachineBasicBlock::iterator I(MI);
2363
20
  removeDeadCode(I, std::next(I));
2364
20
  return true;
2365
20
}
2366
2367
// Attempt to lower call arguments in a faster way than done by
2368
// the selection DAG code.
2369
692
bool PPCFastISel::fastLowerArguments() {
2370
692
  // Defer to normal argument lowering for now.  It's reasonably
2371
692
  // efficient.  Consider doing something like ARM to handle the
2372
692
  // case where all args fit in registers, no varargs, no float
2373
692
  // or vector args.
2374
692
  return false;
2375
692
}
2376
2377
// Handle materializing integer constants into a register.  This is not
2378
// automatically generated for PowerPC, so must be explicitly created here.
2379
6
unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2380
6
2381
6
  if (Opc != ISD::Constant)
2382
0
    return 0;
2383
6
2384
6
  // If we're using CR bit registers for i1 values, handle that as a special
2385
6
  // case first.
2386
6
  if (VT == MVT::i1 && 
PPCSubTarget->useCRBits()0
) {
2387
0
    unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2388
0
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2389
0
            TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2390
0
    return ImmReg;
2391
0
  }
2392
6
2393
6
  if (VT != MVT::i64 && 
VT != MVT::i324
&&
VT != MVT::i160
&&
VT != MVT::i80
&&
2394
6
      
VT != MVT::i10
)
2395
0
    return 0;
2396
6
2397
6
  const TargetRegisterClass *RC = ((VT == MVT::i64) ? 
&PPC::G8RCRegClass2
:
2398
6
                                   
&PPC::GPRCRegClass4
);
2399
6
  if (VT == MVT::i64)
2400
2
    return PPCMaterialize64BitInt(Imm, RC);
2401
4
  else
2402
4
    return PPCMaterialize32BitInt(Imm, RC);
2403
6
}
2404
2405
// Override for ADDI and ADDI8 to set the correct register class
2406
// on RHS operand 0.  The automatic infrastructure naively assumes
2407
// GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2408
// for these cases.  At the moment, none of the other automatically
2409
// generated RI instructions require special treatment.  However, once
2410
// SelectSelect is implemented, "isel" requires similar handling.
2411
//
2412
// Also be conservative about the output register class.  Avoid
2413
// assigning R0 or X0 to the output register for GPRC and G8RC
2414
// register classes, as any such result could be used in ADDI, etc.,
2415
// where those regs have another meaning.
2416
unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2417
                                      const TargetRegisterClass *RC,
2418
                                      unsigned Op0, bool Op0IsKill,
2419
38
                                      uint64_t Imm) {
2420
38
  if (MachineInstOpcode == PPC::ADDI)
2421
20
    MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2422
18
  else if (MachineInstOpcode == PPC::ADDI8)
2423
17
    MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2424
38
2425
38
  const TargetRegisterClass *UseRC =
2426
38
    (RC == &PPC::GPRCRegClass ? 
&PPC::GPRC_and_GPRC_NOR0RegClass21
:
2427
38
     
(RC == &PPC::G8RCRegClass 17
?
&PPC::G8RC_and_G8RC_NOX0RegClass17
:
RC0
));
2428
38
2429
38
  return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC,
2430
38
                                   Op0, Op0IsKill, Imm);
2431
38
}
2432
2433
// Override for instructions with one register operand to avoid use of
2434
// R0/X0.  The automatic infrastructure isn't aware of the context so
2435
// we must be conservative.
2436
unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2437
                                     const TargetRegisterClass* RC,
2438
6
                                     unsigned Op0, bool Op0IsKill) {
2439
6
  const TargetRegisterClass *UseRC =
2440
6
    (RC == &PPC::GPRCRegClass ? 
&PPC::GPRC_and_GPRC_NOR0RegClass0
:
2441
6
     (RC == &PPC::G8RCRegClass ? 
&PPC::G8RC_and_G8RC_NOX0RegClass4
:
RC2
));
2442
6
2443
6
  return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2444
6
}
2445
2446
// Override for instructions with two register operands to avoid use
2447
// of R0/X0.  The automatic infrastructure isn't aware of the context
2448
// so we must be conservative.
2449
unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2450
                                      const TargetRegisterClass* RC,
2451
                                      unsigned Op0, bool Op0IsKill,
2452
24
                                      unsigned Op1, bool Op1IsKill) {
2453
24
  const TargetRegisterClass *UseRC =
2454
24
    (RC == &PPC::GPRCRegClass ? 
&PPC::GPRC_and_GPRC_NOR0RegClass5
:
2455
24
     
(RC == &PPC::G8RCRegClass 19
?
&PPC::G8RC_and_G8RC_NOX0RegClass1
:
RC18
));
2456
24
2457
24
  return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2458
24
                                   Op1, Op1IsKill);
2459
24
}
2460
2461
namespace llvm {
2462
  // Create the fast instruction selector for PowerPC64 ELF.
2463
  FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2464
804
                                const TargetLibraryInfo *LibInfo) {
2465
804
    // Only available on 64-bit ELF for now.
2466
804
    const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2467
804
    if (Subtarget.isPPC64() && 
Subtarget.isSVR4ABI()692
)
2468
692
      return new PPCFastISel(FuncInfo, LibInfo);
2469
112
    return nullptr;
2470
112
  }
2471
}