Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCInstrInfo.h
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//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14
#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15
16
#include "PPCRegisterInfo.h"
17
#include "llvm/CodeGen/TargetInstrInfo.h"
18
19
#define GET_INSTRINFO_HEADER
20
#include "PPCGenInstrInfo.inc"
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namespace llvm {
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24
/// PPCII - This namespace holds all of the PowerPC target-specific
25
/// per-instruction flags.  These must match the corresponding definitions in
26
/// PPC.td and PPCInstrFormats.td.
27
namespace PPCII {
28
enum {
29
  // PPC970 Instruction Flags.  These flags describe the characteristics of the
30
  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
31
  // raw machine instructions.
32
33
  /// PPC970_First - This instruction starts a new dispatch group, so it will
34
  /// always be the first one in the group.
35
  PPC970_First = 0x1,
36
37
  /// PPC970_Single - This instruction starts a new dispatch group and
38
  /// terminates it, so it will be the sole instruction in the group.
39
  PPC970_Single = 0x2,
40
41
  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
42
  /// two dispatch pipes to be available to issue.
43
  PPC970_Cracked = 0x4,
44
45
  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
46
  /// an instruction is issued to.
47
  PPC970_Shift = 3,
48
  PPC970_Mask = 0x07 << PPC970_Shift
49
};
50
enum PPC970_Unit {
51
  /// These are the various PPC970 execution unit pipelines.  Each instruction
52
  /// is one of these.
53
  PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
54
  PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
55
  PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
56
  PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
57
  PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
58
  PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
59
  PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
60
  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
61
};
62
63
enum {
64
  /// Shift count to bypass PPC970 flags
65
  NewDef_Shift = 6,
66
67
  /// This instruction is an X-Form memory operation.
68
  XFormMemOp = 0x1 << (NewDef_Shift+1)
69
};
70
} // end namespace PPCII
71
72
// Instructions that have an immediate form might be convertible to that
73
// form if the correct input is a result of a load immediate. In order to
74
// know whether the transformation is special, we might need to know some
75
// of the details of the two forms.
76
struct ImmInstrInfo {
77
  // Is the immediate field in the immediate form signed or unsigned?
78
  uint64_t SignedImm : 1;
79
  // Does the immediate need to be a multiple of some value?
80
  uint64_t ImmMustBeMultipleOf : 5;
81
  // Is R0/X0 treated specially by the original r+r instruction?
82
  // If so, in which operand?
83
  uint64_t ZeroIsSpecialOrig : 3;
84
  // Is R0/X0 treated specially by the new r+i instruction?
85
  // If so, in which operand?
86
  uint64_t ZeroIsSpecialNew : 3;
87
  // Is the operation commutative?
88
  uint64_t IsCommutative : 1;
89
  // The operand number to check for add-immediate def.
90
  uint64_t OpNoForForwarding : 3;
91
  // The operand number for the immediate.
92
  uint64_t ImmOpNo : 3;
93
  // The opcode of the new instruction.
94
  uint64_t ImmOpcode : 16;
95
  // The size of the immediate.
96
  uint64_t ImmWidth : 5;
97
  // The immediate should be truncated to N bits.
98
  uint64_t TruncateImmTo : 5;
99
  // Is the instruction summing the operand
100
  uint64_t IsSummingOperands : 1;
101
};
102
103
// Information required to convert an instruction to just a materialized
104
// immediate.
105
struct LoadImmediateInfo {
106
  unsigned Imm : 16;
107
  unsigned Is64Bit : 1;
108
  unsigned SetCR : 1;
109
};
110
111
class PPCSubtarget;
112
class PPCInstrInfo : public PPCGenInstrInfo {
113
  PPCSubtarget &Subtarget;
114
  const PPCRegisterInfo RI;
115
116
  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
117
                           int FrameIdx, const TargetRegisterClass *RC,
118
                           SmallVectorImpl<MachineInstr *> &NewMIs) const;
119
  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
120
                            unsigned DestReg, int FrameIdx,
121
                            const TargetRegisterClass *RC,
122
                            SmallVectorImpl<MachineInstr *> &NewMIs) const;
123
124
  // If the inst has imm-form and one of its operand is produced by a LI,
125
  // put the imm into the inst directly and remove the LI if possible.
126
  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
127
                                 unsigned ConstantOpNo, MachineInstr &DefMI,
128
                                 int64_t Imm) const;
129
  // If the inst has imm-form and one of its operand is produced by an
130
  // add-immediate, try to transform it when possible.
131
  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
132
                                  unsigned ConstantOpNo, MachineInstr &DefMI,
133
                                  bool KillDefMI) const;
134
  // Try to find that, if the instruction 'MI' contains any operand that
135
  // could be forwarded from some inst that feeds it. If yes, return the
136
  // Def of that operand. And OpNoForForwarding is the operand index in
137
  // the 'MI' for that 'Def'. If we see another use of this Def between
138
  // the Def and the MI, SeenIntermediateUse becomes 'true'.
139
  MachineInstr *getForwardingDefMI(MachineInstr &MI,
140
                                   unsigned &OpNoForForwarding,
141
                                   bool &SeenIntermediateUse) const;
142
143
  // Can the user MI have it's source at index \p OpNoForForwarding
144
  // forwarded from an add-immediate that feeds it?
145
  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
146
                                   unsigned OpNoForForwarding) const;
147
  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
148
                                   const ImmInstrInfo &III,
149
                                   MachineOperand *&ImmMO,
150
                                   MachineOperand *&RegMO) const;
151
  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
152
                                 const MachineInstr &DefMI,
153
                                 const ImmInstrInfo &III,
154
                                 int64_t &Imm) const;
155
  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
156
                                 const MachineInstr &DefMI,
157
                                 const MachineInstr &MI, bool KillDefMI,
158
                                 bool &IsFwdFeederRegKilled) const;
159
  const unsigned *getStoreOpcodesForSpillArray() const;
160
  const unsigned *getLoadOpcodesForSpillArray() const;
161
  virtual void anchor();
162
163
protected:
164
  /// Commutes the operands in the given instruction.
165
  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
166
  ///
167
  /// Do not call this method for a non-commutable instruction or for
168
  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
169
  /// Even though the instruction is commutable, the method may still
170
  /// fail to commute the operands, null pointer is returned in such cases.
171
  ///
172
  /// For example, we can commute rlwimi instructions, but only if the
173
  /// rotate amt is zero.  We also have to munge the immediates a bit.
174
  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
175
                                       unsigned OpIdx1,
176
                                       unsigned OpIdx2) const override;
177
178
public:
179
  explicit PPCInstrInfo(PPCSubtarget &STI);
180
181
  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
182
  /// such, whenever a client has an instance of instruction info, it should
183
  /// always be able to get register info as well (through this method).
184
  ///
185
5.65M
  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
186
187
6.27k
  bool isXFormMemOp(unsigned Opcode) const {
188
6.27k
    return get(Opcode).TSFlags & PPCII::XFormMemOp;
189
6.27k
  }
190
104k
  static bool isSameClassPhysRegCopy(unsigned Opcode) {
191
104k
    unsigned CopyOpcodes[] =
192
104k
      { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf,
193
104k
        PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb,
194
104k
        PPC::CROR, PPC::EVOR, -1U };
195
1.40M
    for (int i = 0; CopyOpcodes[i] != -1U; 
i++1.30M
)
196
1.30M
      if (Opcode == CopyOpcodes[i])
197
4.48k
        return true;
198
104k
    
return false99.6k
;
199
104k
  }
200
201
  ScheduleHazardRecognizer *
202
  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
203
                               const ScheduleDAG *DAG) const override;
204
  ScheduleHazardRecognizer *
205
  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
206
                                     const ScheduleDAG *DAG) const override;
207
208
  unsigned getInstrLatency(const InstrItineraryData *ItinData,
209
                           const MachineInstr &MI,
210
                           unsigned *PredCost = nullptr) const override;
211
212
  int getOperandLatency(const InstrItineraryData *ItinData,
213
                        const MachineInstr &DefMI, unsigned DefIdx,
214
                        const MachineInstr &UseMI,
215
                        unsigned UseIdx) const override;
216
  int getOperandLatency(const InstrItineraryData *ItinData,
217
                        SDNode *DefNode, unsigned DefIdx,
218
0
                        SDNode *UseNode, unsigned UseIdx) const override {
219
0
    return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
220
0
                                              UseNode, UseIdx);
221
0
  }
222
223
  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
224
                        const MachineInstr &DefMI,
225
533
                        unsigned DefIdx) const override {
226
533
    // Machine LICM should hoist all instructions in low-register-pressure
227
533
    // situations; none are sufficiently free to justify leaving in a loop
228
533
    // body.
229
533
    return false;
230
533
  }
231
232
10.3k
  bool useMachineCombiner() const override {
233
10.3k
    return true;
234
10.3k
  }
235
236
  /// Return true when there is potentially a faster code sequence
237
  /// for an instruction chain ending in <Root>. All potential patterns are
238
  /// output in the <Pattern> array.
239
  bool getMachineCombinerPatterns(
240
      MachineInstr &Root,
241
      SmallVectorImpl<MachineCombinerPattern> &P) const override;
242
243
  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
244
245
  bool isCoalescableExtInstr(const MachineInstr &MI,
246
                             unsigned &SrcReg, unsigned &DstReg,
247
                             unsigned &SubIdx) const override;
248
  unsigned isLoadFromStackSlot(const MachineInstr &MI,
249
                               int &FrameIndex) const override;
250
  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
251
                                         AliasAnalysis *AA) const override;
252
  unsigned isStoreToStackSlot(const MachineInstr &MI,
253
                              int &FrameIndex) const override;
254
255
  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
256
                             unsigned &SrcOpIdx2) const override;
257
258
  void insertNoop(MachineBasicBlock &MBB,
259
                  MachineBasicBlock::iterator MI) const override;
260
261
262
  // Branch analysis.
263
  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
264
                     MachineBasicBlock *&FBB,
265
                     SmallVectorImpl<MachineOperand> &Cond,
266
                     bool AllowModify) const override;
267
  unsigned removeBranch(MachineBasicBlock &MBB,
268
                        int *BytesRemoved = nullptr) const override;
269
  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
270
                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
271
                        const DebugLoc &DL,
272
                        int *BytesAdded = nullptr) const override;
273
274
  // Select analysis.
275
  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
276
                       unsigned, unsigned, int &, int &, int &) const override;
277
  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
278
                    const DebugLoc &DL, unsigned DstReg,
279
                    ArrayRef<MachineOperand> Cond, unsigned TrueReg,
280
                    unsigned FalseReg) const override;
281
282
  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
283
                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
284
                   bool KillSrc) const override;
285
286
  void storeRegToStackSlot(MachineBasicBlock &MBB,
287
                           MachineBasicBlock::iterator MBBI,
288
                           unsigned SrcReg, bool isKill, int FrameIndex,
289
                           const TargetRegisterClass *RC,
290
                           const TargetRegisterInfo *TRI) const override;
291
292
  void loadRegFromStackSlot(MachineBasicBlock &MBB,
293
                            MachineBasicBlock::iterator MBBI,
294
                            unsigned DestReg, int FrameIndex,
295
                            const TargetRegisterClass *RC,
296
                            const TargetRegisterInfo *TRI) const override;
297
298
  unsigned getStoreOpcodeForSpill(unsigned Reg,
299
                                  const TargetRegisterClass *RC = nullptr) const;
300
301
  unsigned getLoadOpcodeForSpill(unsigned Reg,
302
                                 const TargetRegisterClass *RC = nullptr) const;
303
304
  bool
305
  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
306
307
  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
308
                     MachineRegisterInfo *MRI) const override;
309
310
  // If conversion by predication (only supported by some branch instructions).
311
  // All of the profitability checks always return true; it is always
312
  // profitable to use the predicated branches.
313
  bool isProfitableToIfCvt(MachineBasicBlock &MBB,
314
                          unsigned NumCycles, unsigned ExtraPredCycles,
315
2.79k
                          BranchProbability Probability) const override {
316
2.79k
    return true;
317
2.79k
  }
318
319
  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
320
                           unsigned NumT, unsigned ExtraT,
321
                           MachineBasicBlock &FMBB,
322
                           unsigned NumF, unsigned ExtraF,
323
                           BranchProbability Probability) const override;
324
325
  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
326
4.32k
                                 BranchProbability Probability) const override {
327
4.32k
    return true;
328
4.32k
  }
329
330
  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
331
1
                                 MachineBasicBlock &FMBB) const override {
332
1
    return false;
333
1
  }
334
335
  // Predication support.
336
  bool isPredicated(const MachineInstr &MI) const override;
337
338
  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
339
340
  bool PredicateInstruction(MachineInstr &MI,
341
                            ArrayRef<MachineOperand> Pred) const override;
342
343
  bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
344
                         ArrayRef<MachineOperand> Pred2) const override;
345
346
  bool DefinesPredicate(MachineInstr &MI,
347
                        std::vector<MachineOperand> &Pred) const override;
348
349
  bool isPredicable(const MachineInstr &MI) const override;
350
351
  // Comparison optimization.
352
353
  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
354
                      unsigned &SrcReg2, int &Mask, int &Value) const override;
355
356
  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
357
                            unsigned SrcReg2, int Mask, int Value,
358
                            const MachineRegisterInfo *MRI) const override;
359
360
361
  /// Return true if get the base operand, byte offset of an instruction and
362
  /// the memory width. Width is the size of memory that is being
363
  /// loaded/stored (e.g. 1, 2, 4, 8).
364
  bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
365
                                    const MachineOperand *&BaseOp,
366
                                    int64_t &Offset, unsigned &Width,
367
                                    const TargetRegisterInfo *TRI) const;
368
369
  /// Return true if two MIs access different memory addresses and false
370
  /// otherwise
371
  bool
372
  areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
373
                                  const MachineInstr &MIb,
374
                                  AliasAnalysis *AA = nullptr) const override;
375
376
  /// GetInstSize - Return the number of bytes of code the specified
377
  /// instruction may be.  This returns the maximum number of bytes.
378
  ///
379
  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
380
381
  void getNoop(MCInst &NopInst) const override;
382
383
  std::pair<unsigned, unsigned>
384
  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
385
386
  ArrayRef<std::pair<unsigned, const char *>>
387
  getSerializableDirectMachineOperandTargetFlags() const override;
388
389
  ArrayRef<std::pair<unsigned, const char *>>
390
  getSerializableBitmaskMachineOperandTargetFlags() const override;
391
392
  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
393
  bool expandVSXMemPseudo(MachineInstr &MI) const;
394
395
  // Lower pseudo instructions after register allocation.
396
  bool expandPostRAPseudo(MachineInstr &MI) const override;
397
398
9.86k
  static bool isVFRegister(unsigned Reg) {
399
9.86k
    return Reg >= PPC::VF0 && 
Reg <= PPC::VF315.91k
;
400
9.86k
  }
401
8.21k
  static bool isVRRegister(unsigned Reg) {
402
8.21k
    return Reg >= PPC::V0 && 
Reg <= PPC::V318.21k
;
403
8.21k
  }
404
  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
405
  static int getRecordFormOpcode(unsigned Opcode);
406
407
  bool isTOCSaveMI(const MachineInstr &MI) const;
408
409
  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
410
                            const unsigned PhiDepth) const;
411
412
  /// Return true if the output of the instruction is always a sign-extended,
413
  /// i.e. 0 to 31-th bits are same as 32-th bit.
414
496
  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
415
496
    return isSignOrZeroExtended(MI, true, depth);
416
496
  }
417
418
  /// Return true if the output of the instruction is always zero-extended,
419
  /// i.e. 0 to 31-th bits are all zeros
420
463
  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
421
463
   return isSignOrZeroExtended(MI, false, depth);
422
463
  }
423
424
  bool convertToImmediateForm(MachineInstr &MI,
425
                              MachineInstr **KilledDef = nullptr) const;
426
427
  /// Fixup killed/dead flag for register \p RegNo between instructions [\p
428
  /// StartMI, \p EndMI]. Some PostRA transformations may violate register
429
  /// killed/dead flags semantics, this function can be called to fix up. Before
430
  /// calling this function,
431
  /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
432
  /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
433
  ///    and possible definition for \p RegNo is \p StartMI or \p EndMI.
434
  /// 3. Ensure that all instructions between [\p StartMI, \p EndMI] are in same
435
  ///    basic block.
436
  void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
437
                         unsigned RegNo) const;
438
  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
439
  void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
440
                                  int64_t Imm) const;
441
442
  bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III,
443
                       bool PostRA) const;
444
445
  /// getRegNumForOperand - some operands use different numbering schemes
446
  /// for the same registers. For example, a VSX instruction may have any of
447
  /// vs0-vs63 allocated whereas an Altivec instruction could only have
448
  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
449
  /// register number needed for the opcode/operand number combination.
450
  /// The operand number argument will be useful when we need to extend this
451
  /// to instructions that use both Altivec and VSX numbering (for different
452
  /// operands).
453
  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
454
170k
                                      unsigned OpNo) {
455
170k
    int16_t regClass = Desc.OpInfo[OpNo].RegClass;
456
170k
    switch (regClass) {
457
170k
      // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
458
170k
      // VSX32-VSX63 during encoding/disassembling
459
170k
      case PPC::VSSRCRegClassID:
460
9.81k
      case PPC::VSFRCRegClassID:
461
9.81k
        if (isVFRegister(Reg))
462
682
          return PPC::VSX32 + (Reg - PPC::VF0);
463
9.13k
        break;
464
9.13k
      // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
465
9.13k
      // VSX32-VSX63 during encoding/disassembling
466
9.13k
      case PPC::VSRCRegClassID:
467
8.19k
        if (isVRRegister(Reg))
468
3.67k
          return PPC::VSX32 + (Reg - PPC::V0);
469
4.52k
        break;
470
4.52k
      // Other RegClass doesn't need mapping
471
152k
      default:
472
152k
        break;
473
166k
    }
474
166k
    return Reg;
475
166k
  }
476
477
  /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
478
  bool isBDNZ(unsigned Opcode) const;
479
480
  /// Find the hardware loop instruction used to set-up the specified loop.
481
  /// On PPC, we have two instructions used to set-up the hardware loop
482
  /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
483
  /// instructions to indicate the end of a loop.
484
  MachineInstr *findLoopInstr(MachineBasicBlock &PreHeader) const;
485
486
  /// Analyze the loop code to find the loop induction variable and compare used
487
  /// to compute the number of iterations. Currently, we analyze loop that are
488
  /// controlled using hardware loops.  In this case, the induction variable
489
  /// instruction is null.  For all other cases, this function returns true,
490
  /// which means we're unable to analyze it. \p IndVarInst and \p CmpInst will
491
  /// return new values when we can analyze the readonly loop \p L, otherwise,
492
  /// nothing got changed
493
  bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
494
                   MachineInstr *&CmpInst) const override;
495
  /// Generate code to reduce the loop iteration by one and check if the loop
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  /// is finished.  Return the value/register of the new loop count.  We need
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  /// this function when peeling off one or more iterations of a loop. This
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  /// function assumes the last iteration is peeled first.
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  unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader,
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                           MachineInstr *IndVar, MachineInstr &Cmp,
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                           SmallVectorImpl<MachineOperand> &Cond,
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                           SmallVectorImpl<MachineInstr *> &PrevInsts,
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                           unsigned Iter, unsigned MaxIter) const override;
504
};
505
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}
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#endif