Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
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//===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// A pre-emit peephole for catching opportunities introduced by late passes such
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// as MachineBlockPlacement.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-pre-emit-peephole"
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STATISTIC(NumRRConvertedInPreEmit,
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          "Number of r+r instructions converted to r+i in pre-emit peephole");
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STATISTIC(NumRemovedInPreEmit,
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          "Number of instructions deleted in pre-emit peephole");
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STATISTIC(NumberOfSelfCopies,
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          "Number of self copy instructions eliminated");
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static cl::opt<bool>
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RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
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                   cl::desc("Run pre-emit peephole optimizations."));
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namespace {
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  class PPCPreEmitPeephole : public MachineFunctionPass {
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  public:
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    static char ID;
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1.80k
    PPCPreEmitPeephole() : MachineFunctionPass(ID) {
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1.80k
      initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry());
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1.80k
    }
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1.77k
    void getAnalysisUsage(AnalysisUsage &AU) const override {
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1.77k
      MachineFunctionPass::getAnalysisUsage(AU);
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1.77k
    }
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1.77k
    MachineFunctionProperties getRequiredProperties() const override {
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1.77k
      return MachineFunctionProperties().set(
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1.77k
          MachineFunctionProperties::Property::NoVRegs);
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1.77k
    }
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    // This function removes any redundant load immediates. It has two level
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    // loops - The outer loop finds the load immediates BBI that could be used
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    // to replace following redundancy. The inner loop scans instructions that
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    // after BBI to find redundancy and update kill/dead flags accordingly. If
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    // AfterBBI is the same as BBI, it is redundant, otherwise any instructions
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    // that modify the def register of BBI would break the scanning.
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    // DeadOrKillToUnset is a pointer to the previous operand that had the
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    // kill/dead flag set. It keeps track of the def register of BBI, the use
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    // registers of AfterBBIs and the def registers of AfterBBIs.
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    bool removeRedundantLIs(MachineBasicBlock &MBB,
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16.4k
                            const TargetRegisterInfo *TRI) {
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16.4k
      LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n";
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16.4k
                 MBB.dump(); dbgs() << "\n");
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16.4k
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16.4k
      DenseSet<MachineInstr *> InstrsToErase;
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120k
      for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); 
++BBI104k
) {
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104k
        // Skip load immediate that is marked to be erased later because it
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104k
        // cannot be used to replace any other instructions.
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104k
        if (InstrsToErase.find(&*BBI) != InstrsToErase.end())
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28
          continue;
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104k
        // Skip non-load immediate.
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104k
        unsigned Opc = BBI->getOpcode();
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104k
        if (Opc != PPC::LI && 
Opc != PPC::LI8103k
&&
Opc != PPC::LIS100k
&&
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104k
            
Opc != PPC::LIS899.6k
)
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99.3k
          continue;
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4.70k
        // Skip load immediate, where the operand is a relocation (e.g., $r3 =
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4.70k
        // LI target-flags(ppc-lo) %const.0).
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4.70k
        if (!BBI->getOperand(1).isImm())
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269
          continue;
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4.43k
        assert(BBI->getOperand(0).isReg() &&
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4.43k
               "Expected a register for the first operand");
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4.43k
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4.43k
        LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump(););
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4.43k
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4.43k
        unsigned Reg = BBI->getOperand(0).getReg();
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4.43k
        int64_t Imm = BBI->getOperand(1).getImm();
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4.43k
        MachineOperand *DeadOrKillToUnset = nullptr;
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4.43k
        if (BBI->getOperand(0).isDead()) {
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2
          DeadOrKillToUnset = &BBI->getOperand(0);
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2
          LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset
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2
                            << " from load immediate " << *BBI
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2
                            << " is a unsetting candidate\n");
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2
        }
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4.43k
        // This loop scans instructions after BBI to see if there is any
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4.43k
        // redundant load immediate.
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32.7k
        for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end();
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30.8k
             
++AfterBBI28.3k
) {
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          // Track the operand that kill Reg. We would unset the kill flag of
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30.8k
          // the operand if there is a following redundant load immediate.
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          int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI);
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30.8k
          if (KillIdx != -1) {
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            assert(!DeadOrKillToUnset && "Shouldn't kill same register twice");
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            DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx);
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            LLVM_DEBUG(dbgs()
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3.95k
                       << " Kill flag of " << *DeadOrKillToUnset << " from "
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                       << *AfterBBI << " is a unsetting candidate\n");
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          }
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          if (!AfterBBI->modifiesRegister(Reg, TRI))
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            continue;
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          assert(DeadOrKillToUnset &&
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2.55k
                 "Shouldn't overwrite a register before it is killed");
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          // Finish scanning because Reg is overwritten by a non-load
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          // instruction.
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          if (AfterBBI->getOpcode() != Opc)
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1.76k
            break;
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          assert(AfterBBI->getOperand(0).isReg() &&
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785
                 "Expected a register for the first operand");
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          // Finish scanning because Reg is overwritten by a relocation or a
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          // different value.
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          if (!AfterBBI->getOperand(1).isImm() ||
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AfterBBI->getOperand(1).getImm() != Imm782
)
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            break;
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          // It loads same immediate value to the same Reg, which is redundant.
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          // We would unset kill flag in previous Reg usage to extend live range
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          // of Reg first, then remove the redundancy.
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          LLVM_DEBUG(dbgs() << " Unset dead/kill flag of " << *DeadOrKillToUnset
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                            << " from " << *DeadOrKillToUnset->getParent());
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          if (DeadOrKillToUnset->isDef())
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2
            DeadOrKillToUnset->setIsDead(false);
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          else
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            DeadOrKillToUnset->setIsKill(false);
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          DeadOrKillToUnset =
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              AfterBBI->findRegisterDefOperand(Reg, true, true, TRI);
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          if (DeadOrKillToUnset)
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            LLVM_DEBUG(dbgs()
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                       << " Dead flag of " << *DeadOrKillToUnset << " from "
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                       << *AfterBBI << " is a unsetting candidate\n");
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          InstrsToErase.insert(&*AfterBBI);
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          LLVM_DEBUG(dbgs() << " Remove redundant load immediate: ";
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                     AfterBBI->dump());
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        }
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4.43k
      }
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16.4k
      for (MachineInstr *MI : InstrsToErase) {
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        MI->eraseFromParent();
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      }
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16.4k
      NumRemovedInPreEmit += InstrsToErase.size();
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      return !InstrsToErase.empty();
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    }
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11.2k
    bool runOnMachineFunction(MachineFunction &MF) override {
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11.2k
      if (skipFunction(MF.getFunction()) || 
!RunPreEmitPeephole11.2k
)
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        return false;
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11.2k
      bool Changed = false;
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11.2k
      const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
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11.2k
      const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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11.2k
      SmallVector<MachineInstr *, 4> InstrsToErase;
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16.4k
      for (MachineBasicBlock &MBB : MF) {
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        Changed |= removeRedundantLIs(MBB, TRI);
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104k
        for (MachineInstr &MI : MBB) {
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104k
          unsigned Opc = MI.getOpcode();
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104k
          // Detect self copies - these can result from running AADB.
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104k
          if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) {
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4.48k
            const MCInstrDesc &MCID = TII->get(Opc);
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4.48k
            if (MCID.getNumOperands() == 3 &&
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4.48k
                
MI.getOperand(0).getReg() == MI.getOperand(1).getReg()3.10k
&&
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4.48k
                
MI.getOperand(0).getReg() == MI.getOperand(2).getReg()176
) {
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1
              NumberOfSelfCopies++;
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              LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
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              LLVM_DEBUG(MI.dump());
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              InstrsToErase.push_back(&MI);
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1
              continue;
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1
            }
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4.48k
            else if (MCID.getNumOperands() == 2 &&
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4.48k
                     
MI.getOperand(0).getReg() == MI.getOperand(1).getReg()1.38k
) {
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              NumberOfSelfCopies++;
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              LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
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              LLVM_DEBUG(MI.dump());
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              InstrsToErase.push_back(&MI);
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0
              continue;
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0
            }
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104k
          }
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104k
          MachineInstr *DefMIToErase = nullptr;
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104k
          if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
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            Changed = true;
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            NumRRConvertedInPreEmit++;
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737
            LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
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            LLVM_DEBUG(MI.dump());
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737
            if (DefMIToErase) {
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              InstrsToErase.push_back(DefMIToErase);
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            }
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          }
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104k
        }
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16.4k
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16.4k
        // Eliminate conditional branch based on a constant CR bit by
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16.4k
        // CRSET or CRUNSET. We eliminate the conditional branch or
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16.4k
        // convert it into an unconditional branch. Also, if the CR bit
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16.4k
        // is not used by other instructions, we eliminate CRSET as well.
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16.4k
        auto I = MBB.getFirstInstrTerminator();
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16.4k
        if (I == MBB.instr_end())
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1.77k
          continue;
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14.6k
        MachineInstr *Br = &*I;
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14.6k
        if (Br->getOpcode() != PPC::BC && 
Br->getOpcode() != PPC::BCn14.2k
)
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14.0k
          continue;
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        MachineInstr *CRSetMI = nullptr;
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        unsigned CRBit = Br->getOperand(0).getReg();
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        unsigned CRReg = getCRFromCRBit(CRBit);
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        bool SeenUse = false;
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        MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend();
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917
        for (It++; It != Er; 
It++331
) {
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719
          if (It->modifiesRegister(CRBit, TRI)) {
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388
            if ((It->getOpcode() == PPC::CRUNSET ||
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388
                 
It->getOpcode() == PPC::CRSET385
) &&
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388
                
It->getOperand(0).getReg() == CRBit6
)
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6
              CRSetMI = &*It;
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388
            break;
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388
          }
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331
          if (It->readsRegister(CRBit, TRI))
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1
            SeenUse = true;
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331
        }
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586
        if (!CRSetMI) 
continue580
;
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234
6
        unsigned CRSetOp = CRSetMI->getOpcode();
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        if ((Br->getOpcode() == PPC::BCn && 
CRSetOp == PPC::CRSET0
) ||
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            (Br->getOpcode() == PPC::BC  && CRSetOp == PPC::CRUNSET)) {
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          // Remove this branch since it cannot be taken.
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3
          InstrsToErase.push_back(Br);
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3
          MBB.removeSuccessor(Br->getOperand(1).getMBB());
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        }
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3
        else {
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3
          // This conditional branch is always taken. So, remove all branches
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3
          // and insert an unconditional branch to the destination of this.
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3
          MachineBasicBlock::iterator It = Br, Er = MBB.end();
245
7
          for (; It != Er; 
It++4
) {
246
4
            if (It->isDebugInstr()) 
continue0
;
247
4
            assert(It->isTerminator() && "Non-terminator after a terminator");
248
4
            InstrsToErase.push_back(&*It);
249
4
          }
250
3
          if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) {
251
3
            ArrayRef<MachineOperand> NoCond;
252
3
            TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr,
253
3
                              NoCond, Br->getDebugLoc());
254
3
          }
255
3
          for (auto &Succ : MBB.successors())
256
6
            if (Succ != Br->getOperand(1).getMBB()) {
257
3
              MBB.removeSuccessor(Succ);
258
3
              break;
259
3
            }
260
3
        }
261
6
262
6
        // If the CRBit is not used by another instruction, we can eliminate
263
6
        // CRSET/CRUNSET instruction.
264
6
        if (!SeenUse) {
265
5
          // We need to check use of the CRBit in successors.
266
5
          for (auto &SuccMBB : MBB.successors())
267
5
            if (SuccMBB->isLiveIn(CRBit) || 
SuccMBB->isLiveIn(CRReg)4
) {
268
1
              SeenUse = true;
269
1
              break;
270
1
            }
271
5
          if (!SeenUse)
272
4
            InstrsToErase.push_back(CRSetMI);
273
5
        }
274
6
      }
275
11.2k
      for (MachineInstr *MI : InstrsToErase) {
276
710
        LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: ");
277
710
        LLVM_DEBUG(MI->dump());
278
710
        MI->eraseFromParent();
279
710
        NumRemovedInPreEmit++;
280
710
      }
281
11.2k
      return Changed;
282
11.2k
    }
283
  };
284
}
285
286
INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole",
287
                false, false)
288
char PPCPreEmitPeephole::ID = 0;
289
290
1.80k
FunctionPass *llvm::createPPCPreEmitPeepholePass() {
291
1.80k
  return new PPCPreEmitPeephole();
292
1.80k
}