Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
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//===----- PPCQPXLoadSplat.cpp - QPX Load Splat Simplification ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The QPX vector registers overlay the scalar floating-point registers, and
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// any scalar floating-point loads splat their value across all vector lanes.
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// Thus, if we have a scalar load followed by a splat, we can remove the splat
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// (i.e. replace the load with a load-and-splat pseudo instruction).
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//
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// This pass must run after anything that might do store-to-load forwarding.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCInstrInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-qpx-load-splat"
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STATISTIC(NumSimplified, "Number of QPX load splats simplified");
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namespace {
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  struct PPCQPXLoadSplat : public MachineFunctionPass {
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    static char ID;
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1.66k
    PPCQPXLoadSplat() : MachineFunctionPass(ID) {
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      initializePPCQPXLoadSplatPass(*PassRegistry::getPassRegistry());
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    }
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    bool runOnMachineFunction(MachineFunction &Fn) override;
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    StringRef getPassName() const override {
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      return "PowerPC QPX Load Splat Simplification";
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    }
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  };
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  char PPCQPXLoadSplat::ID = 0;
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}
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INITIALIZE_PASS(PPCQPXLoadSplat, "ppc-qpx-load-splat",
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                "PowerPC QPX Load Splat Simplification",
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                false, false)
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FunctionPass *llvm::createPPCQPXLoadSplatPass() {
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  return new PPCQPXLoadSplat();
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}
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bool PPCQPXLoadSplat::runOnMachineFunction(MachineFunction &MF) {
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  if (skipFunction(MF.getFunction()))
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1
    return false;
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  bool MadeChange = false;
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  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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  for (auto MFI = MF.begin(), MFIE = MF.end(); MFI != MFIE; 
++MFI15.3k
) {
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    MachineBasicBlock *MBB = &*MFI;
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    SmallVector<MachineInstr *, 4> Splats;
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    for (auto MBBI = MBB->rbegin(); MBBI != MBB->rend(); 
++MBBI96.0k
) {
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      MachineInstr *MI = &*MBBI;
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      if (MI->hasUnmodeledSideEffects() || 
MI->isCall()89.7k
) {
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        Splats.clear();
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        continue;
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      }
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      // We're looking for a sequence like this:
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      // %f0 = LFD 0, killed %x3, implicit-def %qf0; mem:LD8[%a](tbaa=!2)
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      // %qf1 = QVESPLATI killed %qf0, 0, implicit %rm
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for (auto SI = Splats.begin(); 87.6k
SI != Splats.end();) {
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        MachineInstr *SMI = *SI;
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        unsigned SplatReg = SMI->getOperand(0).getReg();
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        unsigned SrcReg = SMI->getOperand(1).getReg();
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        if (MI->modifiesRegister(SrcReg, TRI)) {
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          switch (MI->getOpcode()) {
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          default:
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            SI = Splats.erase(SI);
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            continue;
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          case PPC::LFS:
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1
          case PPC::LFD:
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1
          case PPC::LFSU:
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1
          case PPC::LFDU:
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1
          case PPC::LFSUX:
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1
          case PPC::LFDUX:
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1
          case PPC::LFSX:
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1
          case PPC::LFDX:
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          case PPC::LFIWAX:
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          case PPC::LFIWZX:
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            if (SplatReg != SrcReg) {
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              // We need to change the load to define the scalar subregister of
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              // the QPX splat source register.
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              unsigned SubRegIndex =
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                TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg());
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              unsigned SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex);
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0
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              // Substitute both the explicit defined register, and also the
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              // implicit def of the containing QPX register.
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              MI->getOperand(0).setReg(SplatSubReg);
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              MI->substituteRegister(SrcReg, SplatReg, 0, *TRI);
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            }
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            SI = Splats.erase(SI);
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            // If SMI is directly after MI, then MBBI's base iterator is
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            // pointing at SMI.  Adjust MBBI around the call to erase SMI to
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            // avoid invalidating MBBI.
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            ++MBBI;
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            SMI->eraseFromParent();
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            --MBBI;
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            ++NumSimplified;
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            MadeChange = true;
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            continue;
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          }
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        }
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        // If this instruction defines the splat register, then we cannot move
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        // the previous definition above it. If it reads from the splat
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        // register, then it must already be alive from some previous
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        // definition, and if the splat register is different from the source
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        // register, then this definition must not be the load for which we're
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        // searching.
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        if (MI->modifiesRegister(SplatReg, TRI) ||
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            (SrcReg != SplatReg &&
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MI->readsRegister(SplatReg, TRI)0
)) {
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          SI = Splats.erase(SI);
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          continue;
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        }
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        ++SI;
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      }
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      if (MI->getOpcode() != PPC::QVESPLATI &&
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MI->getOpcode() != PPC::QVESPLATIs87.5k
&&
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MI->getOpcode() != PPC::QVESPLATIb87.5k
)
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        continue;
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      if (MI->getOperand(2).getImm() != 0)
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        continue;
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      // If there are other uses of the scalar value after this, replacing
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      // those uses might be non-trivial.
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      if (!MI->getOperand(1).isKill())
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        continue;
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      Splats.push_back(MI);
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    }
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  }
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  return MadeChange;
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}