Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Line
Count
Source (jump to first uncovered line)
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//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the PowerPC implementation of the TargetRegisterInfo
10
// class.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "PPCRegisterInfo.h"
15
#include "PPCFrameLowering.h"
16
#include "PPCInstrBuilder.h"
17
#include "PPCMachineFunctionInfo.h"
18
#include "PPCSubtarget.h"
19
#include "PPCTargetMachine.h"
20
#include "llvm/ADT/BitVector.h"
21
#include "llvm/ADT/STLExtras.h"
22
#include "llvm/ADT/Statistic.h"
23
#include "llvm/CodeGen/MachineFrameInfo.h"
24
#include "llvm/CodeGen/MachineFunction.h"
25
#include "llvm/CodeGen/MachineInstrBuilder.h"
26
#include "llvm/CodeGen/MachineModuleInfo.h"
27
#include "llvm/CodeGen/MachineRegisterInfo.h"
28
#include "llvm/CodeGen/RegisterScavenging.h"
29
#include "llvm/CodeGen/TargetFrameLowering.h"
30
#include "llvm/CodeGen/TargetInstrInfo.h"
31
#include "llvm/IR/CallingConv.h"
32
#include "llvm/IR/Constants.h"
33
#include "llvm/IR/Function.h"
34
#include "llvm/IR/Type.h"
35
#include "llvm/Support/CommandLine.h"
36
#include "llvm/Support/Debug.h"
37
#include "llvm/Support/ErrorHandling.h"
38
#include "llvm/Support/MathExtras.h"
39
#include "llvm/Support/raw_ostream.h"
40
#include "llvm/Target/TargetMachine.h"
41
#include "llvm/Target/TargetOptions.h"
42
#include <cstdlib>
43
44
using namespace llvm;
45
46
#define DEBUG_TYPE "reginfo"
47
48
#define GET_REGINFO_TARGET_DESC
49
#include "PPCGenRegisterInfo.inc"
50
51
STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
52
STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
53
54
static cl::opt<bool>
55
EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
56
         cl::desc("Enable use of a base pointer for complex stack frames"));
57
58
static cl::opt<bool>
59
AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
60
         cl::desc("Force the use of a base pointer in every function"));
61
62
static cl::opt<bool>
63
EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
64
         cl::desc("Enable spills from gpr to vsr rather than stack"));
65
66
static cl::opt<bool>
67
StackPtrConst("ppc-stack-ptr-caller-preserved",
68
                cl::desc("Consider R1 caller preserved so stack saves of "
69
                         "caller preserved registers can be LICM candidates"),
70
                cl::init(true), cl::Hidden);
71
72
static cl::opt<unsigned>
73
MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
74
                  cl::desc("Maximum search distance for definition of CR bit "
75
                           "spill on ppc"),
76
                  cl::Hidden, cl::init(100));
77
78
static unsigned offsetMinAlignForOpcode(unsigned OpC);
79
80
PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
81
  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
82
                       TM.isPPC64() ? 0 : 1,
83
                       TM.isPPC64() ? 0 : 1),
84
1.85k
    TM(TM) {
85
1.85k
  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
86
1.85k
  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
87
1.85k
  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
88
1.85k
  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
89
1.85k
  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
90
1.85k
  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
91
1.85k
  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
92
1.85k
  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
93
1.85k
  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
94
1.85k
95
1.85k
  // 64-bit
96
1.85k
  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
97
1.85k
  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
98
1.85k
  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
99
1.85k
  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
100
1.85k
  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
101
1.85k
102
1.85k
  // VSX
103
1.85k
  ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
104
1.85k
  ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
105
1.85k
  ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
106
1.85k
  ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
107
1.85k
  ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
108
1.85k
  ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
109
1.85k
  ImmToIdxMap[PPC::LXV] = PPC::LXVX;
110
1.85k
  ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
111
1.85k
  ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
112
1.85k
  ImmToIdxMap[PPC::STXV] = PPC::STXVX;
113
1.85k
  ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
114
1.85k
  ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
115
1.85k
116
1.85k
  // SPE
117
1.85k
  ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
118
1.85k
  ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
119
1.85k
  ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
120
1.85k
  ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
121
1.85k
}
122
123
/// getPointerRegClass - Return the register class to use to hold pointers.
124
/// This is used for addressing modes.
125
const TargetRegisterClass *
126
PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
127
659k
                                                                       const {
128
659k
  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
129
659k
  // when it checks for ZERO folding.
130
659k
  if (Kind == 1) {
131
496k
    if (TM.isPPC64())
132
427k
      return &PPC::G8RC_NOX0RegClass;
133
68.8k
    return &PPC::GPRC_NOR0RegClass;
134
68.8k
  }
135
162k
136
162k
  if (TM.isPPC64())
137
151k
    return &PPC::G8RCRegClass;
138
10.9k
  return &PPC::GPRCRegClass;
139
10.9k
}
140
141
const MCPhysReg*
142
224k
PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
143
224k
  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
144
224k
  if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
145
0
    if (Subtarget.hasVSX())
146
0
      return CSR_64_AllRegs_VSX_SaveList;
147
0
    if (Subtarget.hasAltivec())
148
0
      return CSR_64_AllRegs_Altivec_SaveList;
149
0
    return CSR_64_AllRegs_SaveList;
150
0
  }
151
224k
152
224k
  if (Subtarget.isDarwinABI())
153
0
    return TM.isPPC64()
154
0
               ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
155
0
                                         : CSR_Darwin64_SaveList)
156
0
               : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
157
0
                                         : CSR_Darwin32_SaveList);
158
224k
159
224k
  if (TM.isPPC64() && 
MF->getInfo<PPCFunctionInfo>()->isSplitCSR()203k
)
160
78
    return CSR_SRV464_TLS_PE_SaveList;
161
223k
162
223k
  // On PPC64, we might need to save r2 (but only if it is not reserved).
163
223k
  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
164
223k
165
223k
  // Cold calling convention CSRs.
166
223k
  if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
167
38
    if (TM.isPPC64()) {
168
38
      if (Subtarget.hasAltivec())
169
38
        return SaveR2 ? 
CSR_SVR64_ColdCC_R2_Altivec_SaveList0
170
38
                      : CSR_SVR64_ColdCC_Altivec_SaveList;
171
0
      return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
172
0
                    : CSR_SVR64_ColdCC_SaveList;
173
0
    }
174
0
    // 32-bit targets.
175
0
    if (Subtarget.hasAltivec())
176
0
      return CSR_SVR32_ColdCC_Altivec_SaveList;
177
0
    else if (Subtarget.hasSPE())
178
0
      return CSR_SVR32_ColdCC_SPE_SaveList;
179
0
    return CSR_SVR32_ColdCC_SaveList;
180
0
  }
181
223k
  // Standard calling convention CSRs.
182
223k
  if (TM.isPPC64()) {
183
203k
    if (Subtarget.hasAltivec())
184
173k
      return SaveR2 ? 
CSR_SVR464_R2_Altivec_SaveList118k
185
173k
                    : 
CSR_SVR464_Altivec_SaveList54.6k
;
186
30.1k
    return SaveR2 ? 
CSR_SVR464_R2_SaveList18.0k
187
30.1k
                  : 
CSR_SVR464_SaveList12.1k
;
188
30.1k
  }
189
20.2k
  // 32-bit targets.
190
20.2k
  if (Subtarget.hasAltivec())
191
3.72k
    return CSR_SVR432_Altivec_SaveList;
192
16.5k
  else if (Subtarget.hasSPE())
193
1.77k
    return CSR_SVR432_SPE_SaveList;
194
14.7k
  return CSR_SVR432_SaveList;
195
14.7k
}
196
197
const MCPhysReg *
198
10.5k
PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
199
10.5k
  assert(MF && "Invalid MachineFunction pointer.");
200
10.5k
  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
201
10.5k
  if (Subtarget.isDarwinABI())
202
0
    return nullptr;
203
10.5k
  if (!TM.isPPC64())
204
1.07k
    return nullptr;
205
9.49k
  if (MF->getFunction().getCallingConv() != CallingConv::CXX_FAST_TLS)
206
9.48k
    return nullptr;
207
6
  if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
208
0
    return nullptr;
209
6
210
6
  // On PPC64, we might need to save r2 (but only if it is not reserved).
211
6
  bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
212
6
  if (Subtarget.hasAltivec())
213
6
    return SaveR2
214
6
      ? 
CSR_SVR464_R2_Altivec_ViaCopy_SaveList4
215
6
      : 
CSR_SVR464_Altivec_ViaCopy_SaveList2
;
216
0
  else
217
0
    return SaveR2
218
0
      ? CSR_SVR464_R2_ViaCopy_SaveList
219
0
      : CSR_SVR464_ViaCopy_SaveList;
220
6
}
221
222
const uint32_t *
223
PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
224
2.32k
                                      CallingConv::ID CC) const {
225
2.32k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
226
2.32k
  if (CC == CallingConv::AnyReg) {
227
10
    if (Subtarget.hasVSX())
228
0
      return CSR_64_AllRegs_VSX_RegMask;
229
10
    if (Subtarget.hasAltivec())
230
0
      return CSR_64_AllRegs_Altivec_RegMask;
231
10
    return CSR_64_AllRegs_RegMask;
232
10
  }
233
2.31k
234
2.31k
  if (Subtarget.isDarwinABI())
235
0
    return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
236
0
                                                  : CSR_Darwin64_RegMask)
237
0
                        : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
238
0
                                                  : CSR_Darwin32_RegMask);
239
2.31k
  if (Subtarget.isAIXABI()) {
240
22
    assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
241
22
    return TM.isPPC64() ? 
CSR_AIX64_RegMask11
:
CSR_AIX32_RegMask11
;
242
22
  }
243
2.28k
244
2.28k
  if (CC == CallingConv::Cold) {
245
2
    return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
246
2
                                                  : 
CSR_SVR64_ColdCC_RegMask0
)
247
2
                        : 
(Subtarget.hasAltivec() 0
?
CSR_SVR32_ColdCC_Altivec_RegMask0
248
0
                                                  : (Subtarget.hasSPE()
249
0
                                                  ? CSR_SVR32_ColdCC_SPE_RegMask
250
0
                                                  : CSR_SVR32_ColdCC_RegMask));
251
2
  }
252
2.28k
253
2.28k
  return TM.isPPC64() ? 
(Subtarget.hasAltivec() 1.89k
?
CSR_SVR464_Altivec_RegMask1.49k
254
1.89k
                                                : 
CSR_SVR464_RegMask403
)
255
2.28k
                      : 
(Subtarget.hasAltivec() 388
?
CSR_SVR432_Altivec_RegMask44
256
388
                                                : (Subtarget.hasSPE()
257
344
                                                  ? 
CSR_SVR432_SPE_RegMask34
258
344
                                                  : 
CSR_SVR432_RegMask310
));
259
2.28k
}
260
261
const uint32_t*
262
8
PPCRegisterInfo::getNoPreservedMask() const {
263
8
  return CSR_NoRegs_RegMask;
264
8
}
265
266
40
void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
267
40
  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
268
120
    Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
269
40
}
270
271
34.0k
BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
272
34.0k
  BitVector Reserved(getNumRegs());
273
34.0k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
274
34.0k
  const PPCFrameLowering *TFI = getFrameLowering(MF);
275
34.0k
276
34.0k
  // The ZERO register is not really a register, but the representation of r0
277
34.0k
  // when used in instructions that treat r0 as the constant 0.
278
34.0k
  markSuperRegs(Reserved, PPC::ZERO);
279
34.0k
280
34.0k
  // The FP register is also not really a register, but is the representation
281
34.0k
  // of the frame pointer register used by ISD::FRAMEADDR.
282
34.0k
  markSuperRegs(Reserved, PPC::FP);
283
34.0k
284
34.0k
  // The BP register is also not really a register, but is the representation
285
34.0k
  // of the base pointer register used by setjmp.
286
34.0k
  markSuperRegs(Reserved, PPC::BP);
287
34.0k
288
34.0k
  // The counter registers must be reserved so that counter-based loops can
289
34.0k
  // be correctly formed (and the mtctr instructions are not DCE'd).
290
34.0k
  markSuperRegs(Reserved, PPC::CTR);
291
34.0k
  markSuperRegs(Reserved, PPC::CTR8);
292
34.0k
293
34.0k
  markSuperRegs(Reserved, PPC::R1);
294
34.0k
  markSuperRegs(Reserved, PPC::LR);
295
34.0k
  markSuperRegs(Reserved, PPC::LR8);
296
34.0k
  markSuperRegs(Reserved, PPC::RM);
297
34.0k
298
34.0k
  if (!Subtarget.isDarwinABI() || 
!Subtarget.hasAltivec()0
)
299
34.0k
    markSuperRegs(Reserved, PPC::VRSAVE);
300
34.0k
301
34.0k
  // The SVR4 ABI reserves r2 and r13
302
34.0k
  if (Subtarget.isSVR4ABI()) {
303
33.9k
    // We only reserve r2 if we need to use the TOC pointer. If we have no
304
33.9k
    // explicit uses of the TOC pointer (meaning we're a leaf function with
305
33.9k
    // no constant-pool loads, etc.) and we have no potential uses inside an
306
33.9k
    // inline asm block, then we can treat r2 has an ordinary callee-saved
307
33.9k
    // register.
308
33.9k
    const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
309
33.9k
    if (!TM.isPPC64() || 
FuncInfo->usesTOCBasePtr()30.8k
||
MF.hasInlineAsm()22.3k
)
310
12.0k
      markSuperRegs(Reserved, PPC::R2);  // System-reserved register
311
33.9k
    markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
312
33.9k
  }
313
34.0k
314
34.0k
  // Always reserve r2 on AIX for now.
315
34.0k
  // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
316
34.0k
  if (Subtarget.isAIXABI())
317
72
    markSuperRegs(Reserved, PPC::R2);  // System-reserved register
318
34.0k
319
34.0k
  // On PPC64, r13 is the thread pointer. Never allocate this register.
320
34.0k
  if (TM.isPPC64())
321
30.9k
    markSuperRegs(Reserved, PPC::R13);
322
34.0k
323
34.0k
  if (TFI->needsFP(MF))
324
468
    markSuperRegs(Reserved, PPC::R31);
325
34.0k
326
34.0k
  bool IsPositionIndependent = TM.isPositionIndependent();
327
34.0k
  if (hasBasePointer(MF)) {
328
79
    if (Subtarget.isSVR4ABI() && !TM.isPPC64() && 
IsPositionIndependent39
)
329
15
      markSuperRegs(Reserved, PPC::R29);
330
64
    else
331
64
      markSuperRegs(Reserved, PPC::R30);
332
79
  }
333
34.0k
334
34.0k
  if (Subtarget.isSVR4ABI() && 
!TM.isPPC64()33.9k
&&
IsPositionIndependent3.12k
)
335
150
    markSuperRegs(Reserved, PPC::R30);
336
34.0k
337
34.0k
  // Reserve Altivec registers when Altivec is unavailable.
338
34.0k
  if (!Subtarget.hasAltivec())
339
5.64k
    for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
340
186k
         IE = PPC::VRRCRegClass.end(); I != IE; 
++I180k
)
341
180k
      markSuperRegs(Reserved, *I);
342
34.0k
343
34.0k
  assert(checkAllSuperRegsMarked(Reserved));
344
34.0k
  return Reserved;
345
34.0k
}
346
347
12.3k
bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
348
12.3k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
349
12.3k
  const PPCInstrInfo *InstrInfo =  Subtarget.getInstrInfo();
350
12.3k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
351
12.3k
  const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
352
12.3k
353
12.3k
  // If the callee saved info is invalid we have to default to true for safety.
354
12.3k
  if (!MFI.isCalleeSavedInfoValid())
355
11.2k
    return true;
356
1.10k
357
1.10k
  // We will require the use of X-Forms because the frame is larger than what
358
1.10k
  // can be represented in signed 16 bits that fit in the immediate of a D-Form.
359
1.10k
  // If we need an X-Form then we need a register to store the address offset.
360
1.10k
  unsigned FrameSize = MFI.getStackSize();
361
1.10k
  // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
362
1.10k
  if (FrameSize & ~0x7FFF)
363
0
    return true;
364
1.10k
365
1.10k
  // The callee saved info is valid so it can be traversed.
366
1.10k
  // Checking for registers that need saving that do not have load or store
367
1.10k
  // forms where the address offset is an immediate.
368
1.79k
  
for (unsigned i = 0; 1.10k
i < Info.size();
i++693
) {
369
791
    int FrIdx = Info[i].getFrameIdx();
370
791
    unsigned Reg = Info[i].getReg();
371
791
372
791
    unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(Reg);
373
791
    if (!MFI.isFixedObjectIndex(FrIdx)) {
374
23
      // This is not a fixed object. If it requires alignment then we may still
375
23
      // need to use the XForm.
376
23
      if (offsetMinAlignForOpcode(Opcode) > 1)
377
0
        return true;
378
791
    }
379
791
380
791
    // This is eiher:
381
791
    // 1) A fixed frame index object which we know are aligned so
382
791
    // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
383
791
    // need to consider the alignement here.
384
791
    // 2) A not fixed object but in that case we now know that the min required
385
791
    // alignment is no more than 1 based on the previous check.
386
791
    if (InstrInfo->isXFormMemOp(Opcode))
387
98
      return true;
388
791
  }
389
1.10k
  
return false1.00k
;
390
1.10k
}
391
392
bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg,
393
2.51k
                                               const MachineFunction &MF) const {
394
2.51k
  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
395
2.51k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
396
2.51k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
397
2.51k
  if (!TM.isPPC64())
398
341
    return false;
399
2.17k
400
2.17k
  if (!Subtarget.isSVR4ABI())
401
0
    return false;
402
2.17k
  if (PhysReg == PPC::X2)
403
106
    // X2 is guaranteed to be preserved within a function if it is reserved.
404
106
    // The reason it's reserved is that it's the TOC pointer (and the function
405
106
    // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
406
106
    // with no TOC access), we can't claim that it is preserved.
407
106
    return (getReservedRegs(MF).test(PPC::X2));
408
2.06k
  if (StackPtrConst && (PhysReg == PPC::X1) && 
!MFI.hasVarSizedObjects()29
409
2.06k
      && 
!MFI.hasOpaqueSPAdjustment()27
)
410
27
    // The value of the stack pointer does not change within a function after
411
27
    // the prologue and before the epilogue if there are no dynamic allocations
412
27
    // and no inline asm which clobbers X1.
413
27
    return true;
414
2.03k
  return false;
415
2.03k
}
416
417
unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
418
0
                                              MachineFunction &MF) const {
419
0
  const PPCFrameLowering *TFI = getFrameLowering(MF);
420
0
  const unsigned DefaultSafety = 1;
421
0
422
0
  switch (RC->getID()) {
423
0
  default:
424
0
    return 0;
425
0
  case PPC::G8RC_NOX0RegClassID:
426
0
  case PPC::GPRC_NOR0RegClassID:
427
0
  case PPC::SPERCRegClassID:
428
0
  case PPC::SPE4RCRegClassID:
429
0
  case PPC::G8RCRegClassID:
430
0
  case PPC::GPRCRegClassID: {
431
0
    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
432
0
    return 32 - FP - DefaultSafety;
433
0
  }
434
0
  case PPC::F8RCRegClassID:
435
0
  case PPC::F4RCRegClassID:
436
0
  case PPC::QFRCRegClassID:
437
0
  case PPC::QSRCRegClassID:
438
0
  case PPC::QBRCRegClassID:
439
0
  case PPC::VRRCRegClassID:
440
0
  case PPC::VFRCRegClassID:
441
0
  case PPC::VSLRCRegClassID:
442
0
    return 32 - DefaultSafety;
443
0
  case PPC::VSRCRegClassID:
444
0
  case PPC::VSFRCRegClassID:
445
0
  case PPC::VSSRCRegClassID:
446
0
    return 64 - DefaultSafety;
447
0
  case PPC::CRRCRegClassID:
448
0
    return 8 - DefaultSafety;
449
0
  }
450
0
}
451
452
const TargetRegisterClass *
453
PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
454
111k
                                           const MachineFunction &MF) const {
455
111k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
456
111k
  if (Subtarget.hasVSX()) {
457
83.9k
    // With VSX, we can inflate various sub-register classes to the full VSX
458
83.9k
    // register set.
459
83.9k
460
83.9k
    // For Power9 we allow the user to enable GPR to vector spills.
461
83.9k
    // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
462
83.9k
    // support to spill GPRC.
463
83.9k
    if (TM.isELFv2ABI()) {
464
51.0k
      if (Subtarget.hasP9Vector() && 
EnableGPRToVecSpills16.8k
&&
465
51.0k
          
RC == &PPC::G8RCRegClass78
) {
466
36
        InflateGP8RC++;
467
36
        return &PPC::SPILLTOVSRRCRegClass;
468
36
      }
469
51.0k
      if (RC == &PPC::GPRCRegClass && 
EnableGPRToVecSpills2.25k
)
470
5
        InflateGPRC++;
471
51.0k
    }
472
83.9k
    
if (83.8k
RC == &PPC::F8RCRegClass83.8k
)
473
122
      return &PPC::VSFRCRegClass;
474
83.7k
    else if (RC == &PPC::VRRCRegClass)
475
5.83k
      return &PPC::VSRCRegClass;
476
77.9k
    else if (RC == &PPC::F4RCRegClass && 
Subtarget.hasP8Vector()1.70k
)
477
1.47k
      return &PPC::VSSRCRegClass;
478
103k
  }
479
103k
480
103k
  return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
481
103k
}
482
483
//===----------------------------------------------------------------------===//
484
// Stack Frame Processing methods
485
//===----------------------------------------------------------------------===//
486
487
/// lowerDynamicAlloc - Generate the code for allocating an object in the
488
/// current frame.  The sequence of code will be in the general form
489
///
490
///   addi   R0, SP, \#frameSize ; get the address of the previous frame
491
///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
492
///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
493
///
494
21
void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
495
21
  // Get the instruction.
496
21
  MachineInstr &MI = *II;
497
21
  // Get the instruction's basic block.
498
21
  MachineBasicBlock &MBB = *MI.getParent();
499
21
  // Get the basic block's function.
500
21
  MachineFunction &MF = *MBB.getParent();
501
21
  // Get the frame info.
502
21
  MachineFrameInfo &MFI = MF.getFrameInfo();
503
21
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
504
21
  // Get the instruction info.
505
21
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
506
21
  // Determine whether 64-bit pointers are used.
507
21
  bool LP64 = TM.isPPC64();
508
21
  DebugLoc dl = MI.getDebugLoc();
509
21
510
21
  // Get the maximum call stack size.
511
21
  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
512
21
  // Get the total frame size.
513
21
  unsigned FrameSize = MFI.getStackSize();
514
21
515
21
  // Get stack alignments.
516
21
  const PPCFrameLowering *TFI = getFrameLowering(MF);
517
21
  unsigned TargetAlign = TFI->getStackAlignment();
518
21
  unsigned MaxAlign = MFI.getMaxAlignment();
519
21
  assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
520
21
         "Maximum call-frame size not sufficiently aligned");
521
21
522
21
  // Determine the previous frame's address.  If FrameSize can't be
523
21
  // represented as 16 bits or we need special alignment, then we load the
524
21
  // previous frame's address from 0(SP).  Why not do an addis of the hi?
525
21
  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
526
21
  // Constructing the constant and adding would take 3 instructions.
527
21
  // Fortunately, a frame greater than 32K is rare.
528
21
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
529
21
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
530
21
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC14
:
GPRC7
);
531
21
532
21
  if (MaxAlign < TargetAlign && 
isInt<16>(FrameSize)17
) {
533
16
    if (LP64)
534
12
      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
535
12
        .addReg(PPC::X31)
536
12
        .addImm(FrameSize);
537
4
    else
538
4
      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
539
4
        .addReg(PPC::R31)
540
4
        .addImm(FrameSize);
541
16
  } else 
if (5
LP645
) {
542
2
    BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
543
2
      .addImm(0)
544
2
      .addReg(PPC::X1);
545
3
  } else {
546
3
    BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
547
3
      .addImm(0)
548
3
      .addReg(PPC::R1);
549
3
  }
550
21
551
21
  bool KillNegSizeReg = MI.getOperand(1).isKill();
552
21
  unsigned NegSizeReg = MI.getOperand(1).getReg();
553
21
554
21
  // Grow the stack and update the stack pointer link, then determine the
555
21
  // address of new allocated space.
556
21
  if (LP64) {
557
14
    if (MaxAlign > TargetAlign) {
558
2
      unsigned UnalNegSizeReg = NegSizeReg;
559
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
560
2
561
2
      // Unfortunately, there is no andi, only andi., and we can't insert that
562
2
      // here because we might clobber cr0 while it is live.
563
2
      BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
564
2
        .addImm(~(MaxAlign-1));
565
2
566
2
      unsigned NegSizeReg1 = NegSizeReg;
567
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
568
2
      BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
569
2
        .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
570
2
        .addReg(NegSizeReg1, RegState::Kill);
571
2
      KillNegSizeReg = true;
572
2
    }
573
14
574
14
    BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
575
14
      .addReg(Reg, RegState::Kill)
576
14
      .addReg(PPC::X1)
577
14
      .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
578
14
    BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
579
14
      .addReg(PPC::X1)
580
14
      .addImm(maxCallFrameSize);
581
14
  } else {
582
7
    if (MaxAlign > TargetAlign) {
583
2
      unsigned UnalNegSizeReg = NegSizeReg;
584
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
585
2
586
2
      // Unfortunately, there is no andi, only andi., and we can't insert that
587
2
      // here because we might clobber cr0 while it is live.
588
2
      BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
589
2
        .addImm(~(MaxAlign-1));
590
2
591
2
      unsigned NegSizeReg1 = NegSizeReg;
592
2
      NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
593
2
      BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
594
2
        .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
595
2
        .addReg(NegSizeReg1, RegState::Kill);
596
2
      KillNegSizeReg = true;
597
2
    }
598
7
599
7
    BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
600
7
      .addReg(Reg, RegState::Kill)
601
7
      .addReg(PPC::R1)
602
7
      .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
603
7
    BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
604
7
      .addReg(PPC::R1)
605
7
      .addImm(maxCallFrameSize);
606
7
  }
607
21
608
21
  // Discard the DYNALLOC instruction.
609
21
  MBB.erase(II);
610
21
}
611
612
void PPCRegisterInfo::lowerDynamicAreaOffset(
613
1
    MachineBasicBlock::iterator II) const {
614
1
  // Get the instruction.
615
1
  MachineInstr &MI = *II;
616
1
  // Get the instruction's basic block.
617
1
  MachineBasicBlock &MBB = *MI.getParent();
618
1
  // Get the basic block's function.
619
1
  MachineFunction &MF = *MBB.getParent();
620
1
  // Get the frame info.
621
1
  MachineFrameInfo &MFI = MF.getFrameInfo();
622
1
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
623
1
  // Get the instruction info.
624
1
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
625
1
626
1
  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
627
1
  bool is64Bit = TM.isPPC64();
628
1
  DebugLoc dl = MI.getDebugLoc();
629
1
  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : 
PPC::LI0
),
630
1
          MI.getOperand(0).getReg())
631
1
      .addImm(maxCallFrameSize);
632
1
  MBB.erase(II);
633
1
}
634
635
/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
636
/// reserving a whole register (R0), we scrounge for one here. This generates
637
/// code like this:
638
///
639
///   mfcr rA                  ; Move the conditional register into GPR rA.
640
///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
641
///   stw rA, FI               ; Store rA to the frame.
642
///
643
void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
644
28
                                      unsigned FrameIndex) const {
645
28
  // Get the instruction.
646
28
  MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>
647
28
  // Get the instruction's basic block.
648
28
  MachineBasicBlock &MBB = *MI.getParent();
649
28
  MachineFunction &MF = *MBB.getParent();
650
28
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
651
28
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
652
28
  DebugLoc dl = MI.getDebugLoc();
653
28
654
28
  bool LP64 = TM.isPPC64();
655
28
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
656
28
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
657
28
658
28
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC20
:
GPRC8
);
659
28
  unsigned SrcReg = MI.getOperand(0).getReg();
660
28
661
28
  // We need to store the CR in the low 4-bits of the saved value. First, issue
662
28
  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
663
28
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::MFOCRF820
:
PPC::MFOCRF8
), Reg)
664
28
      .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
665
28
666
28
  // If the saved register wasn't CR0, shift the bits left so that they are in
667
28
  // CR0's slot.
668
28
  if (SrcReg != PPC::CR0) {
669
14
    unsigned Reg1 = Reg;
670
14
    Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC7
:
GPRC7
);
671
14
672
14
    // rlwinm rA, rA, ShiftBits, 0, 31.
673
14
    BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::RLWINM87
:
PPC::RLWINM7
), Reg)
674
14
      .addReg(Reg1, RegState::Kill)
675
14
      .addImm(getEncodingValue(SrcReg) * 4)
676
14
      .addImm(0)
677
14
      .addImm(31);
678
14
  }
679
28
680
28
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::STW820
:
PPC::STW8
))
681
28
                    .addReg(Reg, RegState::Kill),
682
28
                    FrameIndex);
683
28
684
28
  // Discard the pseudo instruction.
685
28
  MBB.erase(II);
686
28
}
687
688
void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
689
28
                                      unsigned FrameIndex) const {
690
28
  // Get the instruction.
691
28
  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CR <offset>
692
28
  // Get the instruction's basic block.
693
28
  MachineBasicBlock &MBB = *MI.getParent();
694
28
  MachineFunction &MF = *MBB.getParent();
695
28
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
696
28
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
697
28
  DebugLoc dl = MI.getDebugLoc();
698
28
699
28
  bool LP64 = TM.isPPC64();
700
28
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
701
28
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
702
28
703
28
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? 
G8RC20
:
GPRC8
);
704
28
  unsigned DestReg = MI.getOperand(0).getReg();
705
28
  assert(MI.definesRegister(DestReg) &&
706
28
    "RESTORE_CR does not define its destination");
707
28
708
28
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::LWZ820
:
PPC::LWZ8
),
709
28
                              Reg), FrameIndex);
710
28
711
28
  // If the reloaded register isn't CR0, shift the bits right so that they are
712
28
  // in the right CR's slot.
713
28
  if (DestReg != PPC::CR0) {
714
0
    unsigned Reg1 = Reg;
715
0
    Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
716
0
717
0
    unsigned ShiftBits = getEncodingValue(DestReg)*4;
718
0
    // rlwinm r11, r11, 32-ShiftBits, 0, 31.
719
0
    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
720
0
             .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
721
0
             .addImm(31);
722
0
  }
723
28
724
28
  BuildMI(MBB, II, dl, TII.get(LP64 ? 
PPC::MTOCRF820
:
PPC::MTOCRF8
), DestReg)
725
28
             .addReg(Reg, RegState::Kill);
726
28
727
28
  // Discard the pseudo instruction.
728
28
  MBB.erase(II);
729
28
}
730
731
void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
732
11
                                         unsigned FrameIndex) const {
733
11
  // Get the instruction.
734
11
  MachineInstr &MI = *II;       // ; SPILL_CRBIT <SrcReg>, <offset>
735
11
  // Get the instruction's basic block.
736
11
  MachineBasicBlock &MBB = *MI.getParent();
737
11
  MachineFunction &MF = *MBB.getParent();
738
11
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
739
11
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
740
11
  const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
741
11
  DebugLoc dl = MI.getDebugLoc();
742
11
743
11
  bool LP64 = TM.isPPC64();
744
11
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
745
11
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
746
11
747
11
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : 
GPRC0
);
748
11
  unsigned SrcReg = MI.getOperand(0).getReg();
749
11
750
11
  // Search up the BB to find the definition of the CR bit.
751
11
  MachineBasicBlock::reverse_iterator Ins;
752
11
  unsigned CRBitSpillDistance = 0;
753
30
  for (Ins = MI; Ins != MBB.rend(); 
Ins++19
) {
754
30
    // Definition found.
755
30
    if (Ins->modifiesRegister(SrcReg, TRI))
756
11
      break;
757
19
    // Unable to find CR bit definition within maximum search distance.
758
19
    if (CRBitSpillDistance == MaxCRBitSpillDist) {
759
0
      Ins = MI;
760
0
      break;
761
0
    }
762
19
    // Skip debug instructions when counting CR bit spill distance.
763
19
    if (!Ins->isDebugInstr())
764
19
      CRBitSpillDistance++;
765
19
  }
766
11
767
11
  // Unable to find the definition of the CR bit in the MBB.
768
11
  if (Ins == MBB.rend())
769
0
    Ins = MI;
770
11
771
11
  // There is no need to extract the CR bit if its value is already known.
772
11
  switch (Ins->getOpcode()) {
773
11
  case PPC::CRUNSET:
774
2
    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : 
PPC::LI0
), Reg)
775
2
      .addImm(0);
776
2
    break;
777
11
  case PPC::CRSET:
778
2
    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : 
PPC::LIS0
), Reg)
779
2
      .addImm(-32768);
780
2
    break;
781
11
  default:
782
7
    // We need to move the CR field that contains the CR bit we are spilling.
783
7
    // The super register may not be explicitly defined (i.e. it can be defined
784
7
    // by a CR-logical that only defines the subreg) so we state that the CR
785
7
    // field is undef. Also, in order to preserve the kill flag on the CR bit,
786
7
    // we add it as an implicit use.
787
7
    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : 
PPC::MFOCRF0
), Reg)
788
7
      .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
789
7
      .addReg(SrcReg,
790
7
              RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
791
7
792
7
    // If the saved register wasn't CR0LT, shift the bits left so that the bit
793
7
    // to store is the first one. Mask all but that bit.
794
7
    unsigned Reg1 = Reg;
795
7
    Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : 
GPRC0
);
796
7
797
7
    // rlwinm rA, rA, ShiftBits, 0, 0.
798
7
    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : 
PPC::RLWINM0
), Reg)
799
7
      .addReg(Reg1, RegState::Kill)
800
7
      .addImm(getEncodingValue(SrcReg))
801
7
      .addImm(0).addImm(0);
802
11
  }
803
11
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : 
PPC::STW0
))
804
11
                    .addReg(Reg, RegState::Kill),
805
11
                    FrameIndex);
806
11
807
11
  // Discard the pseudo instruction.
808
11
  MBB.erase(II);
809
11
}
810
811
void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
812
6
                                      unsigned FrameIndex) const {
813
6
  // Get the instruction.
814
6
  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CRBIT <offset>
815
6
  // Get the instruction's basic block.
816
6
  MachineBasicBlock &MBB = *MI.getParent();
817
6
  MachineFunction &MF = *MBB.getParent();
818
6
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
819
6
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
820
6
  DebugLoc dl = MI.getDebugLoc();
821
6
822
6
  bool LP64 = TM.isPPC64();
823
6
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
824
6
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
825
6
826
6
  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : 
GPRC0
);
827
6
  unsigned DestReg = MI.getOperand(0).getReg();
828
6
  assert(MI.definesRegister(DestReg) &&
829
6
    "RESTORE_CRBIT does not define its destination");
830
6
831
6
  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : 
PPC::LWZ0
),
832
6
                              Reg), FrameIndex);
833
6
834
6
  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
835
6
836
6
  unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : 
GPRC0
);
837
6
  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : 
PPC::MFOCRF0
), RegO)
838
6
          .addReg(getCRFromCRBit(DestReg));
839
6
840
6
  unsigned ShiftBits = getEncodingValue(DestReg);
841
6
  // rlwimi r11, r10, 32-ShiftBits, ..., ...
842
6
  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : 
PPC::RLWIMI0
), RegO)
843
6
      .addReg(RegO, RegState::Kill)
844
6
      .addReg(Reg, RegState::Kill)
845
6
      .addImm(ShiftBits ? 32 - ShiftBits : 
00
)
846
6
      .addImm(ShiftBits)
847
6
      .addImm(ShiftBits);
848
6
849
6
  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : 
PPC::MTOCRF0
),
850
6
          getCRFromCRBit(DestReg))
851
6
      .addReg(RegO, RegState::Kill)
852
6
      // Make sure we have a use dependency all the way through this
853
6
      // sequence of instructions. We can't have the other bits in the CR
854
6
      // modified in between the mfocrf and the mtocrf.
855
6
      .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
856
6
857
6
  // Discard the pseudo instruction.
858
6
  MBB.erase(II);
859
6
}
860
861
void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
862
0
                                          unsigned FrameIndex) const {
863
0
  // Get the instruction.
864
0
  MachineInstr &MI = *II;       // ; SPILL_VRSAVE <SrcReg>, <offset>
865
0
  // Get the instruction's basic block.
866
0
  MachineBasicBlock &MBB = *MI.getParent();
867
0
  MachineFunction &MF = *MBB.getParent();
868
0
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
869
0
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
870
0
  DebugLoc dl = MI.getDebugLoc();
871
0
872
0
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
873
0
  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
874
0
  unsigned SrcReg = MI.getOperand(0).getReg();
875
0
876
0
  BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
877
0
      .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
878
0
879
0
  addFrameReference(
880
0
      BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
881
0
      FrameIndex);
882
0
883
0
  // Discard the pseudo instruction.
884
0
  MBB.erase(II);
885
0
}
886
887
void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
888
0
                                         unsigned FrameIndex) const {
889
0
  // Get the instruction.
890
0
  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_VRSAVE <offset>
891
0
  // Get the instruction's basic block.
892
0
  MachineBasicBlock &MBB = *MI.getParent();
893
0
  MachineFunction &MF = *MBB.getParent();
894
0
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
895
0
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
896
0
  DebugLoc dl = MI.getDebugLoc();
897
0
898
0
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
899
0
  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
900
0
  unsigned DestReg = MI.getOperand(0).getReg();
901
0
  assert(MI.definesRegister(DestReg) &&
902
0
    "RESTORE_VRSAVE does not define its destination");
903
0
904
0
  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
905
0
                              Reg), FrameIndex);
906
0
907
0
  BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
908
0
             .addReg(Reg, RegState::Kill);
909
0
910
0
  // Discard the pseudo instruction.
911
0
  MBB.erase(II);
912
0
}
913
914
bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
915
2.49k
                                           unsigned Reg, int &FrameIdx) const {
916
2.49k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
917
2.49k
  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
918
2.49k
  // ABI, return true to prevent allocating an additional frame slot.
919
2.49k
  // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
920
2.49k
  // is arbitrary and will be subsequently ignored.  For 32-bit, we have
921
2.49k
  // previously created the stack slot if needed, so return its FrameIdx.
922
2.49k
  if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
923
99
    if (TM.isPPC64())
924
80
      FrameIdx = 0;
925
19
    else {
926
19
      const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
927
19
      FrameIdx = FI->getCRSpillFrameIndex();
928
19
    }
929
99
    return true;
930
99
  }
931
2.39k
  return false;
932
2.39k
}
933
934
// If the offset must be a multiple of some value, return what that value is.
935
11.3k
static unsigned offsetMinAlignForOpcode(unsigned OpC) {
936
11.3k
  switch (OpC) {
937
11.3k
  default:
938
7.36k
    return 1;
939
11.3k
  case PPC::LWA:
940
3.64k
  case PPC::LWA_32:
941
3.64k
  case PPC::LD:
942
3.64k
  case PPC::LDU:
943
3.64k
  case PPC::STD:
944
3.64k
  case PPC::STDU:
945
3.64k
  case PPC::DFLOADf32:
946
3.64k
  case PPC::DFLOADf64:
947
3.64k
  case PPC::DFSTOREf32:
948
3.64k
  case PPC::DFSTOREf64:
949
3.64k
  case PPC::LXSD:
950
3.64k
  case PPC::LXSSP:
951
3.64k
  case PPC::STXSD:
952
3.64k
  case PPC::STXSSP:
953
3.64k
    return 4;
954
3.64k
  case PPC::EVLDD:
955
54
  case PPC::EVSTDD:
956
54
    return 8;
957
290
  case PPC::LXV:
958
290
  case PPC::STXV:
959
290
    return 16;
960
11.3k
  }
961
11.3k
}
962
963
// If the offset must be a multiple of some value, return what that value is.
964
11.3k
static unsigned offsetMinAlign(const MachineInstr &MI) {
965
11.3k
  unsigned OpC = MI.getOpcode();
966
11.3k
  return offsetMinAlignForOpcode(OpC);
967
11.3k
}
968
969
// Return the OffsetOperandNo given the FIOperandNum (and the instruction).
970
static unsigned getOffsetONFromFION(const MachineInstr &MI,
971
12.1k
                                    unsigned FIOperandNum) {
972
12.1k
  // Take into account whether it's an add or mem instruction
973
12.1k
  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 
111.1k
:
21.02k
;
974
12.1k
  if (MI.isInlineAsm())
975
0
    OffsetOperandNo = FIOperandNum - 1;
976
12.1k
  else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
977
12.1k
           
MI.getOpcode() == TargetOpcode::PATCHPOINT12.1k
)
978
16
    OffsetOperandNo = FIOperandNum + 1;
979
12.1k
980
12.1k
  return OffsetOperandNo;
981
12.1k
}
982
983
void
984
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
985
                                     int SPAdj, unsigned FIOperandNum,
986
10.1k
                                     RegScavenger *RS) const {
987
10.1k
  assert(SPAdj == 0 && "Unexpected");
988
10.1k
989
10.1k
  // Get the instruction.
990
10.1k
  MachineInstr &MI = *II;
991
10.1k
  // Get the instruction's basic block.
992
10.1k
  MachineBasicBlock &MBB = *MI.getParent();
993
10.1k
  // Get the basic block's function.
994
10.1k
  MachineFunction &MF = *MBB.getParent();
995
10.1k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
996
10.1k
  // Get the instruction info.
997
10.1k
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
998
10.1k
  // Get the frame info.
999
10.1k
  MachineFrameInfo &MFI = MF.getFrameInfo();
1000
10.1k
  DebugLoc dl = MI.getDebugLoc();
1001
10.1k
1002
10.1k
  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1003
10.1k
1004
10.1k
  // Get the frame index.
1005
10.1k
  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
1006
10.1k
1007
10.1k
  // Get the frame pointer save index.  Users of this index are primarily
1008
10.1k
  // DYNALLOC instructions.
1009
10.1k
  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1010
10.1k
  int FPSI = FI->getFramePointerSaveIndex();
1011
10.1k
  // Get the instruction opcode.
1012
10.1k
  unsigned OpC = MI.getOpcode();
1013
10.1k
1014
10.1k
  if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
1015
1
    lowerDynamicAreaOffset(II);
1016
1
    return;
1017
1
  }
1018
10.1k
1019
10.1k
  // Special case for dynamic alloca.
1020
10.1k
  if (FPSI && 
FrameIndex == FPSI1.20k
&&
1021
10.1k
      
(21
OpC == PPC::DYNALLOC21
||
OpC == PPC::DYNALLOC814
)) {
1022
21
    lowerDynamicAlloc(II);
1023
21
    return;
1024
21
  }
1025
10.1k
1026
10.1k
  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1027
10.1k
  if (OpC == PPC::SPILL_CR) {
1028
28
    lowerCRSpilling(II, FrameIndex);
1029
28
    return;
1030
10.1k
  } else if (OpC == PPC::RESTORE_CR) {
1031
28
    lowerCRRestore(II, FrameIndex);
1032
28
    return;
1033
10.0k
  } else if (OpC == PPC::SPILL_CRBIT) {
1034
11
    lowerCRBitSpilling(II, FrameIndex);
1035
11
    return;
1036
10.0k
  } else if (OpC == PPC::RESTORE_CRBIT) {
1037
6
    lowerCRBitRestore(II, FrameIndex);
1038
6
    return;
1039
10.0k
  } else if (OpC == PPC::SPILL_VRSAVE) {
1040
0
    lowerVRSAVESpilling(II, FrameIndex);
1041
0
    return;
1042
10.0k
  } else if (OpC == PPC::RESTORE_VRSAVE) {
1043
0
    lowerVRSAVERestore(II, FrameIndex);
1044
0
    return;
1045
0
  }
1046
10.0k
1047
10.0k
  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1048
10.0k
  MI.getOperand(FIOperandNum).ChangeToRegister(
1049
10.0k
    FrameIndex < 0 ? 
getBaseRegister(MF)5.55k
:
getFrameRegister(MF)4.50k
, false);
1050
10.0k
1051
10.0k
  // If the instruction is not present in ImmToIdxMap, then it has no immediate
1052
10.0k
  // form (and must be r+r).
1053
10.0k
  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1054
10.0k
                   
OpC != TargetOpcode::PATCHPOINT10.0k
&&
!ImmToIdxMap.count(OpC)10.0k
;
1055
10.0k
1056
10.0k
  // Now add the frame object offset to the offset from r1.
1057
10.0k
  int Offset = MFI.getObjectOffset(FrameIndex);
1058
10.0k
  Offset += MI.getOperand(OffsetOperandNo).getImm();
1059
10.0k
1060
10.0k
  // If we're not using a Frame Pointer that has been set to the value of the
1061
10.0k
  // SP before having the stack size subtracted from it, then add the stack size
1062
10.0k
  // to Offset to get the correct offset.
1063
10.0k
  // Naked functions have stack size 0, although getStackSize may not reflect
1064
10.0k
  // that because we didn't call all the pieces that compute it for naked
1065
10.0k
  // functions.
1066
10.0k
  if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
1067
10.0k
    if (!(hasBasePointer(MF) && 
FrameIndex < 0284
))
1068
9.85k
      Offset += MFI.getStackSize();
1069
10.0k
  }
1070
10.0k
1071
10.0k
  // If we can, encode the offset directly into the instruction.  If this is a
1072
10.0k
  // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
1073
10.0k
  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1074
10.0k
  // clear can be encoded.  This is extremely uncommon, because normally you
1075
10.0k
  // only "std" to a stack slot that is at least 4-byte aligned, but it can
1076
10.0k
  // happen in invalid code.
1077
10.0k
  assert(OpC != PPC::DBG_VALUE &&
1078
10.0k
         "This should be handled in a target-independent way");
1079
10.0k
  bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || 
OpC == PPC::EVLDD10.0k
) ?
1080
49
                            isUInt<8>(Offset) :
1081
10.0k
                            
isInt<16>(Offset)10.0k
;
1082
10.0k
  if (!noImmForm && 
(9.58k
(9.58k
OffsetFitsMnemonic9.58k
&&
1083
9.58k
                      
((Offset % offsetMinAlign(MI)) == 0)9.52k
) ||
1084
9.58k
                     
OpC == TargetOpcode::STACKMAP65
||
1085
9.58k
                     
OpC == TargetOpcode::PATCHPOINT65
)) {
1086
9.52k
    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1087
9.52k
    return;
1088
9.52k
  }
1089
540
1090
540
  // The offset doesn't fit into a single register, scavenge one to build the
1091
540
  // offset in.
1092
540
1093
540
  bool is64Bit = TM.isPPC64();
1094
540
  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1095
540
  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1096
540
  const TargetRegisterClass *RC = is64Bit ? 
G8RC529
:
GPRC11
;
1097
540
  unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
1098
540
           SReg = MF.getRegInfo().createVirtualRegister(RC);
1099
540
1100
540
  // Insert a set of rA with the full offset value before the ld, st, or add
1101
540
  if (isInt<16>(Offset))
1102
482
    BuildMI(MBB, II, dl, TII.get(is64Bit ? 
PPC::LI8478
:
PPC::LI4
), SReg)
1103
482
      .addImm(Offset);
1104
58
  else {
1105
58
    BuildMI(MBB, II, dl, TII.get(is64Bit ? 
PPC::LIS851
:
PPC::LIS7
), SRegHi)
1106
58
      .addImm(Offset >> 16);
1107
58
    BuildMI(MBB, II, dl, TII.get(is64Bit ? 
PPC::ORI851
:
PPC::ORI7
), SReg)
1108
58
      .addReg(SRegHi, RegState::Kill)
1109
58
      .addImm(Offset);
1110
58
  }
1111
540
1112
540
  // Convert into indexed form of the instruction:
1113
540
  //
1114
540
  //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1115
540
  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1116
540
  unsigned OperandBase;
1117
540
1118
540
  if (noImmForm)
1119
475
    OperandBase = 1;
1120
65
  else if (OpC != TargetOpcode::INLINEASM &&
1121
65
           OpC != TargetOpcode::INLINEASM_BR) {
1122
65
    assert(ImmToIdxMap.count(OpC) &&
1123
65
           "No indexed form of load or store available!");
1124
65
    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
1125
65
    MI.setDesc(TII.get(NewOpcode));
1126
65
    OperandBase = 1;
1127
65
  } else {
1128
0
    OperandBase = OffsetOperandNo;
1129
0
  }
1130
540
1131
540
  unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
1132
540
  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1133
540
  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1134
540
}
1135
1136
34.2k
Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1137
34.2k
  const PPCFrameLowering *TFI = getFrameLowering(MF);
1138
34.2k
1139
34.2k
  if (!TM.isPPC64())
1140
5.66k
    return TFI->hasFP(MF) ? 
PPC::R31124
:
PPC::R15.54k
;
1141
28.5k
  else
1142
28.5k
    return TFI->hasFP(MF) ? 
PPC::X31997
:
PPC::X127.5k
;
1143
34.2k
}
1144
1145
30.0k
Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1146
30.0k
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1147
30.0k
  if (!hasBasePointer(MF))
1148
29.7k
    return getFrameRegister(MF);
1149
354
1150
354
  if (TM.isPPC64())
1151
267
    return PPC::X30;
1152
87
1153
87
  if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1154
40
    return PPC::R29;
1155
47
1156
47
  return PPC::R30;
1157
47
}
1158
1159
164k
bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1160
164k
  if (!EnableBasePointer)
1161
0
    return false;
1162
164k
  if (AlwaysBasePointer)
1163
48
    return true;
1164
164k
1165
164k
  // If we need to realign the stack, then the stack pointer can no longer
1166
164k
  // serve as an offset into the caller's stack space. As a result, we need a
1167
164k
  // base pointer.
1168
164k
  return needsStackRealignment(MF);
1169
164k
}
1170
1171
/// Returns true if the instruction's frame index
1172
/// reference would be better served by a base register other than FP
1173
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1174
/// references it should create new base registers for.
1175
bool PPCRegisterInfo::
1176
3.81k
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1177
3.81k
  assert(Offset < 0 && "Local offset must be negative");
1178
3.81k
1179
3.81k
  // It's the load/store FI references that cause issues, as it can be difficult
1180
3.81k
  // to materialize the offset if it won't fit in the literal field. Estimate
1181
3.81k
  // based on the size of the local frame and some conservative assumptions
1182
3.81k
  // about the rest of the stack frame (note, this is pre-regalloc, so
1183
3.81k
  // we don't know everything for certain yet) whether this offset is likely
1184
3.81k
  // to be out of range of the immediate. Return true if so.
1185
3.81k
1186
3.81k
  // We only generate virtual base registers for loads and stores that have
1187
3.81k
  // an r+i form. Return false for everything else.
1188
3.81k
  unsigned OpC = MI->getOpcode();
1189
3.81k
  if (!ImmToIdxMap.count(OpC))
1190
8
    return false;
1191
3.80k
1192
3.80k
  // Don't generate a new virtual base register just to add zero to it.
1193
3.80k
  if ((OpC == PPC::ADDI || 
OpC == PPC::ADDI83.70k
) &&
1194
3.80k
      
MI->getOperand(2).getImm() == 0760
)
1195
710
    return false;
1196
3.09k
1197
3.09k
  MachineBasicBlock &MBB = *MI->getParent();
1198
3.09k
  MachineFunction &MF = *MBB.getParent();
1199
3.09k
  const PPCFrameLowering *TFI = getFrameLowering(MF);
1200
3.09k
  unsigned StackEst = TFI->determineFrameLayout(MF, true);
1201
3.09k
1202
3.09k
  // If we likely don't need a stack frame, then we probably don't need a
1203
3.09k
  // virtual base register either.
1204
3.09k
  if (!StackEst)
1205
1.27k
    return false;
1206
1.82k
1207
1.82k
  // Estimate an offset from the stack pointer.
1208
1.82k
  // The incoming offset is relating to the SP at the start of the function,
1209
1.82k
  // but when we access the local it'll be relative to the SP after local
1210
1.82k
  // allocation, so adjust our SP-relative offset by that allocation size.
1211
1.82k
  Offset += StackEst;
1212
1.82k
1213
1.82k
  // The frame pointer will point to the end of the stack, so estimate the
1214
1.82k
  // offset as the difference between the object offset and the FP location.
1215
1.82k
  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1216
1.82k
}
1217
1218
/// Insert defining instruction(s) for BaseReg to
1219
/// be a pointer to FrameIdx at the beginning of the basic block.
1220
void PPCRegisterInfo::
1221
materializeFrameBaseRegister(MachineBasicBlock *MBB,
1222
                             unsigned BaseReg, int FrameIdx,
1223
3
                             int64_t Offset) const {
1224
3
  unsigned ADDriOpc = TM.isPPC64() ? 
PPC::ADDI82
:
PPC::ADDI1
;
1225
3
1226
3
  MachineBasicBlock::iterator Ins = MBB->begin();
1227
3
  DebugLoc DL;                  // Defaults to "unknown"
1228
3
  if (Ins != MBB->end())
1229
3
    DL = Ins->getDebugLoc();
1230
3
1231
3
  const MachineFunction &MF = *MBB->getParent();
1232
3
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1233
3
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1234
3
  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1235
3
  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1236
3
  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1237
3
1238
3
  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1239
3
    .addFrameIndex(FrameIdx).addImm(Offset);
1240
3
}
1241
1242
void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1243
98
                                        int64_t Offset) const {
1244
98
  unsigned FIOperandNum = 0;
1245
294
  while (!MI.getOperand(FIOperandNum).isFI()) {
1246
196
    ++FIOperandNum;
1247
196
    assert(FIOperandNum < MI.getNumOperands() &&
1248
196
           "Instr doesn't have FrameIndex operand!");
1249
196
  }
1250
98
1251
98
  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1252
98
  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1253
98
  Offset += MI.getOperand(OffsetOperandNo).getImm();
1254
98
  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1255
98
1256
98
  MachineBasicBlock &MBB = *MI.getParent();
1257
98
  MachineFunction &MF = *MBB.getParent();
1258
98
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1259
98
  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1260
98
  const MCInstrDesc &MCID = MI.getDesc();
1261
98
  MachineRegisterInfo &MRI = MF.getRegInfo();
1262
98
  MRI.constrainRegClass(BaseReg,
1263
98
                        TII.getRegClass(MCID, FIOperandNum, this, MF));
1264
98
}
1265
1266
bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1267
                                         unsigned BaseReg,
1268
1.92k
                                         int64_t Offset) const {
1269
1.92k
  unsigned FIOperandNum = 0;
1270
5.71k
  while (!MI->getOperand(FIOperandNum).isFI()) {
1271
3.79k
    ++FIOperandNum;
1272
3.79k
    assert(FIOperandNum < MI->getNumOperands() &&
1273
3.79k
           "Instr doesn't have FrameIndex operand!");
1274
3.79k
  }
1275
1.92k
1276
1.92k
  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1277
1.92k
  Offset += MI->getOperand(OffsetOperandNo).getImm();
1278
1.92k
1279
1.92k
  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1280
1.92k
         MI->getOpcode() == TargetOpcode::STACKMAP ||
1281
1.92k
         MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1282
1.92k
         (isInt<16>(Offset) && 
(Offset % offsetMinAlign(*MI)) == 01.80k
);
1283
1.92k
}