Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
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//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "llvm/ADT/DenseMap.h"
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#define GET_REGINFO_HEADER
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#include "PPCGenRegisterInfo.inc"
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namespace llvm {
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class PPCTargetMachine;
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inline static unsigned getCRFromCRBit(unsigned SrcReg) {
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612
  unsigned Reg = 0;
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  if (SrcReg == PPC::CR0LT || 
SrcReg == PPC::CR0GT609
||
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612
      
SrcReg == PPC::CR0EQ559
||
SrcReg == PPC::CR0UN339
)
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273
    Reg = PPC::CR0;
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339
  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
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339
           
SrcReg == PPC::CR1EQ338
||
SrcReg == PPC::CR1UN335
)
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4
    Reg = PPC::CR1;
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  else if (SrcReg == PPC::CR2LT || 
SrcReg == PPC::CR2GT328
||
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SrcReg == PPC::CR2EQ325
||
SrcReg == PPC::CR2UN322
)
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    Reg = PPC::CR2;
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  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
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           SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
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0
    Reg = PPC::CR3;
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321
  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
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           SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
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0
    Reg = PPC::CR4;
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321
  else if (SrcReg == PPC::CR5LT || 
SrcReg == PPC::CR5GT4
||
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SrcReg == PPC::CR5EQ0
||
SrcReg == PPC::CR5UN0
)
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    Reg = PPC::CR5;
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0
  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
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0
           SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
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0
    Reg = PPC::CR6;
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0
  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
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           SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
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0
    Reg = PPC::CR7;
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  assert(Reg != 0 && "Invalid CR bit register");
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  return Reg;
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}
Unexecuted instantiation: PPCBoolRetToInt.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCAsmPrinter.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCBranchSelector.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCCallingConv.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCCCState.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCHazardRecognizers.cpp:llvm::getCRFromCRBit(unsigned int)
PPCInstrInfo.cpp:llvm::getCRFromCRBit(unsigned int)
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Source
26
1
inline static unsigned getCRFromCRBit(unsigned SrcReg) {
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1
  unsigned Reg = 0;
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1
  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
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1
      SrcReg == PPC::CR0EQ || 
SrcReg == PPC::CR0UN0
)
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    Reg = PPC::CR0;
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0
  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
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0
           SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
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0
    Reg = PPC::CR1;
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0
  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
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           SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
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0
    Reg = PPC::CR2;
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0
  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
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           SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
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    Reg = PPC::CR3;
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0
  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
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           SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
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    Reg = PPC::CR4;
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  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
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           SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
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    Reg = PPC::CR5;
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0
  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
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           SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
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    Reg = PPC::CR6;
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0
  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
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           SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
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    Reg = PPC::CR7;
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1
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  assert(Reg != 0 && "Invalid CR bit register");
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  return Reg;
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}
Unexecuted instantiation: PPCISelDAGToDAG.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCISelLowering.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCEarlyReturn.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCFastISel.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCFrameLowering.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCLoopPreIncPrep.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCMCInstLower.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCMIPeephole.cpp:llvm::getCRFromCRBit(unsigned int)
PPCRegisterInfo.cpp:llvm::getCRFromCRBit(unsigned int)
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inline static unsigned getCRFromCRBit(unsigned SrcReg) {
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  unsigned Reg = 0;
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  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
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      SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
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    Reg = PPC::CR0;
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  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
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SrcReg == PPC::CR1EQ24
||
SrcReg == PPC::CR1UN24
)
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    Reg = PPC::CR1;
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  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
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           SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
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    Reg = PPC::CR2;
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  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
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           SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
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    Reg = PPC::CR3;
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  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
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           SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
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    Reg = PPC::CR4;
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  else if (SrcReg == PPC::CR5LT || 
SrcReg == PPC::CR5GT4
||
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SrcReg == PPC::CR5EQ0
||
SrcReg == PPC::CR5UN0
)
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    Reg = PPC::CR5;
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  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
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           SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
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    Reg = PPC::CR6;
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  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
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           SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
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    Reg = PPC::CR7;
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  assert(Reg != 0 && "Invalid CR bit register");
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  return Reg;
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}
Unexecuted instantiation: PPCQPXLoadSplat.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCSubtarget.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCTargetMachine.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCTargetTransformInfo.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCTOCRegDeps.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCTLSDynamicCall.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCVSXCopy.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCReduceCRLogicals.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCVSXFMAMutate.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCVSXSwapRemoval.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCExpandISEL.cpp:llvm::getCRFromCRBit(unsigned int)
PPCPreEmitPeephole.cpp:llvm::getCRFromCRBit(unsigned int)
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inline static unsigned getCRFromCRBit(unsigned SrcReg) {
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  unsigned Reg = 0;
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  if (SrcReg == PPC::CR0LT || 
SrcReg == PPC::CR0GT583
||
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SrcReg == PPC::CR0EQ533
||
SrcReg == PPC::CR0UN314
)
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    Reg = PPC::CR0;
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  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
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           SrcReg == PPC::CR1EQ || 
SrcReg == PPC::CR1UN311
)
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    Reg = PPC::CR1;
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  else if (SrcReg == PPC::CR2LT || 
SrcReg == PPC::CR2GT304
||
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SrcReg == PPC::CR2EQ301
||
SrcReg == PPC::CR2UN298
)
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    Reg = PPC::CR2;
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  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
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           SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
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    Reg = PPC::CR3;
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  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
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           SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
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    Reg = PPC::CR4;
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  else if (SrcReg == PPC::CR5LT || 
SrcReg == PPC::CR5GT0
||
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SrcReg == PPC::CR5EQ0
||
SrcReg == PPC::CR5UN0
)
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    Reg = PPC::CR5;
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  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
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           SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
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    Reg = PPC::CR6;
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  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
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           SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
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    Reg = PPC::CR7;
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  assert(Reg != 0 && "Invalid CR bit register");
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  return Reg;
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}
Unexecuted instantiation: PPCInstPrinter.cpp:llvm::getCRFromCRBit(unsigned int)
Unexecuted instantiation: PPCMCCodeEmitter.cpp:llvm::getCRFromCRBit(unsigned int)
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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  DenseMap<unsigned, unsigned> ImmToIdxMap;
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  const PPCTargetMachine &TM;
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public:
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  PPCRegisterInfo(const PPCTargetMachine &TM);
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  /// getPointerRegClass - Return the register class to use to hold pointers.
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  /// This is used for addressing modes.
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  const TargetRegisterClass *
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  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
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  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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                               MachineFunction &MF) const override;
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  const TargetRegisterClass *
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  getLargestLegalSuperClass(const TargetRegisterClass *RC,
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                            const MachineFunction &MF) const override;
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  /// Code Generation virtual methods...
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  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
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  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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                                       CallingConv::ID CC) const override;
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  const uint32_t *getNoPreservedMask() const override;
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  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
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  BitVector getReservedRegs(const MachineFunction &MF) const override;
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  bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
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  /// We require the register scavenger.
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32.0k
  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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32.0k
    return true;
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32.0k
  }
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  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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21.9k
  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
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21.9k
    return true;
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21.9k
  }
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11.1k
  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
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11.1k
    return true;
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11.1k
  }
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  void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
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  void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
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  void lowerCRSpilling(MachineBasicBlock::iterator II,
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                       unsigned FrameIndex) const;
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  void lowerCRRestore(MachineBasicBlock::iterator II,
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                      unsigned FrameIndex) const;
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  void lowerCRBitSpilling(MachineBasicBlock::iterator II,
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                          unsigned FrameIndex) const;
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  void lowerCRBitRestore(MachineBasicBlock::iterator II,
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                         unsigned FrameIndex) const;
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  void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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                           unsigned FrameIndex) const;
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  void lowerVRSAVERestore(MachineBasicBlock::iterator II,
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                          unsigned FrameIndex) const;
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  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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                            int &FrameIdx) const override;
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  void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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                           unsigned FIOperandNum,
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                           RegScavenger *RS = nullptr) const override;
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  // Support for virtual base registers.
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  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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                                    unsigned BaseReg, int FrameIdx,
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                                    int64_t Offset) const override;
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  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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                         int64_t Offset) const override;
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  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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                          int64_t Offset) const override;
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  // Debug information queries.
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  Register getFrameRegister(const MachineFunction &MF) const override;
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  // Base pointer (stack realignment) support.
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  Register getBaseRegister(const MachineFunction &MF) const;
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  bool hasBasePointer(const MachineFunction &MF) const;
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  /// stripRegisterPrefix - This method strips the character prefix from a
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  /// register name so that only the number is left.  Used by for linux asm.
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140k
  static const char *stripRegisterPrefix(const char *RegName) {
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140k
    switch (RegName[0]) {
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140k
      case 'r':
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129k
      case 'f':
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129k
      case 'q': // for QPX
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129k
      case 'v':
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129k
        if (RegName[1] == 's')
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7.71k
          return RegName + 2;
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121k
        return RegName + 1;
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121k
      
case 'c': if (4.19k
RegName[1] == 'r'4.19k
)
return RegName + 24.19k
;
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6.71k
    }
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6.71k
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6.71k
    return RegName;
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6.71k
  }
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};
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} // end namespace llvm
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#endif