Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
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//===-- PPCTOCRegDeps.cpp - Add Extra TOC Register Dependencies -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// When resolving an address using the ELF ABI TOC pointer, two relocations are
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// generally required: one for the high part and one for the low part. Only
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// the high part generally explicitly depends on r2 (the TOC pointer). And, so,
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// we might produce code like this:
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//
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// .Ltmp526:
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//         addis 3, 2, .LC12@toc@ha
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// .Ltmp1628:
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//         std 2, 40(1)
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//         ld 5, 0(27)
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//         ld 2, 8(27)
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//         ld 11, 16(27)
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//         ld 3, .LC12@toc@l(3)
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//         rldicl 4, 4, 0, 32
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//         mtctr 5
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//         bctrl
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//         ld 2, 40(1)
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//
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// And there is nothing wrong with this code, as such, but there is a linker bug
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// in binutils (https://sourceware.org/bugzilla/show_bug.cgi?id=18414) that will
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// misoptimize this code sequence to this:
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//         nop
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//         std     r2,40(r1)
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//         ld      r5,0(r27)
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//         ld      r2,8(r27)
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//         ld      r11,16(r27)
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//         ld      r3,-32472(r2)
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//         clrldi  r4,r4,32
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//         mtctr   r5
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//         bctrl
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//         ld      r2,40(r1)
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// because the linker does not know (and does not check) that the value in r2
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// changed in between the instruction using the .LC12@toc@ha (TOC-relative)
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// relocation and the instruction using the .LC12@toc@l(3) relocation.
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// Because it finds these instructions using the relocations (and not by
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// scanning the instructions), it has been asserted that there is no good way
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// to detect the change of r2 in between. As a result, this bug may never be
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// fixed (i.e. it may become part of the definition of the ABI). GCC was
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// updated to add extra dependencies on r2 to instructions using the @toc@l
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// relocations to avoid this problem, and we'll do the same here.
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//
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// This is done as a separate pass because:
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//  1. These extra r2 dependencies are not really properties of the
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//     instructions, but rather due to a linker bug, and maybe one day we'll be
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//     able to get rid of them when targeting linkers without this bug (and,
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//     thus, keeping the logic centralized here will make that
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//     straightforward).
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//  2. There are ISel-level peephole optimizations that propagate the @toc@l
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//     relocations to some user instructions, and so the exta dependencies do
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//     not apply only to a fixed set of instructions (without undesirable
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//     definition replication).
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCPredicates.h"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCInstrInfo.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-toc-reg-deps"
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namespace {
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  // PPCTOCRegDeps pass - For simple functions without epilogue code, move
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  // returns up, and create conditional returns, to avoid unnecessary
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  // branch-to-blr sequences.
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  struct PPCTOCRegDeps : public MachineFunctionPass {
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    static char ID;
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    PPCTOCRegDeps() : MachineFunctionPass(ID) {
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      initializePPCTOCRegDepsPass(*PassRegistry::getPassRegistry());
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    }
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protected:
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    bool hasTOCLoReloc(const MachineInstr &MI) {
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      if (MI.getOpcode() == PPC::LDtocL ||
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MI.getOpcode() == PPC::ADDItocL139k
)
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        return true;
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for (const MachineOperand &MO : MI.operands())137k
{
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        if ((MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) == PPCII::MO_TOC_LO)
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          return true;
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      }
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return false136k
;
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    }
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    bool processBlock(MachineBasicBlock &MBB) {
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      bool Changed = false;
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      for (auto &MI : MBB) {
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        if (!hasTOCLoReloc(MI))
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          continue;
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        MI.addOperand(MachineOperand::CreateReg(PPC::X2,
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                                                false  /*IsDef*/,
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                                                true  /*IsImp*/));
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        Changed = true;
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      }
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      return Changed;
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    }
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public:
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    bool runOnMachineFunction(MachineFunction &MF) override {
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      bool Changed = false;
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      for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
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        MachineBasicBlock &B = *I++;
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        if (processBlock(B))
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          Changed = true;
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      }
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      return Changed;
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    }
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    void getAnalysisUsage(AnalysisUsage &AU) const override {
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      MachineFunctionPass::getAnalysisUsage(AU);
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    }
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  };
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}
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INITIALIZE_PASS(PPCTOCRegDeps, DEBUG_TYPE,
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                "PowerPC TOC Register Dependencies", false, false)
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char PPCTOCRegDeps::ID = 0;
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FunctionPass*
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llvm::createPPCTOCRegDepsPass() { return new PPCTOCRegDeps(); }
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