Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
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Source (jump to first uncovered line)
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//===----------- PPCVSXSwapRemoval.cpp - Remove VSX LE Swaps -------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
7
//===---------------------------------------------------------------------===//
8
//
9
// This pass analyzes vector computations and removes unnecessary
10
// doubleword swaps (xxswapd instructions).  This pass is performed
11
// only for little-endian VSX code generation.
12
//
13
// For this specific case, loads and stores of v4i32, v4f32, v2i64,
14
// and v2f64 vectors are inefficient.  These are implemented using
15
// the lxvd2x and stxvd2x instructions, which invert the order of
16
// doublewords in a vector register.  Thus code generation inserts
17
// an xxswapd after each such load, and prior to each such store.
18
//
19
// The extra xxswapd instructions reduce performance.  The purpose
20
// of this pass is to reduce the number of xxswapd instructions
21
// required for correctness.
22
//
23
// The primary insight is that much code that operates on vectors
24
// does not care about the relative order of elements in a register,
25
// so long as the correct memory order is preserved.  If we have a
26
// computation where all input values are provided by lxvd2x/xxswapd,
27
// all outputs are stored using xxswapd/lxvd2x, and all intermediate
28
// computations are lane-insensitive (independent of element order),
29
// then all the xxswapd instructions associated with the loads and
30
// stores may be removed without changing observable semantics.
31
//
32
// This pass uses standard equivalence class infrastructure to create
33
// maximal webs of computations fitting the above description.  Each
34
// such web is then optimized by removing its unnecessary xxswapd
35
// instructions.
36
//
37
// There are some lane-sensitive operations for which we can still
38
// permit the optimization, provided we modify those operations
39
// accordingly.  Such operations are identified as using "special
40
// handling" within this module.
41
//
42
//===---------------------------------------------------------------------===//
43
44
#include "PPC.h"
45
#include "PPCInstrBuilder.h"
46
#include "PPCInstrInfo.h"
47
#include "PPCTargetMachine.h"
48
#include "llvm/ADT/DenseMap.h"
49
#include "llvm/ADT/EquivalenceClasses.h"
50
#include "llvm/CodeGen/MachineFunctionPass.h"
51
#include "llvm/CodeGen/MachineInstrBuilder.h"
52
#include "llvm/CodeGen/MachineRegisterInfo.h"
53
#include "llvm/Config/llvm-config.h"
54
#include "llvm/Support/Debug.h"
55
#include "llvm/Support/Format.h"
56
#include "llvm/Support/raw_ostream.h"
57
58
using namespace llvm;
59
60
#define DEBUG_TYPE "ppc-vsx-swaps"
61
62
namespace {
63
64
// A PPCVSXSwapEntry is created for each machine instruction that
65
// is relevant to a vector computation.
66
struct PPCVSXSwapEntry {
67
  // Pointer to the instruction.
68
  MachineInstr *VSEMI;
69
70
  // Unique ID (position in the swap vector).
71
  int VSEId;
72
73
  // Attributes of this node.
74
  unsigned int IsLoad : 1;
75
  unsigned int IsStore : 1;
76
  unsigned int IsSwap : 1;
77
  unsigned int MentionsPhysVR : 1;
78
  unsigned int IsSwappable : 1;
79
  unsigned int MentionsPartialVR : 1;
80
  unsigned int SpecialHandling : 3;
81
  unsigned int WebRejected : 1;
82
  unsigned int WillRemove : 1;
83
};
84
85
enum SHValues {
86
  SH_NONE = 0,
87
  SH_EXTRACT,
88
  SH_INSERT,
89
  SH_NOSWAP_LD,
90
  SH_NOSWAP_ST,
91
  SH_SPLAT,
92
  SH_XXPERMDI,
93
  SH_COPYWIDEN
94
};
95
96
struct PPCVSXSwapRemoval : public MachineFunctionPass {
97
98
  static char ID;
99
  const PPCInstrInfo *TII;
100
  MachineFunction *MF;
101
  MachineRegisterInfo *MRI;
102
103
  // Swap entries are allocated in a vector for better performance.
104
  std::vector<PPCVSXSwapEntry> SwapVector;
105
106
  // A mapping is maintained between machine instructions and
107
  // their swap entries.  The key is the address of the MI.
108
  DenseMap<MachineInstr*, int> SwapMap;
109
110
  // Equivalence classes are used to gather webs of related computation.
111
  // Swap entries are represented by their VSEId fields.
112
  EquivalenceClasses<int> *EC;
113
114
558
  PPCVSXSwapRemoval() : MachineFunctionPass(ID) {
115
558
    initializePPCVSXSwapRemovalPass(*PassRegistry::getPassRegistry());
116
558
  }
117
118
private:
119
  // Initialize data structures.
120
  void initialize(MachineFunction &MFParm);
121
122
  // Walk the machine instructions to gather vector usage information.
123
  // Return true iff vector mentions are present.
124
  bool gatherVectorInstructions();
125
126
  // Add an entry to the swap vector and swap map.
127
  int addSwapEntry(MachineInstr *MI, PPCVSXSwapEntry &SwapEntry);
128
129
  // Hunt backwards through COPY and SUBREG_TO_REG chains for a
130
  // source register.  VecIdx indicates the swap vector entry to
131
  // mark as mentioning a physical register if the search leads
132
  // to one.
133
  unsigned lookThruCopyLike(unsigned SrcReg, unsigned VecIdx);
134
135
  // Generate equivalence classes for related computations (webs).
136
  void formWebs();
137
138
  // Analyze webs and determine those that cannot be optimized.
139
  void recordUnoptimizableWebs();
140
141
  // Record which swap instructions can be safely removed.
142
  void markSwapsForRemoval();
143
144
  // Remove swaps and update other instructions requiring special
145
  // handling.  Return true iff any changes are made.
146
  bool removeSwaps();
147
148
  // Insert a swap instruction from SrcReg to DstReg at the given
149
  // InsertPoint.
150
  void insertSwap(MachineInstr *MI, MachineBasicBlock::iterator InsertPoint,
151
                  unsigned DstReg, unsigned SrcReg);
152
153
  // Update instructions requiring special handling.
154
  void handleSpecialSwappables(int EntryIdx);
155
156
  // Dump a description of the entries in the swap vector.
157
  void dumpSwapVector();
158
159
  // Return true iff the given register is in the given class.
160
567k
  bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
161
567k
    if (TargetRegisterInfo::isVirtualRegister(Reg))
162
344k
      return RC->hasSubClassEq(MRI->getRegClass(Reg));
163
222k
    return RC->contains(Reg);
164
222k
  }
165
166
  // Return true iff the given register is a full vector register.
167
120k
  bool isVecReg(unsigned Reg) {
168
120k
    return (isRegInClass(Reg, &PPC::VSRCRegClass) ||
169
120k
            
isRegInClass(Reg, &PPC::VRRCRegClass)88.2k
);
170
120k
  }
171
172
  // Return true iff the given register is a partial vector register.
173
188k
  bool isScalarVecReg(unsigned Reg) {
174
188k
    return (isRegInClass(Reg, &PPC::VSFRCRegClass) ||
175
188k
            
isRegInClass(Reg, &PPC::VSSRCRegClass)170k
);
176
188k
  }
177
178
  // Return true iff the given register mentions all or part of a
179
  // vector register.  Also sets Partial to true if the mention
180
  // is for just the floating-point register overlap of the register.
181
81.9k
  bool isAnyVecReg(unsigned Reg, bool &Partial) {
182
81.9k
    if (isScalarVecReg(Reg))
183
4.46k
      Partial = true;
184
81.9k
    return isScalarVecReg(Reg) || 
isVecReg(Reg)77.4k
;
185
81.9k
  }
186
187
public:
188
  // Main entry point for this pass.
189
4.96k
  bool runOnMachineFunction(MachineFunction &MF) override {
190
4.96k
    if (skipFunction(MF.getFunction()))
191
0
      return false;
192
4.96k
193
4.96k
    // If we don't have VSX on the subtarget, don't do anything.
194
4.96k
    // Also, on Power 9 the load and store ops preserve element order and so
195
4.96k
    // the swaps are not required.
196
4.96k
    const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
197
4.96k
    if (!STI.hasVSX() || 
!STI.needsSwapsForVSXMemOps()4.81k
)
198
1.60k
      return false;
199
3.36k
200
3.36k
    bool Changed = false;
201
3.36k
    initialize(MF);
202
3.36k
203
3.36k
    if (gatherVectorInstructions()) {
204
1.30k
      formWebs();
205
1.30k
      recordUnoptimizableWebs();
206
1.30k
      markSwapsForRemoval();
207
1.30k
      Changed = removeSwaps();
208
1.30k
    }
209
3.36k
210
3.36k
    // FIXME: See the allocation of EC in initialize().
211
3.36k
    delete EC;
212
3.36k
    return Changed;
213
3.36k
  }
214
};
215
216
// Initialize data structures for this pass.  In particular, clear the
217
// swap vector and allocate the equivalence class mapping before
218
// processing each function.
219
3.36k
void PPCVSXSwapRemoval::initialize(MachineFunction &MFParm) {
220
3.36k
  MF = &MFParm;
221
3.36k
  MRI = &MF->getRegInfo();
222
3.36k
  TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
223
3.36k
224
3.36k
  // An initial vector size of 256 appears to work well in practice.
225
3.36k
  // Small/medium functions with vector content tend not to incur a
226
3.36k
  // reallocation at this size.  Three of the vector tests in
227
3.36k
  // projects/test-suite reallocate, which seems like a reasonable rate.
228
3.36k
  const int InitialVectorSize(256);
229
3.36k
  SwapVector.clear();
230
3.36k
  SwapVector.reserve(InitialVectorSize);
231
3.36k
232
3.36k
  // FIXME: Currently we allocate EC each time because we don't have
233
3.36k
  // access to the set representation on which to call clear().  Should
234
3.36k
  // consider adding a clear() method to the EquivalenceClasses class.
235
3.36k
  EC = new EquivalenceClasses<int>;
236
3.36k
}
237
238
// Create an entry in the swap vector for each instruction that mentions
239
// a full vector register, recording various characteristics of the
240
// instructions there.
241
3.36k
bool PPCVSXSwapRemoval::gatherVectorInstructions() {
242
3.36k
  bool RelevantFunction = false;
243
3.36k
244
5.89k
  for (MachineBasicBlock &MBB : *MF) {
245
44.3k
    for (MachineInstr &MI : MBB) {
246
44.3k
247
44.3k
      if (MI.isDebugInstr())
248
1
        continue;
249
44.3k
250
44.3k
      bool RelevantInstr = false;
251
44.3k
      bool Partial = false;
252
44.3k
253
102k
      for (const MachineOperand &MO : MI.operands()) {
254
102k
        if (!MO.isReg())
255
20.5k
          continue;
256
81.9k
        unsigned Reg = MO.getReg();
257
81.9k
        if (isAnyVecReg(Reg, Partial)) {
258
13.2k
          RelevantInstr = true;
259
13.2k
          break;
260
13.2k
        }
261
81.9k
      }
262
44.3k
263
44.3k
      if (!RelevantInstr)
264
31.0k
        continue;
265
13.2k
266
13.2k
      RelevantFunction = true;
267
13.2k
268
13.2k
      // Create a SwapEntry initialized to zeros, then fill in the
269
13.2k
      // instruction and ID fields before pushing it to the back
270
13.2k
      // of the swap vector.
271
13.2k
      PPCVSXSwapEntry SwapEntry{};
272
13.2k
      int VecIdx = addSwapEntry(&MI, SwapEntry);
273
13.2k
274
13.2k
      switch(MI.getOpcode()) {
275
13.2k
      default:
276
4.46k
        // Unless noted otherwise, an instruction is considered
277
4.46k
        // safe for the optimization.  There are a large number of
278
4.46k
        // such true-SIMD instructions (all vector math, logical,
279
4.46k
        // select, compare, etc.).  However, if the instruction
280
4.46k
        // mentions a partial vector register and does not have
281
4.46k
        // special handling defined, it is not swappable.
282
4.46k
        if (Partial)
283
2.05k
          SwapVector[VecIdx].MentionsPartialVR = 1;
284
2.41k
        else
285
2.41k
          SwapVector[VecIdx].IsSwappable = 1;
286
4.46k
        break;
287
13.2k
      case PPC::XXPERMDI: {
288
1.66k
        // This is a swap if it is of the form XXPERMDI t, s, s, 2.
289
1.66k
        // Unfortunately, MachineCSE ignores COPY and SUBREG_TO_REG, so we
290
1.66k
        // can also see XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), 2,
291
1.66k
        // for example.  We have to look through chains of COPY and
292
1.66k
        // SUBREG_TO_REG to find the real source value for comparison.
293
1.66k
        // If the real source value is a physical register, then mark the
294
1.66k
        // XXPERMDI as mentioning a physical register.
295
1.66k
        int immed = MI.getOperand(3).getImm();
296
1.66k
        if (immed == 2) {
297
1.35k
          unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
298
1.35k
                                               VecIdx);
299
1.35k
          unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
300
1.35k
                                               VecIdx);
301
1.35k
          if (trueReg1 == trueReg2)
302
1.34k
            SwapVector[VecIdx].IsSwap = 1;
303
10
          else {
304
10
            // We can still handle these if the two registers are not
305
10
            // identical, by adjusting the form of the XXPERMDI.
306
10
            SwapVector[VecIdx].IsSwappable = 1;
307
10
            SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
308
10
          }
309
1.35k
        // This is a doubleword splat if it is of the form
310
1.35k
        // XXPERMDI t, s, s, 0 or XXPERMDI t, s, s, 3.  As above we
311
1.35k
        // must look through chains of copy-likes to find the source
312
1.35k
        // register.  We turn off the marking for mention of a physical
313
1.35k
        // register, because splatting it is safe; the optimization
314
1.35k
        // will not swap the value in the physical register.  Whether
315
1.35k
        // or not the two input registers are identical, we can handle
316
1.35k
        // these by adjusting the form of the XXPERMDI.
317
1.35k
        } else 
if (307
immed == 0307
||
immed == 398
) {
318
276
319
276
          SwapVector[VecIdx].IsSwappable = 1;
320
276
          SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
321
276
322
276
          unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
323
276
                                               VecIdx);
324
276
          unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
325
276
                                               VecIdx);
326
276
          if (trueReg1 == trueReg2)
327
99
            SwapVector[VecIdx].MentionsPhysVR = 0;
328
276
329
276
        } else {
330
31
          // We can still handle these by adjusting the form of the XXPERMDI.
331
31
          SwapVector[VecIdx].IsSwappable = 1;
332
31
          SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
333
31
        }
334
1.66k
        break;
335
13.2k
      }
336
13.2k
      case PPC::LVX:
337
329
        // Non-permuting loads are currently unsafe.  We can use special
338
329
        // handling for this in the future.  By not marking these as
339
329
        // IsSwap, we ensure computations containing them will be rejected
340
329
        // for now.
341
329
        SwapVector[VecIdx].IsLoad = 1;
342
329
        break;
343
13.2k
      case PPC::LXVD2X:
344
491
      case PPC::LXVW4X:
345
491
        // Permuting loads are marked as both load and swap, and are
346
491
        // safe for optimization.
347
491
        SwapVector[VecIdx].IsLoad = 1;
348
491
        SwapVector[VecIdx].IsSwap = 1;
349
491
        break;
350
491
      case PPC::LXSDX:
351
450
      case PPC::LXSSPX:
352
450
      case PPC::XFLOADf64:
353
450
      case PPC::XFLOADf32:
354
450
        // A load of a floating-point value into the high-order half of
355
450
        // a vector register is safe, provided that we introduce a swap
356
450
        // following the load, which will be done by the SUBREG_TO_REG
357
450
        // support.  So just mark these as safe.
358
450
        SwapVector[VecIdx].IsLoad = 1;
359
450
        SwapVector[VecIdx].IsSwappable = 1;
360
450
        break;
361
450
      case PPC::STVX:
362
122
        // Non-permuting stores are currently unsafe.  We can use special
363
122
        // handling for this in the future.  By not marking these as
364
122
        // IsSwap, we ensure computations containing them will be rejected
365
122
        // for now.
366
122
        SwapVector[VecIdx].IsStore = 1;
367
122
        break;
368
450
      case PPC::STXVD2X:
369
313
      case PPC::STXVW4X:
370
313
        // Permuting stores are marked as both store and swap, and are
371
313
        // safe for optimization.
372
313
        SwapVector[VecIdx].IsStore = 1;
373
313
        SwapVector[VecIdx].IsSwap = 1;
374
313
        break;
375
3.60k
      case PPC::COPY:
376
3.60k
        // These are fine provided they are moving between full vector
377
3.60k
        // register classes.
378
3.60k
        if (isVecReg(MI.getOperand(0).getReg()) &&
379
3.60k
            
isVecReg(MI.getOperand(1).getReg())1.85k
)
380
1.85k
          SwapVector[VecIdx].IsSwappable = 1;
381
1.75k
        // If we have a copy from one scalar floating-point register
382
1.75k
        // to another, we can accept this even if it is a physical
383
1.75k
        // register.  The only way this gets involved is if it feeds
384
1.75k
        // a SUBREG_TO_REG, which is handled by introducing a swap.
385
1.75k
        else if (isScalarVecReg(MI.getOperand(0).getReg()) &&
386
1.75k
                 isScalarVecReg(MI.getOperand(1).getReg()))
387
1.35k
          SwapVector[VecIdx].IsSwappable = 1;
388
3.60k
        break;
389
361
      case PPC::SUBREG_TO_REG: {
390
361
        // These are fine provided they are moving between full vector
391
361
        // register classes.  If they are moving from a scalar
392
361
        // floating-point class to a vector class, we can handle those
393
361
        // as well, provided we introduce a swap.  It is generally the
394
361
        // case that we will introduce fewer swaps than we remove, but
395
361
        // (FIXME) a cost model could be used.  However, introduced
396
361
        // swaps could potentially be CSEd, so this is not trivial.
397
361
        if (isVecReg(MI.getOperand(0).getReg()) &&
398
361
            isVecReg(MI.getOperand(2).getReg()))
399
0
          SwapVector[VecIdx].IsSwappable = 1;
400
361
        else if (isVecReg(MI.getOperand(0).getReg()) &&
401
361
                 isScalarVecReg(MI.getOperand(2).getReg())) {
402
361
          SwapVector[VecIdx].IsSwappable = 1;
403
361
          SwapVector[VecIdx].SpecialHandling = SHValues::SH_COPYWIDEN;
404
361
        }
405
361
        break;
406
313
      }
407
313
      case PPC::VSPLTB:
408
57
      case PPC::VSPLTH:
409
57
      case PPC::VSPLTW:
410
57
      case PPC::XXSPLTW:
411
57
        // Splats are lane-sensitive, but we can use special handling
412
57
        // to adjust the source lane for the splat.
413
57
        SwapVector[VecIdx].IsSwappable = 1;
414
57
        SwapVector[VecIdx].SpecialHandling = SHValues::SH_SPLAT;
415
57
        break;
416
57
      // The presence of the following lane-sensitive operations in a
417
57
      // web will kill the optimization, at least for now.  For these
418
57
      // we do nothing, causing the optimization to fail.
419
57
      // FIXME: Some of these could be permitted with special handling,
420
57
      // and will be phased in as time permits.
421
57
      // FIXME: There is no simple and maintainable way to express a set
422
57
      // of opcodes having a common attribute in TableGen.  Should this
423
57
      // change, this is a prime candidate to use such a mechanism.
424
1.41k
      case PPC::INLINEASM:
425
1.41k
      case PPC::INLINEASM_BR:
426
1.41k
      case PPC::EXTRACT_SUBREG:
427
1.41k
      case PPC::INSERT_SUBREG:
428
1.41k
      case PPC::COPY_TO_REGCLASS:
429
1.41k
      case PPC::LVEBX:
430
1.41k
      case PPC::LVEHX:
431
1.41k
      case PPC::LVEWX:
432
1.41k
      case PPC::LVSL:
433
1.41k
      case PPC::LVSR:
434
1.41k
      case PPC::LVXL:
435
1.41k
      case PPC::STVEBX:
436
1.41k
      case PPC::STVEHX:
437
1.41k
      case PPC::STVEWX:
438
1.41k
      case PPC::STVXL:
439
1.41k
        // We can handle STXSDX and STXSSPX similarly to LXSDX and LXSSPX,
440
1.41k
        // by adding special handling for narrowing copies as well as
441
1.41k
        // widening ones.  However, I've experimented with this, and in
442
1.41k
        // practice we currently do not appear to use STXSDX fed by
443
1.41k
        // a narrowing copy from a full vector register.  Since I can't
444
1.41k
        // generate any useful test cases, I've left this alone for now.
445
1.41k
      case PPC::STXSDX:
446
1.41k
      case PPC::STXSSPX:
447
1.41k
      case PPC::VCIPHER:
448
1.41k
      case PPC::VCIPHERLAST:
449
1.41k
      case PPC::VMRGHB:
450
1.41k
      case PPC::VMRGHH:
451
1.41k
      case PPC::VMRGHW:
452
1.41k
      case PPC::VMRGLB:
453
1.41k
      case PPC::VMRGLH:
454
1.41k
      case PPC::VMRGLW:
455
1.41k
      case PPC::VMULESB:
456
1.41k
      case PPC::VMULESH:
457
1.41k
      case PPC::VMULESW:
458
1.41k
      case PPC::VMULEUB:
459
1.41k
      case PPC::VMULEUH:
460
1.41k
      case PPC::VMULEUW:
461
1.41k
      case PPC::VMULOSB:
462
1.41k
      case PPC::VMULOSH:
463
1.41k
      case PPC::VMULOSW:
464
1.41k
      case PPC::VMULOUB:
465
1.41k
      case PPC::VMULOUH:
466
1.41k
      case PPC::VMULOUW:
467
1.41k
      case PPC::VNCIPHER:
468
1.41k
      case PPC::VNCIPHERLAST:
469
1.41k
      case PPC::VPERM:
470
1.41k
      case PPC::VPERMXOR:
471
1.41k
      case PPC::VPKPX:
472
1.41k
      case PPC::VPKSHSS:
473
1.41k
      case PPC::VPKSHUS:
474
1.41k
      case PPC::VPKSDSS:
475
1.41k
      case PPC::VPKSDUS:
476
1.41k
      case PPC::VPKSWSS:
477
1.41k
      case PPC::VPKSWUS:
478
1.41k
      case PPC::VPKUDUM:
479
1.41k
      case PPC::VPKUDUS:
480
1.41k
      case PPC::VPKUHUM:
481
1.41k
      case PPC::VPKUHUS:
482
1.41k
      case PPC::VPKUWUM:
483
1.41k
      case PPC::VPKUWUS:
484
1.41k
      case PPC::VPMSUMB:
485
1.41k
      case PPC::VPMSUMD:
486
1.41k
      case PPC::VPMSUMH:
487
1.41k
      case PPC::VPMSUMW:
488
1.41k
      case PPC::VRLB:
489
1.41k
      case PPC::VRLD:
490
1.41k
      case PPC::VRLH:
491
1.41k
      case PPC::VRLW:
492
1.41k
      case PPC::VSBOX:
493
1.41k
      case PPC::VSHASIGMAD:
494
1.41k
      case PPC::VSHASIGMAW:
495
1.41k
      case PPC::VSL:
496
1.41k
      case PPC::VSLDOI:
497
1.41k
      case PPC::VSLO:
498
1.41k
      case PPC::VSR:
499
1.41k
      case PPC::VSRO:
500
1.41k
      case PPC::VSUM2SWS:
501
1.41k
      case PPC::VSUM4SBS:
502
1.41k
      case PPC::VSUM4SHS:
503
1.41k
      case PPC::VSUM4UBS:
504
1.41k
      case PPC::VSUMSWS:
505
1.41k
      case PPC::VUPKHPX:
506
1.41k
      case PPC::VUPKHSB:
507
1.41k
      case PPC::VUPKHSH:
508
1.41k
      case PPC::VUPKHSW:
509
1.41k
      case PPC::VUPKLPX:
510
1.41k
      case PPC::VUPKLSB:
511
1.41k
      case PPC::VUPKLSH:
512
1.41k
      case PPC::VUPKLSW:
513
1.41k
      case PPC::XXMRGHW:
514
1.41k
      case PPC::XXMRGLW:
515
1.41k
      // XXSLDWI could be replaced by a general permute with one of three
516
1.41k
      // permute control vectors (for shift values 1, 2, 3).  However,
517
1.41k
      // VPERM has a more restrictive register class.
518
1.41k
      case PPC::XXSLDWI:
519
1.41k
      case PPC::XSCVDPSPN:
520
1.41k
      case PPC::XSCVSPDPN:
521
1.41k
        break;
522
13.2k
      }
523
13.2k
    }
524
5.89k
  }
525
3.36k
526
3.36k
  if (RelevantFunction) {
527
1.30k
    LLVM_DEBUG(dbgs() << "Swap vector when first built\n\n");
528
1.30k
    LLVM_DEBUG(dumpSwapVector());
529
1.30k
  }
530
3.36k
531
3.36k
  return RelevantFunction;
532
3.36k
}
533
534
// Add an entry to the swap vector and swap map, and make a
535
// singleton equivalence class for the entry.
536
int PPCVSXSwapRemoval::addSwapEntry(MachineInstr *MI,
537
13.2k
                                  PPCVSXSwapEntry& SwapEntry) {
538
13.2k
  SwapEntry.VSEMI = MI;
539
13.2k
  SwapEntry.VSEId = SwapVector.size();
540
13.2k
  SwapVector.push_back(SwapEntry);
541
13.2k
  EC->insert(SwapEntry.VSEId);
542
13.2k
  SwapMap[MI] = SwapEntry.VSEId;
543
13.2k
  return SwapEntry.VSEId;
544
13.2k
}
545
546
// This is used to find the "true" source register for an
547
// XXPERMDI instruction, since MachineCSE does not handle the
548
// "copy-like" operations (Copy and SubregToReg).  Returns
549
// the original SrcReg unless it is the target of a copy-like
550
// operation, in which case we chain backwards through all
551
// such operations to the ultimate source register.  If a
552
// physical register is encountered, we stop the search and
553
// flag the swap entry indicated by VecIdx (the original
554
// XXPERMDI) as mentioning a physical register.
555
unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg,
556
3.75k
                                             unsigned VecIdx) {
557
3.75k
  MachineInstr *MI = MRI->getVRegDef(SrcReg);
558
3.75k
  if (!MI->isCopyLike())
559
2.93k
    return SrcReg;
560
826
561
826
  unsigned CopySrcReg;
562
826
  if (MI->isCopy())
563
474
    CopySrcReg = MI->getOperand(1).getReg();
564
352
  else {
565
352
    assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
566
352
    CopySrcReg = MI->getOperand(2).getReg();
567
352
  }
568
826
569
826
  if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg)) {
570
330
    if (!isScalarVecReg(CopySrcReg))
571
204
      SwapVector[VecIdx].MentionsPhysVR = 1;
572
330
    return CopySrcReg;
573
330
  }
574
496
575
496
  return lookThruCopyLike(CopySrcReg, VecIdx);
576
496
}
577
578
// Generate equivalence classes for related computations (webs) by
579
// def-use relationships of virtual registers.  Mention of a physical
580
// register terminates the generation of equivalence classes as this
581
// indicates a use of a parameter, definition of a return value, use
582
// of a value returned from a call, or definition of a parameter to a
583
// call.  Computations with physical register mentions are flagged
584
// as such so their containing webs will not be optimized.
585
1.30k
void PPCVSXSwapRemoval::formWebs() {
586
1.30k
587
1.30k
  LLVM_DEBUG(dbgs() << "\n*** Forming webs for swap removal ***\n\n");
588
1.30k
589
14.5k
  for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); 
++EntryIdx13.2k
) {
590
13.2k
591
13.2k
    MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
592
13.2k
593
13.2k
    LLVM_DEBUG(dbgs() << "\n" << SwapVector[EntryIdx].VSEId << " ");
594
13.2k
    LLVM_DEBUG(MI->dump());
595
13.2k
596
13.2k
    // It's sufficient to walk vector uses and join them to their unique
597
13.2k
    // definitions.  In addition, check full vector register operands
598
13.2k
    // for physical regs.  We exclude partial-vector register operands
599
13.2k
    // because we can handle them if copied to a full vector.
600
39.8k
    for (const MachineOperand &MO : MI->operands()) {
601
39.8k
      if (!MO.isReg())
602
3.74k
        continue;
603
36.1k
604
36.1k
      unsigned Reg = MO.getReg();
605
36.1k
      if (!isVecReg(Reg) && 
!isScalarVecReg(Reg)17.4k
)
606
9.56k
        continue;
607
26.5k
608
26.5k
      if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
609
4.46k
        if (!(MI->isCopy() && 
isScalarVecReg(Reg)2.81k
))
610
3.26k
          SwapVector[EntryIdx].MentionsPhysVR = 1;
611
4.46k
        continue;
612
4.46k
      }
613
22.0k
614
22.0k
      if (!MO.isUse())
615
9.66k
        continue;
616
12.4k
617
12.4k
      MachineInstr* DefMI = MRI->getVRegDef(Reg);
618
12.4k
      assert(SwapMap.find(DefMI) != SwapMap.end() &&
619
12.4k
             "Inconsistency: def of vector reg not found in swap map!");
620
12.4k
      int DefIdx = SwapMap[DefMI];
621
12.4k
      (void)EC->unionSets(SwapVector[DefIdx].VSEId,
622
12.4k
                          SwapVector[EntryIdx].VSEId);
623
12.4k
624
12.4k
      LLVM_DEBUG(dbgs() << format("Unioning %d with %d\n",
625
12.4k
                                  SwapVector[DefIdx].VSEId,
626
12.4k
                                  SwapVector[EntryIdx].VSEId));
627
12.4k
      LLVM_DEBUG(dbgs() << "  Def: ");
628
12.4k
      LLVM_DEBUG(DefMI->dump());
629
12.4k
    }
630
13.2k
  }
631
1.30k
}
632
633
// Walk the swap vector entries looking for conditions that prevent their
634
// containing computations from being optimized.  When such conditions are
635
// found, mark the representative of the computation's equivalence class
636
// as rejected.
637
1.30k
void PPCVSXSwapRemoval::recordUnoptimizableWebs() {
638
1.30k
639
1.30k
  LLVM_DEBUG(dbgs() << "\n*** Rejecting webs for swap removal ***\n\n");
640
1.30k
641
14.5k
  for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); 
++EntryIdx13.2k
) {
642
13.2k
    int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
643
13.2k
644
13.2k
    // If representative is already rejected, don't waste further time.
645
13.2k
    if (SwapVector[Repr].WebRejected)
646
7.36k
      continue;
647
5.90k
648
5.90k
    // Reject webs containing mentions of physical or partial registers, or
649
5.90k
    // containing operations that we don't know how to handle in a lane-
650
5.90k
    // permuted region.
651
5.90k
    if (SwapVector[EntryIdx].MentionsPhysVR ||
652
5.90k
        
SwapVector[EntryIdx].MentionsPartialVR3.97k
||
653
5.90k
        
!(3.56k
SwapVector[EntryIdx].IsSwappable3.56k
||
SwapVector[EntryIdx].IsSwap1.53k
)) {
654
2.63k
655
2.63k
      SwapVector[Repr].WebRejected = 1;
656
2.63k
657
2.63k
      LLVM_DEBUG(
658
2.63k
          dbgs() << format("Web %d rejected for physreg, partial reg, or not "
659
2.63k
                           "swap[pable]\n",
660
2.63k
                           Repr));
661
2.63k
      LLVM_DEBUG(dbgs() << "  in " << EntryIdx << ": ");
662
2.63k
      LLVM_DEBUG(SwapVector[EntryIdx].VSEMI->dump());
663
2.63k
      LLVM_DEBUG(dbgs() << "\n");
664
2.63k
    }
665
3.26k
666
3.26k
    // Reject webs than contain swapping loads that feed something other
667
3.26k
    // than a swap instruction.
668
3.26k
    else if (SwapVector[EntryIdx].IsLoad && 
SwapVector[EntryIdx].IsSwap815
) {
669
452
      MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
670
452
      unsigned DefReg = MI->getOperand(0).getReg();
671
452
672
452
      // We skip debug instructions in the analysis.  (Note that debug
673
452
      // location information is still maintained by this optimization
674
452
      // because it remains on the LXVD2X and STXVD2X instructions after
675
452
      // the XXPERMDIs are removed.)
676
452
      for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
677
452
        int UseIdx = SwapMap[&UseMI];
678
452
679
452
        if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
680
452
            SwapVector[UseIdx].IsStore) {
681
0
682
0
          SwapVector[Repr].WebRejected = 1;
683
0
684
0
          LLVM_DEBUG(dbgs() << format(
685
0
                         "Web %d rejected for load not feeding swap\n", Repr));
686
0
          LLVM_DEBUG(dbgs() << "  def " << EntryIdx << ": ");
687
0
          LLVM_DEBUG(MI->dump());
688
0
          LLVM_DEBUG(dbgs() << "  use " << UseIdx << ": ");
689
0
          LLVM_DEBUG(UseMI.dump());
690
0
          LLVM_DEBUG(dbgs() << "\n");
691
0
        }
692
452
      }
693
452
694
452
    // Reject webs that contain swapping stores that are fed by something
695
452
    // other than a swap instruction.
696
2.81k
    } else if (SwapVector[EntryIdx].IsStore && 
SwapVector[EntryIdx].IsSwap167
) {
697
167
      MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
698
167
      unsigned UseReg = MI->getOperand(0).getReg();
699
167
      MachineInstr *DefMI = MRI->getVRegDef(UseReg);
700
167
      unsigned DefReg = DefMI->getOperand(0).getReg();
701
167
      int DefIdx = SwapMap[DefMI];
702
167
703
167
      if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
704
167
          SwapVector[DefIdx].IsStore) {
705
0
706
0
        SwapVector[Repr].WebRejected = 1;
707
0
708
0
        LLVM_DEBUG(dbgs() << format(
709
0
                       "Web %d rejected for store not fed by swap\n", Repr));
710
0
        LLVM_DEBUG(dbgs() << "  def " << DefIdx << ": ");
711
0
        LLVM_DEBUG(DefMI->dump());
712
0
        LLVM_DEBUG(dbgs() << "  use " << EntryIdx << ": ");
713
0
        LLVM_DEBUG(MI->dump());
714
0
        LLVM_DEBUG(dbgs() << "\n");
715
0
      }
716
167
717
167
      // Ensure all uses of the register defined by DefMI feed store
718
167
      // instructions
719
188
      for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
720
188
        int UseIdx = SwapMap[&UseMI];
721
188
722
188
        if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) {
723
1
          SwapVector[Repr].WebRejected = 1;
724
1
725
1
          LLVM_DEBUG(
726
1
              dbgs() << format(
727
1
                  "Web %d rejected for swap not feeding only stores\n", Repr));
728
1
          LLVM_DEBUG(dbgs() << "  def "
729
1
                            << " : ");
730
1
          LLVM_DEBUG(DefMI->dump());
731
1
          LLVM_DEBUG(dbgs() << "  use " << UseIdx << ": ");
732
1
          LLVM_DEBUG(SwapVector[UseIdx].VSEMI->dump());
733
1
          LLVM_DEBUG(dbgs() << "\n");
734
1
        }
735
188
      }
736
167
    }
737
5.90k
  }
738
1.30k
739
1.30k
  LLVM_DEBUG(dbgs() << "Swap vector after web analysis:\n\n");
740
1.30k
  LLVM_DEBUG(dumpSwapVector());
741
1.30k
}
742
743
// Walk the swap vector entries looking for swaps fed by permuting loads
744
// and swaps that feed permuting stores.  If the containing computation
745
// has not been marked rejected, mark each such swap for removal.
746
// (Removal is delayed in case optimization has disturbed the pattern,
747
// such that multiple loads feed the same swap, etc.)
748
1.30k
void PPCVSXSwapRemoval::markSwapsForRemoval() {
749
1.30k
750
1.30k
  LLVM_DEBUG(dbgs() << "\n*** Marking swaps for removal ***\n\n");
751
1.30k
752
14.5k
  for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); 
++EntryIdx13.2k
) {
753
13.2k
754
13.2k
    if (SwapVector[EntryIdx].IsLoad && 
SwapVector[EntryIdx].IsSwap1.27k
) {
755
491
      int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
756
491
757
491
      if (!SwapVector[Repr].WebRejected) {
758
151
        MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
759
151
        unsigned DefReg = MI->getOperand(0).getReg();
760
151
761
151
        for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
762
151
          int UseIdx = SwapMap[&UseMI];
763
151
          SwapVector[UseIdx].WillRemove = 1;
764
151
765
151
          LLVM_DEBUG(dbgs() << "Marking swap fed by load for removal: ");
766
151
          LLVM_DEBUG(UseMI.dump());
767
151
        }
768
151
      }
769
491
770
12.7k
    } else if (SwapVector[EntryIdx].IsStore && 
SwapVector[EntryIdx].IsSwap435
) {
771
313
      int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
772
313
773
313
      if (!SwapVector[Repr].WebRejected) {
774
152
        MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
775
152
        unsigned UseReg = MI->getOperand(0).getReg();
776
152
        MachineInstr *DefMI = MRI->getVRegDef(UseReg);
777
152
        int DefIdx = SwapMap[DefMI];
778
152
        SwapVector[DefIdx].WillRemove = 1;
779
152
780
152
        LLVM_DEBUG(dbgs() << "Marking swap feeding store for removal: ");
781
152
        LLVM_DEBUG(DefMI->dump());
782
152
      }
783
313
784
12.4k
    } else if (SwapVector[EntryIdx].IsSwappable &&
785
12.4k
               
SwapVector[EntryIdx].SpecialHandling != 06.81k
) {
786
735
      int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
787
735
788
735
      if (!SwapVector[Repr].WebRejected)
789
31
        handleSpecialSwappables(EntryIdx);
790
735
    }
791
13.2k
  }
792
1.30k
}
793
794
// Create an xxswapd instruction and insert it prior to the given point.
795
// MI is used to determine basic block and debug loc information.
796
// FIXME: When inserting a swap, we should check whether SrcReg is
797
// defined by another swap:  SrcReg = XXPERMDI Reg, Reg, 2;  If so,
798
// then instead we should generate a copy from Reg to DstReg.
799
void PPCVSXSwapRemoval::insertSwap(MachineInstr *MI,
800
                                   MachineBasicBlock::iterator InsertPoint,
801
9
                                   unsigned DstReg, unsigned SrcReg) {
802
9
  BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
803
9
          TII->get(PPC::XXPERMDI), DstReg)
804
9
    .addReg(SrcReg)
805
9
    .addReg(SrcReg)
806
9
    .addImm(2);
807
9
}
808
809
// The identified swap entry requires special handling to allow its
810
// containing computation to be optimized.  Perform that handling
811
// here.
812
// FIXME: Additional opportunities will be phased in with subsequent
813
// patches.
814
31
void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
815
31
  switch (SwapVector[EntryIdx].SpecialHandling) {
816
31
817
31
  default:
818
0
    llvm_unreachable("Unexpected special handling type");
819
31
820
31
  // For splats based on an index into a vector, add N/2 modulo N
821
31
  // to the index, where N is the number of vector elements.
822
31
  case SHValues::SH_SPLAT: {
823
3
    MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
824
3
    unsigned NElts;
825
3
826
3
    LLVM_DEBUG(dbgs() << "Changing splat: ");
827
3
    LLVM_DEBUG(MI->dump());
828
3
829
3
    switch (MI->getOpcode()) {
830
3
    default:
831
0
      llvm_unreachable("Unexpected splat opcode");
832
3
    
case PPC::VSPLTB: NElts = 16; break1
;
833
3
    
case PPC::VSPLTH: NElts = 8; break1
;
834
3
    case PPC::VSPLTW:
835
1
    case PPC::XXSPLTW: NElts = 4;  break;
836
3
    }
837
3
838
3
    unsigned EltNo;
839
3
    if (MI->getOpcode() == PPC::XXSPLTW)
840
1
      EltNo = MI->getOperand(2).getImm();
841
2
    else
842
2
      EltNo = MI->getOperand(1).getImm();
843
3
844
3
    EltNo = (EltNo + NElts / 2) % NElts;
845
3
    if (MI->getOpcode() == PPC::XXSPLTW)
846
1
      MI->getOperand(2).setImm(EltNo);
847
2
    else
848
2
      MI->getOperand(1).setImm(EltNo);
849
3
850
3
    LLVM_DEBUG(dbgs() << "  Into: ");
851
3
    LLVM_DEBUG(MI->dump());
852
3
    break;
853
3
  }
854
3
855
3
  // For an XXPERMDI that isn't handled otherwise, we need to
856
3
  // reverse the order of the operands.  If the selector operand
857
3
  // has a value of 0 or 3, we need to change it to 3 or 0,
858
3
  // respectively.  Otherwise we should leave it alone.  (This
859
3
  // is equivalent to reversing the two bits of the selector
860
3
  // operand and complementing the result.)
861
19
  case SHValues::SH_XXPERMDI: {
862
19
    MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
863
19
864
19
    LLVM_DEBUG(dbgs() << "Changing XXPERMDI: ");
865
19
    LLVM_DEBUG(MI->dump());
866
19
867
19
    unsigned Selector = MI->getOperand(3).getImm();
868
19
    if (Selector == 0 || 
Selector == 39
)
869
16
      Selector = 3 - Selector;
870
19
    MI->getOperand(3).setImm(Selector);
871
19
872
19
    unsigned Reg1 = MI->getOperand(1).getReg();
873
19
    unsigned Reg2 = MI->getOperand(2).getReg();
874
19
    MI->getOperand(1).setReg(Reg2);
875
19
    MI->getOperand(2).setReg(Reg1);
876
19
877
19
    // We also need to swap kill flag associated with the register.
878
19
    bool IsKill1 = MI->getOperand(1).isKill();
879
19
    bool IsKill2 = MI->getOperand(2).isKill();
880
19
    MI->getOperand(1).setIsKill(IsKill2);
881
19
    MI->getOperand(2).setIsKill(IsKill1);
882
19
883
19
    LLVM_DEBUG(dbgs() << "  Into: ");
884
19
    LLVM_DEBUG(MI->dump());
885
19
    break;
886
3
  }
887
3
888
3
  // For a copy from a scalar floating-point register to a vector
889
3
  // register, removing swaps will leave the copied value in the
890
3
  // wrong lane.  Insert a swap following the copy to fix this.
891
9
  case SHValues::SH_COPYWIDEN: {
892
9
    MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
893
9
894
9
    LLVM_DEBUG(dbgs() << "Changing SUBREG_TO_REG: ");
895
9
    LLVM_DEBUG(MI->dump());
896
9
897
9
    unsigned DstReg = MI->getOperand(0).getReg();
898
9
    const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
899
9
    unsigned NewVReg = MRI->createVirtualRegister(DstRC);
900
9
901
9
    MI->getOperand(0).setReg(NewVReg);
902
9
    LLVM_DEBUG(dbgs() << "  Into: ");
903
9
    LLVM_DEBUG(MI->dump());
904
9
905
9
    auto InsertPoint = ++MachineBasicBlock::iterator(MI);
906
9
907
9
    // Note that an XXPERMDI requires a VSRC, so if the SUBREG_TO_REG
908
9
    // is copying to a VRRC, we need to be careful to avoid a register
909
9
    // assignment problem.  In this case we must copy from VRRC to VSRC
910
9
    // prior to the swap, and from VSRC to VRRC following the swap.
911
9
    // Coalescing will usually remove all this mess.
912
9
    if (DstRC == &PPC::VRRCRegClass) {
913
0
      unsigned VSRCTmp1 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
914
0
      unsigned VSRCTmp2 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
915
0
916
0
      BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
917
0
              TII->get(PPC::COPY), VSRCTmp1)
918
0
        .addReg(NewVReg);
919
0
      LLVM_DEBUG(std::prev(InsertPoint)->dump());
920
0
921
0
      insertSwap(MI, InsertPoint, VSRCTmp2, VSRCTmp1);
922
0
      LLVM_DEBUG(std::prev(InsertPoint)->dump());
923
0
924
0
      BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
925
0
              TII->get(PPC::COPY), DstReg)
926
0
        .addReg(VSRCTmp2);
927
0
      LLVM_DEBUG(std::prev(InsertPoint)->dump());
928
0
929
9
    } else {
930
9
      insertSwap(MI, InsertPoint, DstReg, NewVReg);
931
9
      LLVM_DEBUG(std::prev(InsertPoint)->dump());
932
9
    }
933
9
    break;
934
3
  }
935
31
  }
936
31
}
937
938
// Walk the swap vector and replace each entry marked for removal with
939
// a copy operation.
940
1.30k
bool PPCVSXSwapRemoval::removeSwaps() {
941
1.30k
942
1.30k
  LLVM_DEBUG(dbgs() << "\n*** Removing swaps ***\n\n");
943
1.30k
944
1.30k
  bool Changed = false;
945
1.30k
946
14.5k
  for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); 
++EntryIdx13.2k
) {
947
13.2k
    if (SwapVector[EntryIdx].WillRemove) {
948
293
      Changed = true;
949
293
      MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
950
293
      MachineBasicBlock *MBB = MI->getParent();
951
293
      BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
952
293
              MI->getOperand(0).getReg())
953
293
          .add(MI->getOperand(1));
954
293
955
293
      LLVM_DEBUG(dbgs() << format("Replaced %d with copy: ",
956
293
                                  SwapVector[EntryIdx].VSEId));
957
293
      LLVM_DEBUG(MI->dump());
958
293
959
293
      MI->eraseFromParent();
960
293
    }
961
13.2k
  }
962
1.30k
963
1.30k
  return Changed;
964
1.30k
}
965
966
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
967
// For debug purposes, dump the contents of the swap vector.
968
LLVM_DUMP_METHOD void PPCVSXSwapRemoval::dumpSwapVector() {
969
970
  for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
971
972
    MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
973
    int ID = SwapVector[EntryIdx].VSEId;
974
975
    dbgs() << format("%6d", ID);
976
    dbgs() << format("%6d", EC->getLeaderValue(ID));
977
    dbgs() << format(" %bb.%3d", MI->getParent()->getNumber());
978
    dbgs() << format("  %14s  ", TII->getName(MI->getOpcode()).str().c_str());
979
980
    if (SwapVector[EntryIdx].IsLoad)
981
      dbgs() << "load ";
982
    if (SwapVector[EntryIdx].IsStore)
983
      dbgs() << "store ";
984
    if (SwapVector[EntryIdx].IsSwap)
985
      dbgs() << "swap ";
986
    if (SwapVector[EntryIdx].MentionsPhysVR)
987
      dbgs() << "physreg ";
988
    if (SwapVector[EntryIdx].MentionsPartialVR)
989
      dbgs() << "partialreg ";
990
991
    if (SwapVector[EntryIdx].IsSwappable) {
992
      dbgs() << "swappable ";
993
      switch(SwapVector[EntryIdx].SpecialHandling) {
994
      default:
995
        dbgs() << "special:**unknown**";
996
        break;
997
      case SH_NONE:
998
        break;
999
      case SH_EXTRACT:
1000
        dbgs() << "special:extract ";
1001
        break;
1002
      case SH_INSERT:
1003
        dbgs() << "special:insert ";
1004
        break;
1005
      case SH_NOSWAP_LD:
1006
        dbgs() << "special:load ";
1007
        break;
1008
      case SH_NOSWAP_ST:
1009
        dbgs() << "special:store ";
1010
        break;
1011
      case SH_SPLAT:
1012
        dbgs() << "special:splat ";
1013
        break;
1014
      case SH_XXPERMDI:
1015
        dbgs() << "special:xxpermdi ";
1016
        break;
1017
      case SH_COPYWIDEN:
1018
        dbgs() << "special:copywiden ";
1019
        break;
1020
      }
1021
    }
1022
1023
    if (SwapVector[EntryIdx].WebRejected)
1024
      dbgs() << "rejected ";
1025
    if (SwapVector[EntryIdx].WillRemove)
1026
      dbgs() << "remove ";
1027
1028
    dbgs() << "\n";
1029
1030
    // For no-asserts builds.
1031
    (void)MI;
1032
    (void)ID;
1033
  }
1034
1035
  dbgs() << "\n";
1036
}
1037
#endif
1038
1039
} // end default namespace
1040
1041
101k
INITIALIZE_PASS_BEGIN(PPCVSXSwapRemoval, DEBUG_TYPE,
1042
101k
                      "PowerPC VSX Swap Removal", false, false)
1043
101k
INITIALIZE_PASS_END(PPCVSXSwapRemoval, DEBUG_TYPE,
1044
                    "PowerPC VSX Swap Removal", false, false)
1045
1046
char PPCVSXSwapRemoval::ID = 0;
1047
FunctionPass*
1048
558
llvm::createPPCVSXSwapRemovalPass() { return new PPCVSXSwapRemoval(); }