Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
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//===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "Utils/RISCVBaseInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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STATISTIC(MCNumFixups, "Number of MC fixups created");
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namespace {
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class RISCVMCCodeEmitter : public MCCodeEmitter {
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  RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
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  void operator=(const RISCVMCCodeEmitter &) = delete;
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  MCContext &Ctx;
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  MCInstrInfo const &MCII;
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public:
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  RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
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320
      : Ctx(ctx), MCII(MCII) {}
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49
320
  ~RISCVMCCodeEmitter() override {}
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  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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                         SmallVectorImpl<MCFixup> &Fixups,
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                         const MCSubtargetInfo &STI) const override;
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  void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
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                          SmallVectorImpl<MCFixup> &Fixups,
57
                          const MCSubtargetInfo &STI) const;
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  void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
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                      SmallVectorImpl<MCFixup> &Fixups,
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                      const MCSubtargetInfo &STI) const;
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  /// TableGen'erated function for getting the binary encoding for an
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  /// instruction.
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  uint64_t getBinaryCodeForInstr(const MCInst &MI,
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                                 SmallVectorImpl<MCFixup> &Fixups,
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                                 const MCSubtargetInfo &STI) const;
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  /// Return binary encoding of operand. If the machine operand requires
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  /// relocation, record the relocation and return zero.
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  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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                             SmallVectorImpl<MCFixup> &Fixups,
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                             const MCSubtargetInfo &STI) const;
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  unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
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                             SmallVectorImpl<MCFixup> &Fixups,
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                             const MCSubtargetInfo &STI) const;
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  unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
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                         SmallVectorImpl<MCFixup> &Fixups,
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                         const MCSubtargetInfo &STI) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
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                                              const MCRegisterInfo &MRI,
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                                              MCContext &Ctx) {
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320
  return new RISCVMCCodeEmitter(Ctx, MCII);
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320
}
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// Expand PseudoCALL(Reg) and PseudoTAIL to AUIPC and JALR with relocation
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// types. We expand PseudoCALL(Reg) and PseudoTAIL while encoding, meaning AUIPC
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// and JALR won't go through RISCV MC to MC compressed instruction
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// transformation. This is acceptable because AUIPC has no 16-bit form and
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// C_JALR have no immediate operand field.  We let linker relaxation deal with
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// it. When linker relaxation enabled, AUIPC and JALR have chance relax to JAL.
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// If C extension is enabled, JAL has chance relax to C_JAL.
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void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
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                                            SmallVectorImpl<MCFixup> &Fixups,
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132
                                            const MCSubtargetInfo &STI) const {
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  MCInst TmpInst;
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  MCOperand Func;
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132
  unsigned Ra;
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  if (MI.getOpcode() == RISCV::PseudoTAIL) {
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36
    Func = MI.getOperand(0);
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    Ra = RISCV::X6;
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  } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
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    Func = MI.getOperand(1);
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    Ra = MI.getOperand(0).getReg();
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90
  } else {
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    Func = MI.getOperand(0);
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    Ra = RISCV::X1;
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90
  }
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  uint32_t Binary;
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132
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  assert(Func.isExpr() && "Expected expression");
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  const MCExpr *CallExpr = Func.getExpr();
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132
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  // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
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  TmpInst = MCInstBuilder(RISCV::AUIPC)
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                .addReg(Ra)
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                .addOperand(MCOperand::createExpr(CallExpr));
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  Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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  support::endian::write(OS, Binary, support::little);
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  if (MI.getOpcode() == RISCV::PseudoTAIL)
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    // Emit JALR X0, X6, 0
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    TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
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  else
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    // Emit JALR Ra, Ra, 0
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    TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
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  Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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  support::endian::write(OS, Binary, support::little);
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}
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// Expand PseudoAddTPRel to a simple ADD with the correct relocation.
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void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
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                                        SmallVectorImpl<MCFixup> &Fixups,
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6
                                        const MCSubtargetInfo &STI) const {
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  MCOperand DestReg = MI.getOperand(0);
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  MCOperand SrcReg = MI.getOperand(1);
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  MCOperand TPReg = MI.getOperand(2);
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  assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
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         "Expected thread pointer as second input to TP-relative add");
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  MCOperand SrcSymbol = MI.getOperand(3);
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  assert(SrcSymbol.isExpr() &&
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         "Expected expression as third input to TP-relative add");
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  const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
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  assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
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         "Expected tprel_add relocation on TP-relative symbol");
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  // Emit the correct tprel_add relocation for the symbol.
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  Fixups.push_back(MCFixup::create(
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      0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
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  // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
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  if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
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0
    const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
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0
    Fixups.push_back(MCFixup::create(
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0
        0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
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0
  }
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6
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  // Emit a normal ADD instruction with the given operands.
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  MCInst TmpInst = MCInstBuilder(RISCV::ADD)
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                       .addOperand(DestReg)
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                       .addOperand(SrcReg)
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                       .addOperand(TPReg);
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  uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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  support::endian::write(OS, Binary, support::little);
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6
}
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void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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                                           SmallVectorImpl<MCFixup> &Fixups,
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5.48k
                                           const MCSubtargetInfo &STI) const {
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5.48k
  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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5.48k
  // Get byte count of instruction.
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5.48k
  unsigned Size = Desc.getSize();
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5.48k
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5.48k
  if (MI.getOpcode() == RISCV::PseudoCALLReg ||
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5.48k
      
MI.getOpcode() == RISCV::PseudoCALL5.47k
||
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5.48k
      
MI.getOpcode() == RISCV::PseudoTAIL5.38k
) {
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    expandFunctionCall(MI, OS, Fixups, STI);
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    MCNumEmitted += 2;
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    return;
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  }
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5.35k
190
5.35k
  if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
191
6
    expandAddTPRel(MI, OS, Fixups, STI);
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    MCNumEmitted += 1;
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    return;
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  }
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5.34k
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5.34k
  switch (Size) {
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5.34k
  default:
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0
    llvm_unreachable("Unhandled encodeInstruction length!");
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5.34k
  case 2: {
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    uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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    support::endian::write<uint16_t>(OS, Bits, support::little);
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901
    break;
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5.34k
  }
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5.34k
  case 4: {
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4.44k
    uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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4.44k
    support::endian::write(OS, Bits, support::little);
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4.44k
    break;
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5.34k
  }
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5.34k
  }
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5.34k
211
5.34k
  ++MCNumEmitted; // Keep track of the # of mi's emitted.
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5.34k
}
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unsigned
215
RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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                                      SmallVectorImpl<MCFixup> &Fixups,
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12.9k
                                      const MCSubtargetInfo &STI) const {
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12.9k
219
12.9k
  if (MO.isReg())
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10.4k
    return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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2.51k
222
2.51k
  if (MO.isImm())
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2.51k
    return static_cast<unsigned>(MO.getImm());
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0
225
0
  llvm_unreachable("Unhandled expression!");
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0
  return 0;
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0
}
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unsigned
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RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
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                                      SmallVectorImpl<MCFixup> &Fixups,
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464
                                      const MCSubtargetInfo &STI) const {
233
464
  const MCOperand &MO = MI.getOperand(OpNo);
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464
235
464
  if (MO.isImm()) {
236
150
    unsigned Res = MO.getImm();
237
150
    assert((Res & 1) == 0 && "LSB is non-zero");
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    return Res >> 1;
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150
  }
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314
241
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  return getImmOpValue(MI, OpNo, Fixups, STI);
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314
}
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unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
245
                                           SmallVectorImpl<MCFixup> &Fixups,
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2.13k
                                           const MCSubtargetInfo &STI) const {
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2.13k
  bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
248
2.13k
  const MCOperand &MO = MI.getOperand(OpNo);
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2.13k
250
2.13k
  MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
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2.13k
  unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
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2.13k
253
2.13k
  // If the destination is an immediate, there is nothing to do.
254
2.13k
  if (MO.isImm())
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1.39k
    return MO.getImm();
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742
257
742
  assert(MO.isExpr() &&
258
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         "getImmOpValue expects only expressions or immediates");
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  const MCExpr *Expr = MO.getExpr();
260
742
  MCExpr::ExprKind Kind = Expr->getKind();
261
742
  RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
262
742
  bool RelaxCandidate = false;
263
742
  if (Kind == MCExpr::Target) {
264
428
    const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
265
428
266
428
    switch (RVExpr->getKind()) {
267
428
    case RISCVMCExpr::VK_RISCV_None:
268
0
    case RISCVMCExpr::VK_RISCV_Invalid:
269
0
      llvm_unreachable("Unhandled fixup kind!");
270
0
    case RISCVMCExpr::VK_RISCV_TPREL_ADD:
271
0
      // tprel_add is only used to indicate that a relocation should be emitted
272
0
      // for an add instruction used in TP-relative addressing. It should not be
273
0
      // expanded as if representing an actual instruction operand and so to
274
0
      // encounter it here is an error.
275
0
      llvm_unreachable(
276
0
          "VK_RISCV_TPREL_ADD should not represent an instruction operand");
277
69
    case RISCVMCExpr::VK_RISCV_LO:
278
69
      if (MIFrm == RISCVII::InstFormatI)
279
46
        FixupKind = RISCV::fixup_riscv_lo12_i;
280
23
      else if (MIFrm == RISCVII::InstFormatS)
281
23
        FixupKind = RISCV::fixup_riscv_lo12_s;
282
23
      else
283
23
        
llvm_unreachable0
("VK_RISCV_LO used with unexpected instruction format");
284
69
      RelaxCandidate = true;
285
69
      break;
286
69
    case RISCVMCExpr::VK_RISCV_HI:
287
35
      FixupKind = RISCV::fixup_riscv_hi20;
288
35
      RelaxCandidate = true;
289
35
      break;
290
105
    case RISCVMCExpr::VK_RISCV_PCREL_LO:
291
105
      if (MIFrm == RISCVII::InstFormatI)
292
76
        FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
293
29
      else if (MIFrm == RISCVII::InstFormatS)
294
29
        FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
295
29
      else
296
29
        
llvm_unreachable0
(
297
105
            "VK_RISCV_PCREL_LO used with unexpected instruction format");
298
105
      RelaxCandidate = true;
299
105
      break;
300
105
    case RISCVMCExpr::VK_RISCV_PCREL_HI:
301
43
      FixupKind = RISCV::fixup_riscv_pcrel_hi20;
302
43
      RelaxCandidate = true;
303
43
      break;
304
105
    case RISCVMCExpr::VK_RISCV_GOT_HI:
305
10
      FixupKind = RISCV::fixup_riscv_got_hi20;
306
10
      break;
307
105
    case RISCVMCExpr::VK_RISCV_TPREL_LO:
308
12
      if (MIFrm == RISCVII::InstFormatI)
309
6
        FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
310
6
      else if (MIFrm == RISCVII::InstFormatS)
311
6
        FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
312
6
      else
313
6
        
llvm_unreachable0
(
314
12
            "VK_RISCV_TPREL_LO used with unexpected instruction format");
315
12
      RelaxCandidate = true;
316
12
      break;
317
12
    case RISCVMCExpr::VK_RISCV_TPREL_HI:
318
8
      FixupKind = RISCV::fixup_riscv_tprel_hi20;
319
8
      RelaxCandidate = true;
320
8
      break;
321
12
    case RISCVMCExpr::VK_RISCV_TLS_GOT_HI:
322
6
      FixupKind = RISCV::fixup_riscv_tls_got_hi20;
323
6
      break;
324
12
    case RISCVMCExpr::VK_RISCV_TLS_GD_HI:
325
8
      FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
326
8
      break;
327
112
    case RISCVMCExpr::VK_RISCV_CALL:
328
112
      FixupKind = RISCV::fixup_riscv_call;
329
112
      RelaxCandidate = true;
330
112
      break;
331
20
    case RISCVMCExpr::VK_RISCV_CALL_PLT:
332
20
      FixupKind = RISCV::fixup_riscv_call_plt;
333
20
      RelaxCandidate = true;
334
20
      break;
335
314
    }
336
314
  } else if (Kind == MCExpr::SymbolRef &&
337
314
             cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
338
314
    if (Desc.getOpcode() == RISCV::JAL) {
339
73
      FixupKind = RISCV::fixup_riscv_jal;
340
241
    } else if (MIFrm == RISCVII::InstFormatB) {
341
94
      FixupKind = RISCV::fixup_riscv_branch;
342
147
    } else if (MIFrm == RISCVII::InstFormatCJ) {
343
64
      FixupKind = RISCV::fixup_riscv_rvc_jump;
344
83
    } else if (MIFrm == RISCVII::InstFormatCB) {
345
83
      FixupKind = RISCV::fixup_riscv_rvc_branch;
346
83
    }
347
314
  }
348
742
349
742
  assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
350
742
351
742
  Fixups.push_back(
352
742
      MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
353
742
  ++MCNumFixups;
354
742
355
742
  // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
356
742
  // enabled and the current fixup will result in a relocation that may be
357
742
  // relaxed.
358
742
  if (EnableRelax && 
RelaxCandidate222
) {
359
78
    const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
360
78
    Fixups.push_back(
361
78
    MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
362
78
                    MI.getLoc()));
363
78
    ++MCNumFixups;
364
78
  }
365
742
366
742
  return 0;
367
742
}
368
369
#include "RISCVGenMCCodeEmitter.inc"