Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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//===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVFrameLowering.h"
14
#include "RISCVMachineFunctionInfo.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/MC/MCDwarf.h"
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using namespace llvm;
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25
29.8k
bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const {
26
29.8k
  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
27
29.8k
28
29.8k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
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29.8k
  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
30
29.8k
         
RegInfo->needsStackRealignment(MF)27.8k
||
MFI.hasVarSizedObjects()27.8k
||
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29.8k
         
MFI.isFrameAddressTaken()27.6k
;
32
29.8k
}
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// Determines the size of the frame and maximum call frame size.
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3.35k
void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
36
3.35k
  MachineFrameInfo &MFI = MF.getFrameInfo();
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3.35k
  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
38
3.35k
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3.35k
  // Get the number of bytes to allocate from the FrameInfo.
40
3.35k
  uint64_t FrameSize = MFI.getStackSize();
41
3.35k
42
3.35k
  // Get the alignment.
43
3.35k
  uint64_t StackAlign = RI->needsStackRealignment(MF) ? 
MFI.getMaxAlignment()0
44
3.35k
                                                      : getStackAlignment();
45
3.35k
46
3.35k
  // Make sure the frame is aligned.
47
3.35k
  FrameSize = alignTo(FrameSize, StackAlign);
48
3.35k
49
3.35k
  // Update frame info.
50
3.35k
  MFI.setStackSize(FrameSize);
51
3.35k
}
52
53
void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
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                                   MachineBasicBlock::iterator MBBI,
55
                                   const DebugLoc &DL, unsigned DestReg,
56
                                   unsigned SrcReg, int64_t Val,
57
5.04k
                                   MachineInstr::MIFlag Flag) const {
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5.04k
  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
59
5.04k
  const RISCVInstrInfo *TII = STI.getInstrInfo();
60
5.04k
61
5.04k
  if (DestReg == SrcReg && 
Val == 04.86k
)
62
1.86k
    return;
63
3.18k
64
3.18k
  if (isInt<12>(Val)) {
65
3.17k
    BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
66
3.17k
        .addReg(SrcReg)
67
3.17k
        .addImm(Val)
68
3.17k
        .setMIFlag(Flag);
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3.17k
  } else 
if (10
isInt<32>(Val)10
) {
70
10
    unsigned Opc = RISCV::ADD;
71
10
    bool isSub = Val < 0;
72
10
    if (isSub) {
73
4
      Val = -Val;
74
4
      Opc = RISCV::SUB;
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4
    }
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10
77
10
    unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
78
10
    TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag);
79
10
    BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
80
10
        .addReg(SrcReg)
81
10
        .addReg(ScratchReg, RegState::Kill)
82
10
        .setMIFlag(Flag);
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10
  } else {
84
0
    report_fatal_error("adjustReg cannot yet handle adjustments >32 bits");
85
0
  }
86
3.18k
}
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// Returns the register used to hold the frame pointer.
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6.72k
static unsigned getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
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// Returns the register used to hold the stack pointer.
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6.72k
static unsigned getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
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void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
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3.35k
                                      MachineBasicBlock &MBB) const {
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3.35k
  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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3.35k
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3.35k
  MachineFrameInfo &MFI = MF.getFrameInfo();
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3.35k
  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
100
3.35k
  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
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3.35k
  const RISCVInstrInfo *TII = STI.getInstrInfo();
102
3.35k
  MachineBasicBlock::iterator MBBI = MBB.begin();
103
3.35k
104
3.35k
  unsigned FPReg = getFPReg(STI);
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3.35k
  unsigned SPReg = getSPReg(STI);
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3.35k
107
3.35k
  // Debug location must be unknown since the first debug location is used
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3.35k
  // to determine the end of the prologue.
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3.35k
  DebugLoc DL;
110
3.35k
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  // Determine the correct frame layout
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  determineFrameLayout(MF);
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3.35k
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3.35k
  // FIXME (note copied from Lanai): This appears to be overallocating.  Needs
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  // investigation. Get the number of bytes to allocate from the FrameInfo.
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3.35k
  uint64_t StackSize = MFI.getStackSize();
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3.35k
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3.35k
  // Early exit if there is no need to allocate on the stack
119
3.35k
  if (StackSize == 0 && 
!MFI.adjustsStack()1.85k
)
120
1.85k
    return;
121
1.50k
122
1.50k
  // Allocate space on the stack if necessary.
123
1.50k
  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
124
1.50k
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1.50k
  // Emit ".cfi_def_cfa_offset StackSize"
126
1.50k
  unsigned CFIIndex = MF.addFrameInst(
127
1.50k
      MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
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1.50k
  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
129
1.50k
      .addCFIIndex(CFIIndex);
130
1.50k
131
1.50k
  // The frame pointer is callee-saved, and code has been generated for us to
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1.50k
  // save it to the stack. We need to skip over the storing of callee-saved
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1.50k
  // registers as the frame pointer must be modified after it has been saved
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1.50k
  // to the stack, not before.
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1.50k
  // FIXME: assumes exactly one instruction is used to save each callee-saved
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1.50k
  // register.
137
1.50k
  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
138
1.50k
  std::advance(MBBI, CSI.size());
139
1.50k
140
1.50k
  // Iterate over list of callee-saved registers and emit .cfi_offset
141
1.50k
  // directives.
142
3.37k
  for (const auto &Entry : CSI) {
143
3.37k
    int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());
144
3.37k
    unsigned Reg = Entry.getReg();
145
3.37k
    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
146
3.37k
        nullptr, RI->getDwarfRegNum(Reg, true), Offset));
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3.37k
    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
148
3.37k
        .addCFIIndex(CFIIndex);
149
3.37k
  }
150
1.50k
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1.50k
  // Generate new FP.
152
1.50k
  if (hasFP(MF)) {
153
162
    adjustReg(MBB, MBBI, DL, FPReg, SPReg,
154
162
              StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);
155
162
156
162
    // Emit ".cfi_def_cfa $fp, 0"
157
162
    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
158
162
        nullptr, RI->getDwarfRegNum(FPReg, true), 0));
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162
    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
160
162
        .addCFIIndex(CFIIndex);
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162
  }
162
1.50k
}
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void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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3.36k
                                      MachineBasicBlock &MBB) const {
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3.36k
  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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3.36k
  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
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3.36k
  MachineFrameInfo &MFI = MF.getFrameInfo();
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3.36k
  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
170
3.36k
  DebugLoc DL = MBBI->getDebugLoc();
171
3.36k
  const RISCVInstrInfo *TII = STI.getInstrInfo();
172
3.36k
  unsigned FPReg = getFPReg(STI);
173
3.36k
  unsigned SPReg = getSPReg(STI);
174
3.36k
175
3.36k
  // Skip to before the restores of callee-saved registers
176
3.36k
  // FIXME: assumes exactly one instruction is used to restore each
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3.36k
  // callee-saved register.
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3.36k
  auto LastFrameDestroy = std::prev(MBBI, MFI.getCalleeSavedInfo().size());
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3.36k
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3.36k
  uint64_t StackSize = MFI.getStackSize();
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  uint64_t FPOffset = StackSize - RVFI->getVarArgsSaveSize();
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3.36k
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3.36k
  // Restore the stack pointer using the value of the frame pointer. Only
184
3.36k
  // necessary if the stack pointer was modified, meaning the stack size is
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  // unknown.
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3.36k
  if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) {
187
14
    assert(hasFP(MF) && "frame pointer should not have been eliminated");
188
14
    adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
189
14
              MachineInstr::FrameDestroy);
190
14
  }
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3.36k
192
3.36k
  if (hasFP(MF)) {
193
162
    // To find the instruction restoring FP from stack.
194
510
    for (auto &I = LastFrameDestroy; I != MBBI; 
++I348
) {
195
510
      if (I->mayLoad() && I->getOperand(0).isReg()) {
196
510
        unsigned DestReg = I->getOperand(0).getReg();
197
510
        if (DestReg == FPReg) {
198
162
          // If there is frame pointer, after restoring $fp registers, we
199
162
          // need adjust CFA to ($sp - FPOffset).
200
162
          // Emit ".cfi_def_cfa $sp, -FPOffset"
201
162
          unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
202
162
              nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset));
203
162
          BuildMI(MBB, std::next(I), DL,
204
162
                  TII->get(TargetOpcode::CFI_INSTRUCTION))
205
162
              .addCFIIndex(CFIIndex);
206
162
          break;
207
162
        }
208
510
      }
209
510
    }
210
162
  }
211
3.36k
212
3.36k
  // Add CFI directives for callee-saved registers.
213
3.36k
  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
214
3.36k
  // Iterate over list of callee-saved registers and emit .cfi_restore
215
3.36k
  // directives.
216
3.38k
  for (const auto &Entry : CSI) {
217
3.38k
    unsigned Reg = Entry.getReg();
218
3.38k
    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
219
3.38k
        nullptr, RI->getDwarfRegNum(Reg, true)));
220
3.38k
    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
221
3.38k
        .addCFIIndex(CFIIndex);
222
3.38k
  }
223
3.36k
224
3.36k
  // Deallocate stack
225
3.36k
  adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
226
3.36k
227
3.36k
  // After restoring $sp, we need to adjust CFA to $(sp + 0)
228
3.36k
  // Emit ".cfi_def_cfa_offset 0"
229
3.36k
  unsigned CFIIndex =
230
3.36k
      MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
231
3.36k
  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
232
3.36k
      .addCFIIndex(CFIIndex);
233
3.36k
}
234
235
int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
236
                                               int FI,
237
10.7k
                                               unsigned &FrameReg) const {
238
10.7k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
239
10.7k
  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
240
10.7k
  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
241
10.7k
242
10.7k
  // Callee-saved registers should be referenced relative to the stack
243
10.7k
  // pointer (positive offset), otherwise use the frame pointer (negative
244
10.7k
  // offset).
245
10.7k
  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
246
10.7k
  int MinCSFI = 0;
247
10.7k
  int MaxCSFI = -1;
248
10.7k
249
10.7k
  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea() +
250
10.7k
               MFI.getOffsetAdjustment();
251
10.7k
252
10.7k
  if (CSI.size()) {
253
9.66k
    MinCSFI = CSI[0].getFrameIdx();
254
9.66k
    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
255
9.66k
  }
256
10.7k
257
10.7k
  if (FI >= MinCSFI && 
FI <= MaxCSFI7.41k
) {
258
6.75k
    FrameReg = RISCV::X2;
259
6.75k
    Offset += MF.getFrameInfo().getStackSize();
260
6.75k
  } else {
261
4.02k
    FrameReg = RI->getFrameRegister(MF);
262
4.02k
    if (hasFP(MF))
263
532
      Offset += RVFI->getVarArgsSaveSize();
264
3.49k
    else
265
3.49k
      Offset += MF.getFrameInfo().getStackSize();
266
4.02k
  }
267
10.7k
  return Offset;
268
10.7k
}
269
270
void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
271
                                              BitVector &SavedRegs,
272
3.36k
                                              RegScavenger *RS) const {
273
3.36k
  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
274
3.36k
  // Unconditionally spill RA and FP only if the function uses a frame
275
3.36k
  // pointer.
276
3.36k
  if (hasFP(MF)) {
277
163
    SavedRegs.set(RISCV::X1);
278
163
    SavedRegs.set(RISCV::X8);
279
163
  }
280
3.36k
281
3.36k
  // If interrupt is enabled and there are calls in the handler,
282
3.36k
  // unconditionally save all Caller-saved registers and
283
3.36k
  // all FP registers, regardless whether they are used.
284
3.36k
  MachineFrameInfo &MFI = MF.getFrameInfo();
285
3.36k
286
3.36k
  if (MF.getFunction().hasFnAttribute("interrupt") && 
MFI.hasCalls()50
) {
287
20
288
20
    static const MCPhysReg CSRegs[] = { RISCV::X1,      /* ra */
289
20
      RISCV::X5, RISCV::X6, RISCV::X7,                  /* t0-t2 */
290
20
      RISCV::X10, RISCV::X11,                           /* a0-a1, a2-a7 */
291
20
      RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
292
20
      RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
293
20
    };
294
20
295
340
    for (unsigned i = 0; CSRegs[i]; 
++i320
)
296
320
      SavedRegs.set(CSRegs[i]);
297
20
298
20
    if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD() ||
299
20
        
MF.getSubtarget<RISCVSubtarget>().hasStdExtF()16
) {
300
10
301
10
      // If interrupt is enabled, this list contains all FP registers.
302
10
      const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
303
10
304
630
      for (unsigned i = 0; Regs[i]; 
++i620
)
305
620
        if (RISCV::FPR32RegClass.contains(Regs[i]) ||
306
620
            
RISCV::FPR64RegClass.contains(Regs[i])428
)
307
320
          SavedRegs.set(Regs[i]);
308
10
    }
309
20
  }
310
3.36k
}
311
312
void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
313
3.35k
    MachineFunction &MF, RegScavenger *RS) const {
314
3.35k
  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
315
3.35k
  MachineFrameInfo &MFI = MF.getFrameInfo();
316
3.35k
  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
317
3.35k
  // estimateStackSize has been observed to under-estimate the final stack
318
3.35k
  // size, so give ourselves wiggle-room by checking for stack size
319
3.35k
  // representable an 11-bit signed field rather than 12-bits.
320
3.35k
  // FIXME: It may be possible to craft a function with a small stack that
321
3.35k
  // still needs an emergency spill slot for branch relaxation. This case
322
3.35k
  // would currently be missed.
323
3.35k
  if (!isInt<11>(MFI.estimateStackSize(MF))) {
324
4
    int RegScavFI = MFI.CreateStackObject(
325
4
        RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);
326
4
    RS->addScavengingFrameIndex(RegScavFI);
327
4
  }
328
3.35k
}
329
330
// Not preserve stack space within prologue for outgoing variables when the
331
// function contains variable size objects and let eliminateCallFramePseudoInstr
332
// preserve stack space for it.
333
7.89k
bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
334
7.89k
  return !MF.getFrameInfo().hasVarSizedObjects();
335
7.89k
}
336
337
// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
338
MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr(
339
    MachineFunction &MF, MachineBasicBlock &MBB,
340
2.68k
    MachineBasicBlock::iterator MI) const {
341
2.68k
  unsigned SPReg = RISCV::X2;
342
2.68k
  DebugLoc DL = MI->getDebugLoc();
343
2.68k
344
2.68k
  if (!hasReservedCallFrame(MF)) {
345
56
    // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
346
56
    // ADJCALLSTACKUP must be converted to instructions manipulating the stack
347
56
    // pointer. This is necessary when there is a variable length stack
348
56
    // allocation (e.g. alloca), which means it's not possible to allocate
349
56
    // space for outgoing arguments from within the function prologue.
350
56
    int64_t Amount = MI->getOperand(0).getImm();
351
56
352
56
    if (Amount != 0) {
353
2
      // Ensure the stack remains aligned after adjustment.
354
2
      Amount = alignSPAdjust(Amount);
355
2
356
2
      if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
357
1
        Amount = -Amount;
358
2
359
2
      adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
360
2
    }
361
56
  }
362
2.68k
363
2.68k
  return MBB.erase(MI);
364
2.68k
}