Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVISelLowering.h
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//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that RISCV uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#include "RISCV.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class RISCVSubtarget;
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namespace RISCVISD {
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enum NodeType : unsigned {
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  FIRST_NUMBER = ISD::BUILTIN_OP_END,
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  RET_FLAG,
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  URET_FLAG,
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  SRET_FLAG,
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  MRET_FLAG,
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  CALL,
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  SELECT_CC,
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  BuildPairF64,
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  SplitF64,
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  TAIL,
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  // RV64I shifts, directly matching the semantics of the named RISC-V
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  // instructions.
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  SLLW,
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  SRAW,
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  SRLW,
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  // 32-bit operations from RV64M that can't be simply matched with a pattern
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  // at instruction selection time.
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  DIVW,
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  DIVUW,
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  REMUW,
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  // FPR32<->GPR transfer operations for RV64. Needed as an i32<->f32 bitcast
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  // is not legal on RV64. FMV_W_X_RV64 matches the semantics of the FMV.W.X.
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  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
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  // This is a more convenient semantic for producing dagcombines that remove
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  // unnecessary GPR->FPR->GPR moves.
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  FMV_W_X_RV64,
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  FMV_X_ANYEXTW_RV64,
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  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
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  // (returns (Lo, Hi)). It takes a chain operand.
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  READ_CYCLE_WIDE
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};
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}
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class RISCVTargetLowering : public TargetLowering {
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  const RISCVSubtarget &Subtarget;
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public:
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  explicit RISCVTargetLowering(const TargetMachine &TM,
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                               const RISCVSubtarget &STI);
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  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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                          MachineFunction &MF,
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                          unsigned Intrinsic) const override;
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  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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                             unsigned AS,
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                             Instruction *I = nullptr) const override;
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  bool isLegalICmpImmediate(int64_t Imm) const override;
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  bool isLegalAddImmediate(int64_t Imm) const override;
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  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
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  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
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  bool isZExtFree(SDValue Val, EVT VT2) const override;
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  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
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  bool hasBitPreservingFPLogic(EVT VT) const override;
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  // Provide custom lowering hooks for some operations.
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  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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                          SelectionDAG &DAG) const override;
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  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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  unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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                                           const APInt &DemandedElts,
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                                           const SelectionDAG &DAG,
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                                           unsigned Depth) const override;
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  // This method returns the name of a target specific DAG node.
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  const char *getTargetNodeName(unsigned Opcode) const override;
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  std::pair<unsigned, const TargetRegisterClass *>
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  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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                               StringRef Constraint, MVT VT) const override;
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  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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                                    std::vector<SDValue> &Ops,
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                                    SelectionDAG &DAG) const override;
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  MachineBasicBlock *
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  EmitInstrWithCustomInserter(MachineInstr &MI,
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                              MachineBasicBlock *BB) const override;
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  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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                         EVT VT) const override;
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  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
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    return VT.isScalarInteger();
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  }
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  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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    return isa<LoadInst>(I) || 
isa<StoreInst>(I)484
;
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  }
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  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
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                                AtomicOrdering Ord) const override;
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  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
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                                 AtomicOrdering Ord) const override;
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  ISD::NodeType getExtendForAtomicOps() const override {
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    return ISD::SIGN_EXTEND;
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  }
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  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
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    if (DAG.getMachineFunction().getFunction().hasMinSize())
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      return false;
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    return true;
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  }
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  bool isDesirableToCommuteWithShift(const SDNode *N,
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                                     CombineLevel Level) const override;
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  /// If a physical register, this returns the register that receives the
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  /// exception address on entry to an EH pad.
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  unsigned
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  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
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  /// If a physical register, this returns the register that receives the
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  /// exception typeid on entry to a landing pad.
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  unsigned
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  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
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private:
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  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
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                        const SmallVectorImpl<ISD::InputArg> &Ins,
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                        bool IsRet) const;
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  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
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                         const SmallVectorImpl<ISD::OutputArg> &Outs,
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                         bool IsRet, CallLoweringInfo *CLI) const;
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  // Lower incoming arguments, copy physregs into vregs
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  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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                               bool IsVarArg,
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                               const SmallVectorImpl<ISD::InputArg> &Ins,
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                               const SDLoc &DL, SelectionDAG &DAG,
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                               SmallVectorImpl<SDValue> &InVals) const override;
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  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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                      bool IsVarArg,
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                      const SmallVectorImpl<ISD::OutputArg> &Outs,
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                      LLVMContext &Context) const override;
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  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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                      const SmallVectorImpl<ISD::OutputArg> &Outs,
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                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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                      SelectionDAG &DAG) const override;
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  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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                    SmallVectorImpl<SDValue> &InVals) const override;
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  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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                                         Type *Ty) const override {
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    return true;
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  }
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  template <class NodeTy>
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  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
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  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
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                           bool UseGOT) const;
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  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
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  bool shouldConsiderGEPOffsetSplit() const override { return true; }
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  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
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  bool isEligibleForTailCallOptimization(
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      CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
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      const SmallVector<CCValAssign, 16> &ArgLocs) const;
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  TargetLowering::AtomicExpansionKind
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  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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  virtual Value *emitMaskedAtomicRMWIntrinsic(
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      IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
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      Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override;
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  TargetLowering::AtomicExpansionKind
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  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
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  virtual Value *
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  emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI,
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                                   Value *AlignedAddr, Value *CmpVal,
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                                   Value *NewVal, Value *Mask,
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                                   AtomicOrdering Ord) const override;
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};
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}
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#endif