Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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//===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the RISCV implementation of the TargetInstrInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "RISCVInstrInfo.h"
14
#include "RISCV.h"
15
#include "RISCVSubtarget.h"
16
#include "RISCVTargetMachine.h"
17
#include "llvm/ADT/STLExtras.h"
18
#include "llvm/ADT/SmallVector.h"
19
#include "llvm/CodeGen/MachineFunctionPass.h"
20
#include "llvm/CodeGen/MachineInstrBuilder.h"
21
#include "llvm/CodeGen/MachineRegisterInfo.h"
22
#include "llvm/CodeGen/RegisterScavenging.h"
23
#include "llvm/Support/ErrorHandling.h"
24
#include "llvm/Support/TargetRegistry.h"
25
26
#define GET_INSTRINFO_CTOR_DTOR
27
#include "RISCVGenInstrInfo.inc"
28
29
using namespace llvm;
30
31
RISCVInstrInfo::RISCVInstrInfo()
32
373
    : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {}
33
34
unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
35
7.34k
                                             int &FrameIndex) const {
36
7.34k
  switch (MI.getOpcode()) {
37
7.34k
  default:
38
6.57k
    return 0;
39
7.34k
  case RISCV::LB:
40
773
  case RISCV::LBU:
41
773
  case RISCV::LH:
42
773
  case RISCV::LHU:
43
773
  case RISCV::LW:
44
773
  case RISCV::FLW:
45
773
  case RISCV::LWU:
46
773
  case RISCV::LD:
47
773
  case RISCV::FLD:
48
773
    break;
49
773
  }
50
773
51
773
  if (MI.getOperand(1).isFI() && 
MI.getOperand(2).isImm()220
&&
52
773
      
MI.getOperand(2).getImm() == 0220
) {
53
180
    FrameIndex = MI.getOperand(1).getIndex();
54
180
    return MI.getOperand(0).getReg();
55
180
  }
56
593
57
593
  return 0;
58
593
}
59
60
unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
61
4.51k
                                            int &FrameIndex) const {
62
4.51k
  switch (MI.getOpcode()) {
63
4.51k
  default:
64
3.75k
    return 0;
65
4.51k
  case RISCV::SB:
66
755
  case RISCV::SH:
67
755
  case RISCV::SW:
68
755
  case RISCV::FSW:
69
755
  case RISCV::SD:
70
755
  case RISCV::FSD:
71
755
    break;
72
755
  }
73
755
74
755
  if (MI.getOperand(0).isFI() && 
MI.getOperand(1).isImm()0
&&
75
755
      
MI.getOperand(1).getImm() == 00
) {
76
0
    FrameIndex = MI.getOperand(0).getIndex();
77
0
    return MI.getOperand(2).getReg();
78
0
  }
79
755
80
755
  return 0;
81
755
}
82
83
void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
84
                                 MachineBasicBlock::iterator MBBI,
85
                                 const DebugLoc &DL, unsigned DstReg,
86
2.17k
                                 unsigned SrcReg, bool KillSrc) const {
87
2.17k
  if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
88
2.12k
    BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
89
2.12k
        .addReg(SrcReg, getKillRegState(KillSrc))
90
2.12k
        .addImm(0);
91
2.12k
    return;
92
2.12k
  }
93
57
94
57
  // FPR->FPR copies
95
57
  unsigned Opc;
96
57
  if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
97
28
    Opc = RISCV::FSGNJ_S;
98
29
  else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
99
29
    Opc = RISCV::FSGNJ_D;
100
29
  else
101
29
    
llvm_unreachable0
("Impossible reg-to-reg copy");
102
57
103
57
  BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
104
57
      .addReg(SrcReg, getKillRegState(KillSrc))
105
57
      .addReg(SrcReg, getKillRegState(KillSrc));
106
57
}
107
108
void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
109
                                         MachineBasicBlock::iterator I,
110
                                         unsigned SrcReg, bool IsKill, int FI,
111
                                         const TargetRegisterClass *RC,
112
3.95k
                                         const TargetRegisterInfo *TRI) const {
113
3.95k
  DebugLoc DL;
114
3.95k
  if (I != MBB.end())
115
3.95k
    DL = I->getDebugLoc();
116
3.95k
117
3.95k
  unsigned Opcode;
118
3.95k
119
3.95k
  if (RISCV::GPRRegClass.hasSubClassEq(RC))
120
3.17k
    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
121
1.93k
             RISCV::SW : 
RISCV::SD1.24k
;
122
784
  else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
123
391
    Opcode = RISCV::FSW;
124
393
  else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
125
393
    Opcode = RISCV::FSD;
126
393
  else
127
393
    
llvm_unreachable0
("Can't store this register to stack slot");
128
3.95k
129
3.95k
  BuildMI(MBB, I, DL, get(Opcode))
130
3.95k
      .addReg(SrcReg, getKillRegState(IsKill))
131
3.95k
      .addFrameIndex(FI)
132
3.95k
      .addImm(0);
133
3.95k
}
134
135
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
136
                                          MachineBasicBlock::iterator I,
137
                                          unsigned DstReg, int FI,
138
                                          const TargetRegisterClass *RC,
139
4.08k
                                          const TargetRegisterInfo *TRI) const {
140
4.08k
  DebugLoc DL;
141
4.08k
  if (I != MBB.end())
142
4.08k
    DL = I->getDebugLoc();
143
4.08k
144
4.08k
  unsigned Opcode;
145
4.08k
146
4.08k
  if (RISCV::GPRRegClass.hasSubClassEq(RC))
147
3.18k
    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
148
1.93k
             RISCV::LW : 
RISCV::LD1.24k
;
149
904
  else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
150
391
    Opcode = RISCV::FLW;
151
513
  else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
152
513
    Opcode = RISCV::FLD;
153
513
  else
154
513
    
llvm_unreachable0
("Can't load this register from stack slot");
155
4.08k
156
4.08k
  BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
157
4.08k
}
158
159
void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
160
                              MachineBasicBlock::iterator MBBI,
161
                              const DebugLoc &DL, unsigned DstReg, uint64_t Val,
162
27
                              MachineInstr::MIFlag Flag) const {
163
27
  assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
164
27
165
27
  // TODO: If the value can be materialized using only one instruction, only
166
27
  // insert a single instruction.
167
27
168
27
  uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
169
27
  uint64_t Lo12 = SignExtend64<12>(Val);
170
27
  BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
171
27
      .addImm(Hi20)
172
27
      .setMIFlag(Flag);
173
27
  BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
174
27
      .addReg(DstReg, RegState::Kill)
175
27
      .addImm(Lo12)
176
27
      .setMIFlag(Flag);
177
27
}
178
179
// The contents of values added to Cond are not examined outside of
180
// RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
181
// push BranchOpcode, Reg1, Reg2.
182
static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
183
27.5k
                            SmallVectorImpl<MachineOperand> &Cond) {
184
27.5k
  // Block ends with fall-through condbranch.
185
27.5k
  assert(LastInst.getDesc().isConditionalBranch() &&
186
27.5k
         "Unknown conditional branch");
187
27.5k
  Target = LastInst.getOperand(2).getMBB();
188
27.5k
  Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
189
27.5k
  Cond.push_back(LastInst.getOperand(0));
190
27.5k
  Cond.push_back(LastInst.getOperand(1));
191
27.5k
}
192
193
1.97k
static unsigned getOppositeBranchOpcode(int Opc) {
194
1.97k
  switch (Opc) {
195
1.97k
  default:
196
0
    llvm_unreachable("Unrecognized conditional branch");
197
1.97k
  case RISCV::BEQ:
198
725
    return RISCV::BNE;
199
1.97k
  case RISCV::BNE:
200
551
    return RISCV::BEQ;
201
1.97k
  case RISCV::BLT:
202
182
    return RISCV::BGE;
203
1.97k
  case RISCV::BGE:
204
182
    return RISCV::BLT;
205
1.97k
  case RISCV::BLTU:
206
166
    return RISCV::BGEU;
207
1.97k
  case RISCV::BGEU:
208
166
    return RISCV::BLTU;
209
1.97k
  }
210
1.97k
}
211
212
bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
213
                                   MachineBasicBlock *&TBB,
214
                                   MachineBasicBlock *&FBB,
215
                                   SmallVectorImpl<MachineOperand> &Cond,
216
147k
                                   bool AllowModify) const {
217
147k
  TBB = FBB = nullptr;
218
147k
  Cond.clear();
219
147k
220
147k
  // If the block has no terminators, it just falls into the block after it.
221
147k
  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
222
147k
  if (I == MBB.end() || 
!isUnpredicatedTerminator(*I)144k
)
223
22.5k
    return false;
224
124k
225
124k
  // Count the number of terminators and find the first unconditional or
226
124k
  // indirect branch.
227
124k
  MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
228
124k
  int NumTerminators = 0;
229
255k
  for (auto J = I.getReverse(); J != MBB.rend() && 
isUnpredicatedTerminator(*J)251k
;
230
130k
       J++) {
231
130k
    NumTerminators++;
232
130k
    if (J->getDesc().isUnconditionalBranch() ||
233
130k
        
J->getDesc().isIndirectBranch()120k
) {
234
10.9k
      FirstUncondOrIndirectBr = J.getReverse();
235
10.9k
    }
236
130k
  }
237
124k
238
124k
  // If AllowModify is true, we can erase any terminators after
239
124k
  // FirstUncondOrIndirectBR.
240
124k
  if (AllowModify && 
FirstUncondOrIndirectBr != MBB.end()15.4k
) {
241
2.22k
    while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
242
0
      std::next(FirstUncondOrIndirectBr)->eraseFromParent();
243
0
      NumTerminators--;
244
0
    }
245
2.22k
    I = FirstUncondOrIndirectBr;
246
2.22k
  }
247
124k
248
124k
  // We can't handle blocks that end in an indirect branch.
249
124k
  if (I->getDesc().isIndirectBranch())
250
212
    return true;
251
124k
252
124k
  // We can't handle blocks with more than 2 terminators.
253
124k
  if (NumTerminators > 2)
254
0
    return true;
255
124k
256
124k
  // Handle a single unconditional branch.
257
124k
  if (NumTerminators == 1 && 
I->getDesc().isUnconditionalBranch()118k
) {
258
4.35k
    TBB = I->getOperand(0).getMBB();
259
4.35k
    return false;
260
4.35k
  }
261
120k
262
120k
  // Handle a single conditional branch.
263
120k
  if (NumTerminators == 1 && 
I->getDesc().isConditionalBranch()113k
) {
264
21.1k
    parseCondBranch(*I, TBB, Cond);
265
21.1k
    return false;
266
21.1k
  }
267
98.8k
268
98.8k
  // Handle a conditional branch followed by an unconditional branch.
269
98.8k
  if (NumTerminators == 2 && 
std::prev(I)->getDesc().isConditionalBranch()6.36k
&&
270
98.8k
      
I->getDesc().isUnconditionalBranch()6.36k
) {
271
6.36k
    parseCondBranch(*std::prev(I), TBB, Cond);
272
6.36k
    FBB = I->getOperand(0).getMBB();
273
6.36k
    return false;
274
6.36k
  }
275
92.5k
276
92.5k
  // Otherwise, we can't handle this.
277
92.5k
  return true;
278
92.5k
}
279
280
unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
281
2.67k
                                      int *BytesRemoved) const {
282
2.67k
  if (BytesRemoved)
283
4
    *BytesRemoved = 0;
284
2.67k
  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
285
2.67k
  if (I == MBB.end())
286
0
    return 0;
287
2.67k
288
2.67k
  if (!I->getDesc().isUnconditionalBranch() &&
289
2.67k
      
!I->getDesc().isConditionalBranch()1.93k
)
290
129
    return 0;
291
2.54k
292
2.54k
  // Remove the branch.
293
2.54k
  if (BytesRemoved)
294
4
    *BytesRemoved += getInstSizeInBytes(*I);
295
2.54k
  I->eraseFromParent();
296
2.54k
297
2.54k
  I = MBB.end();
298
2.54k
299
2.54k
  if (I == MBB.begin())
300
134
    return 1;
301
2.41k
  --I;
302
2.41k
  if (!I->getDesc().isConditionalBranch())
303
2.10k
    return 1;
304
307
305
307
  // Remove the branch.
306
307
  if (BytesRemoved)
307
0
    *BytesRemoved += getInstSizeInBytes(*I);
308
307
  I->eraseFromParent();
309
307
  return 2;
310
307
}
311
312
// Inserts a branch into the end of the specific MachineBasicBlock, returning
313
// the number of instructions inserted.
314
unsigned RISCVInstrInfo::insertBranch(
315
    MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
316
2.87k
    ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
317
2.87k
  if (BytesAdded)
318
4
    *BytesAdded = 0;
319
2.87k
320
2.87k
  // Shouldn't be a fall through.
321
2.87k
  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
322
2.87k
  assert((Cond.size() == 3 || Cond.size() == 0) &&
323
2.87k
         "RISCV branch conditions have two components!");
324
2.87k
325
2.87k
  // Unconditional branch.
326
2.87k
  if (Cond.empty()) {
327
769
    MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
328
769
    if (BytesAdded)
329
0
      *BytesAdded += getInstSizeInBytes(MI);
330
769
    return 1;
331
769
  }
332
2.10k
333
2.10k
  // Either a one or two-way conditional branch.
334
2.10k
  unsigned Opc = Cond[0].getImm();
335
2.10k
  MachineInstr &CondMI =
336
2.10k
      *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
337
2.10k
  if (BytesAdded)
338
4
    *BytesAdded += getInstSizeInBytes(CondMI);
339
2.10k
340
2.10k
  // One-way conditional branch.
341
2.10k
  if (!FBB)
342
2.06k
    return 1;
343
48
344
48
  // Two-way conditional branch.
345
48
  MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
346
48
  if (BytesAdded)
347
4
    *BytesAdded += getInstSizeInBytes(MI);
348
48
  return 2;
349
48
}
350
351
unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
352
                                              MachineBasicBlock &DestBB,
353
                                              const DebugLoc &DL,
354
                                              int64_t BrOffset,
355
2
                                              RegScavenger *RS) const {
356
2
  assert(RS && "RegScavenger required for long branching");
357
2
  assert(MBB.empty() &&
358
2
         "new block should be inserted for expanding unconditional branch");
359
2
  assert(MBB.pred_size() == 1);
360
2
361
2
  MachineFunction *MF = MBB.getParent();
362
2
  MachineRegisterInfo &MRI = MF->getRegInfo();
363
2
  const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
364
2
365
2
  if (TM.isPositionIndependent())
366
0
    report_fatal_error("Unable to insert indirect branch");
367
2
368
2
  if (!isInt<32>(BrOffset))
369
0
    report_fatal_error(
370
0
        "Branch offsets outside of the signed 32-bit range not supported");
371
2
372
2
  // FIXME: A virtual register must be used initially, as the register
373
2
  // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
374
2
  // uses the same workaround).
375
2
  unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
376
2
  auto II = MBB.end();
377
2
378
2
  MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
379
2
                             .addMBB(&DestBB, RISCVII::MO_HI);
380
2
  BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
381
2
      .addReg(ScratchReg, RegState::Kill)
382
2
      .addMBB(&DestBB, RISCVII::MO_LO);
383
2
384
2
  RS->enterBasicBlockEnd(MBB);
385
2
  unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
386
2
                                                LuiMI.getIterator(), false, 0);
387
2
  MRI.replaceRegWith(ScratchReg, Scav);
388
2
  MRI.clearVirtRegs();
389
2
  RS->setRegUsed(Scav);
390
2
  return 8;
391
2
}
392
393
bool RISCVInstrInfo::reverseBranchCondition(
394
1.97k
    SmallVectorImpl<MachineOperand> &Cond) const {
395
1.97k
  assert((Cond.size() == 3) && "Invalid branch condition!");
396
1.97k
  Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
397
1.97k
  return false;
398
1.97k
}
399
400
MachineBasicBlock *
401
1.13k
RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
402
1.13k
  assert(MI.getDesc().isBranch() && "Unexpected opcode!");
403
1.13k
  // The branch target is always the last operand.
404
1.13k
  int NumOp = MI.getNumExplicitOperands();
405
1.13k
  return MI.getOperand(NumOp - 1).getMBB();
406
1.13k
}
407
408
bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
409
1.13k
                                           int64_t BrOffset) const {
410
1.13k
  // Ideally we could determine the supported branch offset from the
411
1.13k
  // RISCVII::FormMask, but this can't be used for Pseudo instructions like
412
1.13k
  // PseudoBR.
413
1.13k
  switch (BranchOp) {
414
1.13k
  default:
415
0
    llvm_unreachable("Unexpected opcode!");
416
1.13k
  case RISCV::BEQ:
417
742
  case RISCV::BNE:
418
742
  case RISCV::BLT:
419
742
  case RISCV::BGE:
420
742
  case RISCV::BLTU:
421
742
  case RISCV::BGEU:
422
742
    return isIntN(13, BrOffset);
423
742
  case RISCV::JAL:
424
393
  case RISCV::PseudoBR:
425
393
    return isIntN(21, BrOffset);
426
1.13k
  }
427
1.13k
}
428
429
55.5k
unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
430
55.5k
  unsigned Opcode = MI.getOpcode();
431
55.5k
432
55.5k
  switch (Opcode) {
433
55.5k
  
default: { return get(Opcode).getSize()53.8k
; }
434
55.5k
  case TargetOpcode::EH_LABEL:
435
46
  case TargetOpcode::IMPLICIT_DEF:
436
46
  case TargetOpcode::KILL:
437
46
  case TargetOpcode::DBG_VALUE:
438
46
    return 0;
439
1.56k
  case RISCV::PseudoCALLReg:
440
1.56k
  case RISCV::PseudoCALL:
441
1.56k
  case RISCV::PseudoTAIL:
442
1.56k
  case RISCV::PseudoLLA:
443
1.56k
  case RISCV::PseudoLA:
444
1.56k
  case RISCV::PseudoLA_TLS_IE:
445
1.56k
  case RISCV::PseudoLA_TLS_GD:
446
1.56k
    return 8;
447
1.56k
  case TargetOpcode::INLINEASM:
448
46
  case TargetOpcode::INLINEASM_BR: {
449
46
    const MachineFunction &MF = *MI.getParent()->getParent();
450
46
    const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
451
46
    return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
452
46
                              *TM.getMCAsmInfo());
453
46
  }
454
55.5k
  }
455
55.5k
}
456
457
5.13k
bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
458
5.13k
  const unsigned Opcode = MI.getOpcode();
459
5.13k
  switch(Opcode) {
460
5.13k
    default:
461
3.06k
      break;
462
5.13k
    case RISCV::ADDI:
463
2.07k
    case RISCV::ORI:
464
2.07k
    case RISCV::XORI:
465
2.07k
      return (MI.getOperand(1).isReg() && 
MI.getOperand(1).getReg() == RISCV::X01.51k
);
466
3.06k
  }
467
3.06k
  return MI.isAsCheapAsAMove();
468
3.06k
}