/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
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1 | | //===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file contains code to lower RISCV MachineInstrs to their corresponding |
10 | | // MCInst records. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "RISCV.h" |
15 | | #include "MCTargetDesc/RISCVMCExpr.h" |
16 | | #include "llvm/CodeGen/AsmPrinter.h" |
17 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
18 | | #include "llvm/CodeGen/MachineInstr.h" |
19 | | #include "llvm/MC/MCAsmInfo.h" |
20 | | #include "llvm/MC/MCContext.h" |
21 | | #include "llvm/MC/MCExpr.h" |
22 | | #include "llvm/MC/MCInst.h" |
23 | | #include "llvm/Support/ErrorHandling.h" |
24 | | #include "llvm/Support/raw_ostream.h" |
25 | | |
26 | | using namespace llvm; |
27 | | |
28 | | static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, |
29 | 3.55k | const AsmPrinter &AP) { |
30 | 3.55k | MCContext &Ctx = AP.OutContext; |
31 | 3.55k | RISCVMCExpr::VariantKind Kind; |
32 | 3.55k | |
33 | 3.55k | switch (MO.getTargetFlags()) { |
34 | 3.55k | default: |
35 | 0 | llvm_unreachable("Unknown target flag on GV operand"); |
36 | 3.55k | case RISCVII::MO_None: |
37 | 1.52k | Kind = RISCVMCExpr::VK_RISCV_None; |
38 | 1.52k | break; |
39 | 3.55k | case RISCVII::MO_CALL: |
40 | 1.31k | Kind = RISCVMCExpr::VK_RISCV_CALL; |
41 | 1.31k | break; |
42 | 3.55k | case RISCVII::MO_PLT: |
43 | 21 | Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; |
44 | 21 | break; |
45 | 3.55k | case RISCVII::MO_LO: |
46 | 374 | Kind = RISCVMCExpr::VK_RISCV_LO; |
47 | 374 | break; |
48 | 3.55k | case RISCVII::MO_HI: |
49 | 262 | Kind = RISCVMCExpr::VK_RISCV_HI; |
50 | 262 | break; |
51 | 3.55k | case RISCVII::MO_PCREL_LO: |
52 | 14 | Kind = RISCVMCExpr::VK_RISCV_PCREL_LO; |
53 | 14 | break; |
54 | 3.55k | case RISCVII::MO_PCREL_HI: |
55 | 6 | Kind = RISCVMCExpr::VK_RISCV_PCREL_HI; |
56 | 6 | break; |
57 | 3.55k | case RISCVII::MO_GOT_HI: |
58 | 2 | Kind = RISCVMCExpr::VK_RISCV_GOT_HI; |
59 | 2 | break; |
60 | 3.55k | case RISCVII::MO_TPREL_LO: |
61 | 10 | Kind = RISCVMCExpr::VK_RISCV_TPREL_LO; |
62 | 10 | break; |
63 | 3.55k | case RISCVII::MO_TPREL_HI: |
64 | 10 | Kind = RISCVMCExpr::VK_RISCV_TPREL_HI; |
65 | 10 | break; |
66 | 3.55k | case RISCVII::MO_TPREL_ADD: |
67 | 10 | Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD; |
68 | 10 | break; |
69 | 3.55k | case RISCVII::MO_TLS_GOT_HI: |
70 | 2 | Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI; |
71 | 2 | break; |
72 | 3.55k | case RISCVII::MO_TLS_GD_HI: |
73 | 4 | Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI; |
74 | 4 | break; |
75 | 3.55k | } |
76 | 3.55k | |
77 | 3.55k | const MCExpr *ME = |
78 | 3.55k | MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx); |
79 | 3.55k | |
80 | 3.55k | if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()2.01k ) |
81 | 12 | ME = MCBinaryExpr::createAdd( |
82 | 12 | ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); |
83 | 3.55k | |
84 | 3.55k | if (Kind != RISCVMCExpr::VK_RISCV_None) |
85 | 2.03k | ME = RISCVMCExpr::create(ME, Kind, Ctx); |
86 | 3.55k | return MCOperand::createExpr(ME); |
87 | 3.55k | } |
88 | | |
89 | | bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, |
90 | | MCOperand &MCOp, |
91 | 106k | const AsmPrinter &AP) { |
92 | 106k | switch (MO.getType()) { |
93 | 106k | default: |
94 | 0 | report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type"); |
95 | 106k | case MachineOperand::MO_Register: |
96 | 76.5k | // Ignore all implicit register operands. |
97 | 76.5k | if (MO.isImplicit()) |
98 | 7.88k | return false; |
99 | 68.6k | MCOp = MCOperand::createReg(MO.getReg()); |
100 | 68.6k | break; |
101 | 68.6k | case MachineOperand::MO_RegisterMask: |
102 | 1.32k | // Regmasks are like implicit defs. |
103 | 1.32k | return false; |
104 | 68.6k | case MachineOperand::MO_Immediate: |
105 | 25.4k | MCOp = MCOperand::createImm(MO.getImm()); |
106 | 25.4k | break; |
107 | 68.6k | case MachineOperand::MO_MachineBasicBlock: |
108 | 1.53k | MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP); |
109 | 1.53k | break; |
110 | 68.6k | case MachineOperand::MO_GlobalAddress: |
111 | 1.60k | MCOp = lowerSymbolOperand(MO, AP.getSymbol(MO.getGlobal()), AP); |
112 | 1.60k | break; |
113 | 68.6k | case MachineOperand::MO_BlockAddress: |
114 | 5 | MCOp = lowerSymbolOperand( |
115 | 5 | MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP); |
116 | 5 | break; |
117 | 68.6k | case MachineOperand::MO_ExternalSymbol: |
118 | 226 | MCOp = lowerSymbolOperand( |
119 | 226 | MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP); |
120 | 226 | break; |
121 | 68.6k | case MachineOperand::MO_ConstantPoolIndex: |
122 | 175 | MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP); |
123 | 175 | break; |
124 | 97.6k | } |
125 | 97.6k | return true; |
126 | 97.6k | } |
127 | | |
128 | | void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, |
129 | 33.8k | const AsmPrinter &AP) { |
130 | 33.8k | OutMI.setOpcode(MI->getOpcode()); |
131 | 33.8k | |
132 | 106k | for (const MachineOperand &MO : MI->operands()) { |
133 | 106k | MCOperand MCOp; |
134 | 106k | if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP)) |
135 | 97.2k | OutMI.addOperand(MCOp); |
136 | 106k | } |
137 | 33.8k | } |