Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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//===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVRegisterInfo.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_TARGET_DESC
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#include "RISCVGenRegisterInfo.inc"
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using namespace llvm;
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RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
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    : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
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                           /*PC*/0, HwMode) {}
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const MCPhysReg *
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RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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  auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
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  if (MF->getFunction().hasFnAttribute("interrupt")) {
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    if (Subtarget.hasStdExtD())
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      return CSR_XLEN_F64_Interrupt_SaveList;
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    if (Subtarget.hasStdExtF())
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      return CSR_XLEN_F32_Interrupt_SaveList;
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    return CSR_Interrupt_SaveList;
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  }
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  switch (Subtarget.getTargetABI()) {
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  default:
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    llvm_unreachable("Unrecognized ABI");
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  case RISCVABI::ABI_ILP32:
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  case RISCVABI::ABI_LP64:
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    return CSR_ILP32_LP64_SaveList;
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  case RISCVABI::ABI_ILP32F:
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  case RISCVABI::ABI_LP64F:
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    return CSR_ILP32F_LP64F_SaveList;
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  case RISCVABI::ABI_ILP32D:
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  case RISCVABI::ABI_LP64D:
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    return CSR_ILP32D_LP64D_SaveList;
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  }
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}
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BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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  const TargetFrameLowering *TFI = getFrameLowering(MF);
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  BitVector Reserved(getNumRegs());
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  // Use markSuperRegs to ensure any register aliases are also reserved
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  markSuperRegs(Reserved, RISCV::X0); // zero
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  markSuperRegs(Reserved, RISCV::X1); // ra
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  markSuperRegs(Reserved, RISCV::X2); // sp
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  markSuperRegs(Reserved, RISCV::X3); // gp
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  markSuperRegs(Reserved, RISCV::X4); // tp
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  if (TFI->hasFP(MF))
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    markSuperRegs(Reserved, RISCV::X8); // fp
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  assert(checkAllSuperRegsMarked(Reserved));
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  return Reserved;
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}
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bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
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  return PhysReg == RISCV::X0;
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}
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const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
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  return CSR_NoRegs_RegMask;
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}
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void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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                                            int SPAdj, unsigned FIOperandNum,
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                                            RegScavenger *RS) const {
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  assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
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  MachineInstr &MI = *II;
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  MachineFunction &MF = *MI.getParent()->getParent();
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  MachineRegisterInfo &MRI = MF.getRegInfo();
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  const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
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  DebugLoc DL = MI.getDebugLoc();
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  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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  unsigned FrameReg;
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  int Offset =
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      getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
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      MI.getOperand(FIOperandNum + 1).getImm();
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  if (!isInt<32>(Offset)) {
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    report_fatal_error(
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        "Frame offsets outside of the signed 32-bit range not supported");
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  }
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  MachineBasicBlock &MBB = *MI.getParent();
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  bool FrameRegIsKill = false;
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  if (!isInt<12>(Offset)) {
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    assert(isInt<32>(Offset) && "Int32 expected");
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    // The offset won't fit in an immediate, so use a scratch register instead
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    // Modify Offset and FrameReg appropriately
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    unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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    TII->movImm32(MBB, II, DL, ScratchReg, Offset);
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    BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
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        .addReg(FrameReg)
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        .addReg(ScratchReg, RegState::Kill);
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    Offset = 0;
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    FrameReg = ScratchReg;
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    FrameRegIsKill = true;
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  }
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  MI.getOperand(FIOperandNum)
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      .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
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  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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  const TargetFrameLowering *TFI = getFrameLowering(MF);
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  return TFI->hasFP(MF) ? 
RISCV::X8543
:
RISCV::X23.50k
;
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}
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const uint32_t *
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RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
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                                        CallingConv::ID /*CC*/) const {
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  auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
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  if (MF.getFunction().hasFnAttribute("interrupt")) {
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    if (Subtarget.hasStdExtD())
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      return CSR_XLEN_F64_Interrupt_RegMask;
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    if (Subtarget.hasStdExtF())
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      return CSR_XLEN_F32_Interrupt_RegMask;
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    return CSR_Interrupt_RegMask;
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  }
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  switch (Subtarget.getTargetABI()) {
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  default:
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    llvm_unreachable("Unrecognized ABI");
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  case RISCVABI::ABI_ILP32:
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  case RISCVABI::ABI_LP64:
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    return CSR_ILP32_LP64_RegMask;
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  case RISCVABI::ABI_ILP32F:
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  case RISCVABI::ABI_LP64F:
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    return CSR_ILP32F_LP64F_RegMask;
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  case RISCVABI::ABI_ILP32D:
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  case RISCVABI::ABI_LP64D:
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    return CSR_ILP32D_LP64D_RegMask;
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  }
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}