Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
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//===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "RISCVGenRegisterInfo.inc"
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namespace llvm {
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struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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  RISCVRegisterInfo(unsigned HwMode);
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  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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                                       CallingConv::ID) const override;
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  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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  BitVector getReservedRegs(const MachineFunction &MF) const override;
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  bool isConstantPhysReg(unsigned PhysReg) const override;
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  const uint32_t *getNoPreservedMask() const override;
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  void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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                           unsigned FIOperandNum,
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                           RegScavenger *RS = nullptr) const override;
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  Register getFrameRegister(const MachineFunction &MF) const override;
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  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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    return true;
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  }
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  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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    return true;
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  }
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  bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
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    return true;
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  }
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};
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}
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#endif