Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
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//===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCV specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVSubtarget.h"
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#include "RISCV.h"
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#include "RISCVFrameLowering.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "RISCVGenSubtargetInfo.inc"
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void RISCVSubtarget::anchor() {}
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RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
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    const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
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  // Determine default and user-specified characteristics
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  bool Is64Bit = TT.isArch64Bit();
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  std::string CPUName = CPU;
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  if (CPUName.empty())
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    CPUName = Is64Bit ? 
"generic-rv64"148
:
"generic-rv32"226
;
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  ParseSubtargetFeatures(CPUName, FS);
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  if (Is64Bit) {
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    XLenVT = MVT::i64;
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    XLen = 64;
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  }
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  TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
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  RISCVFeatures::validate(TT, getFeatureBits());
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  return *this;
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}
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RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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                               StringRef ABIName, const TargetMachine &TM)
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    : RISCVGenSubtargetInfo(TT, CPU, FS),
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      FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
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      InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}